CS5467

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Technical content

Copyright  Cirrus Logic, Inc. 2011 (All Rights Reserved)http://www.cirrus.com CS5467 Four-channel Power/Energy IC Features & Description

• Energy Linearity: ±0.1% of Reading over 1000:1 Dynamic Range
• On-chip Functions: - Voltage and Current Measurement - Active, Reactive, and Apparent Power/Energy - RMS Voltage and Current Calculations - Current Fault and Voltage Sag Detection - Calibration - Phase Compensation - Temperature Sensor - Energy Pulse Outputs
• Meets Accuracy Spec for IEC, ANSI, & JIS
• Low Power Consumption
• Voltage Tamper Correction
• Ground-referenced Inputs with Single Supply
• On-chip 2.5 V Reference (40 ppm / °C typ.)
• Power Supply Monitor Function
• Three-wire Serial Interface to Microcontroller or E 2PROM
• Power Supply Configurations GND: 0 V, VA+: +5 V, VD+: +3.3 V to +5 V

Description

The CS5467 is a watt-hour meter on a chip. It measures line voltage and current and calcu- lates active, reactive, apparent power, energy, power factor, and RMS voltage and current. An internal RMS voltage reference can be used if voltage measurement is disabled by tampering. Four  analog-to-digital converters are used to measure two voltages and two currents. Option- ally, voltage2 channel can be used for temperature measurement. The CS5467 is designed to interface to a variety of voltage and current sensors. Additional features include system-level calibra- tion, voltage sag and current fault detection, peak detection, phase compensation, and ener- gy pulse outputs.

ORDERING INFORMATION

See Page 45. VA+ VD+ IIN1+ IIN1- VIN2+ VIN2- VREFIN VREFOUT AGND XIN XOUT CPUCLK DGND CS SDO SDI SCLK INT Voltage Reference System Clock /K Clock Generator Serial Interface E-to-F Power Monitor PFMON RESET Digital Filter Calibration MODE Power Calculation Engine 4th Order  Modulator 2nd Order  Modulator Temperature Sensor Digital FilterPGA HPF Option HPF Option x10 IIN2+ IIN2- 4th Order  Modulator Digital FilterPGA HPF Option VIN1+ VIIN1- Digital Filter 2nd Order  Modulator HPF Optionx10 JAN ‘11 DS714F3

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Figure 13. Typical Interface of E Table 4. E2

1. OVERVIEW The CS5467 is a CMOS power measurement integrated circuit utilizing four  analog-to-digital convert- ers to measure two line voltages and two currents. Optionally, voltage2 channel can be used for temper- ature measurement. It calculates active, reactive, and apparent power as well as RMS and peak voltage and current. It handles other system-related functions, such as pulse output conversion, voltage sag, cur- rent fault, voltage zero crossing, line frequency, and voltage tamper correction. The CS5467 is optimized to interface to current transformers or shunt resistors for current measurement, and to resistive dividers or voltage transformers for voltage measurement. Two full-scale ranges are pro- vided on the current inputs to accommodate both types of current sensors. The CS5467’s four differential inputs have a common-mode input range from anal og ground (AGND) to the positive analog supply (VA+). An additional analog input (PFMON) is provided to allow the application to determine when a power failure is in progress. By monitoring the unregulated power supply, the application can take any required action when a power loss occurs. An on-chip voltage reference (nominally 2.5 volts) is generated and provided at analog output, VREFOUT. This reference can be supplied to the chip by connecting it to the reference voltage input, VREFIN. Alter- natively, an external voltage reference can be supplied to the reference input. Three digital outputs (E1, E2, E3) provide a variety of output signals and, depending on the mode select- ed, provide energy pulses, power failure indication, or other choices. The CS5467 includes a three-wire serial host interface to an external microcontroller or serial E2PROM. Signals include serial data input (SDI), serial data output (SDO), serial clock (SCLK), and optionally a chip select (CS), which allows the CS5467 to share the SDO signal with other devices. A MODE input is used to control whether an E2PROM will be used instead of a host microcontroller.

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1. PIN DESCRIPTION Clock Generator Crystal Out Crystal In 1,28 XOUT, XIN — Connect to an external quartz crystal. Alternatively, an external clock can be sup- plied to the XIN pin to provide the system clock for the device. CPU Clock Output 2 CPUCLK — Logic-level output from cr ystal oscillator. Can be used to clock an external CPU. Control Pins and Serial Data I/O Serial Clock 5 SCLK — Clocks serial data from the SDI pin and to the SDO pin when CS is low. SCLK is a Schmitt-trigger input when MODE is low and a driven output when MODE is high. Serial Data Output 6 SDO — Serial data output. Data is clocked out by SCLK. Chip Select 7 CS — An input that enables the serial inte rface when MODE is low and a driven output when MODE is high. Mode Select 8 MODE — High selects external E 2PROM, Low selects external microcontroller. MODE includes a weak internal pull-down and therefore selects microcontroller mode if not connected. Energy Output 22, 25, E3, E1, E2 — Primarily active-low energy pulse outputs. These can be programmed to output other conditions. Reset 23 RESET — An active-low Schmitt-trigger input used to reset the chip. Interrupt 24 INT — Active-low output, indicates that an enabled condition has occurred. Serial Data Input 27 SDI — Serial data input. Data is clocked in by SCLK. Analog Inputs/Outputs Differential Voltage Inputs 9,10 13, 14 VIN1+, VIN1-, VIN2+, VIN2- — Differential analog inputs for the voltage channels. Differential Current Inputs 20,19, 16,15 IIN1+, IIN1-, IIN2+, IIN2- — Differential analog inputs for the current channels. Voltage Reference Output 11 VREFOUT — The on-chip voltage reference output. Nominally 2.5 V, referenced to AGND. Voltage Reference Input 12 VREFIN — The voltage reference input. Can be connected to VREFOUT or external 2.5 V refer- ence. Power Supply Connections Positive Digital Supply 3 VD+ — The positive digital supply. Digital Ground 4 DGND — Digital ground. Positive Analog Supply 18 VA+ — The positive analog supply. Analog Ground 17 AGND — Analog ground. Power Fail Monitor 21 PFMON — Used to monitor the unregulated power suppl y via a resistive divider. If the PFMON voltage drops below its low limit, the low-supply detect (LSD) bit is set in the Status register. VREFIN 12Voltage Reference Input VREFOUT 11Voltage Reference Output VIN1- 10Differential Voltage Input VIN1+ 9Differential Voltage Input MODE 8Mode Select CS 7Chip Select SDO 6Serial Data Ouput SCLK 5Serial Clock DGND 4Digital Ground VD+ 3Positive Digital Supply CPUCLK 2CPU Clock Output XOUT 1Crystal Out AGND17 Analog Ground VA+18 Positive Analog Supply IIN1-19 Differential Current Input IIN1+20 Differential Current Input PFMON21 Power Fail Monitor E322 Energy Output 3 RESET23 Reset INT24 Interrupt E125 Energy Output 1 SDI27 Serial Data Input XIN28 Crystal In E2 Energy Output 2 VIN2- 14Differential Voltage Input VIN2+ 13Differential Voltage Input IIN2-15 Differential Current Input IIN2+16 Differential Current Input

1. CHARACTERISTICS & SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS ANALOG CHARACTERISTICS

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V.
• DCLK = 4.096 MHz. Notes: 1. Applies when the HPF option is enabled. 2. Applies when the line frequency is equal to the produc t of the output word rate (OWR) and the value of Epsilon. Parameter Symbol Min Typ Max Unit Positive Digital Power Supply VD+ 3.135 5.0 5.25 V Positive Analog Power Supply VA+ 4.75 5.0 5.25 V Voltage Reference VREFIN - 2.5 - V Specified Temperature Range T A -40 - +85 °C Parameter Symbol Min Typ Max Unit Accuracy Active Power All Gain Ranges (Note 1) Input Range 0.1% - 100% PACTIVE -± 0 . 1- % Reactive Power All Gain Ranges (Note 1 and 2) Input Range 0.1% - 100% QAVG -± 0 . 2- % Power Factor All Gain Ranges (Note 1 and 2) Input Range 1.0% - 100% Input Range 0.1% - 1.0% PF - ±0.2 ±0.27 Current RMS All Gain Ranges (Note 1) Input Range 1.0% - 100% Input Range 0.1% - 1.0% IRMS - ±0.1 ±0.17 Voltage RMS All Gain Ranges (Note 1) Input Range 5% - 100% VRMS -± 0 . 1- % Analog Inputs (All Inputs) Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB Common Mode + Signal -0.25 - VA+ V Analog Inputs (Current Inputs) Differential Input Range (Gain = 10) [(IIN+) – (IIN-)] (Gain = 50) IIN - 500 100 mVP-P mVP-P Total Harmonic Distortion (Gain = 50) THD 80 94 - dB Crosstalk from Voltage input at Full Scale (50, 60 Hz) -- 1 1 5-d B Input Capacitance IC - 27 - pF Effective Input Impedance EII 30 - - k  Noise (Referred to Input) (Gain = 10) (Gain = 50) NI 22.5 4.5 µVrms µVrms Offset Drift (Without the High-pass Filter) OD - 4.0 - µV/°C Gain Error (Note 3) GE - ±0.4 %

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ANALOG CHARACTERISTICS (Continued) Notes: 3. Applies before system calibration. 4. All outputs unloaded. All inputs CMOS level. 5. Measurement method for PSRR: VREFIN ti ed to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to AGND. The CS5467 is then commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is (in dB): 6. When the voltage level on PFMON is sagging and LSD bit = 0, this is the voltage at which LSD is set to 1. 7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at which the LSD bit can be permanently reset back to 0. Parameter Symbol Min Typ Max Unit Analog Inputs (Voltage Inputs) Differential Input Range [(VIN+) – (VIN-)] VIN - 500 - mV P-P Total Harmonic Distortion THD 65 75 - dB Crosstalk from Current inputs at Full Scale Input Capacitance All Gain Ranges IC - 2.0 - pF Effective Input Impedance EII 2 - - M  Noise (Referred to Input) N V -- 1 4 0 µ V rms Offset Drift (Without the High-pass Filter) OD - 16.0 - µV/°C Gain Error (Note 3) GE - ±3.0 % Temperature Temperature Accuracy T - ±5 - °C Power Supplies Power Supply Currents (Active State) IA+ ID+ (VA+ = VD+ = 5 V) ID+ (VA+ = 5 V, VD+ = 3.3 V) PSCA PSCD PSCD 1.5 3.5 2.3 mA mA mA Power Consumption Active State (VA+ = VD+ = 5 V) (Note 4) Active State (VA+ = 5 V, VD+ = 3.3 V) Stand-by State Sleep State PC mW mW mW uW Power Supply Rejection Ratio (50, 60 Hz) (Note 5) Voltage Current (Gain = 50x) Current (Gain = 10x) PSRR 48 dB dB dB PFMON Low-voltage Trigger Threshold (Note 6) PMLO 2.3 2.45 - V PFMON High-voltage Power-on Trip Point (Note 7) PMHI - 2.55 2.7 V PSRR 20 150 Veq

Notes: 8. The voltage at VREFOUT is measured across th e temperature range. From these measurements the following formula is used to calculate the VREFOUT temperature coefficient. 9. Specified at maximum recommended output of 1 µA, source or sink. Parameter Symbol Min Typ Max Unit Reference Output Output Voltage VREFOUT +2.4 +2.5 +2.6 V Temperature Coefficient (Note 8) TCVREF - 40 - ppm/°C Load Regulation (Note 9) VR -6 1 0 m V Reference Input Input Voltage Range VREFIN +2.4 +2.5 +2.6 V Input Capacitance - 4 - pF Input CVF Current - 100 - nA (VREFOUTMAX - VREFOUTMIN) VREFOUTAVG( ( 1 TAMAX - TAMIN( ( 1.0 x 10( (6 TCVREF =

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• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
• DCLK = 4.096 MHz. Notes: 10. All measurements performed under static conditions. 11. If a crystal is used, XIN frequency must remain be tween 2.5 MHz - 5.0 MHz. If an external oscillator is used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz. 12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification. 13. The frequency of CPUCLK is equal to MCLK. 14. The minimum FSCR is limited by the maximum allowe d gain register value. The maximum FSCR is limited by the full-scale signal applied to the input. 15. Configuration register ( Config) bits PC[6:0] are set to “0000000”. 16. The MODE pin is pulled low by an internal resistor. Parameter Symbol Min Typ Max Unit Master Clock Characteristics Master Clock Frequency Internal Gate Oscillator (Note 11) DCLK 2.5 4.096 20 MHz Master Clock Duty Cycle 40 - 60 % CPUCLK Duty Cycle (Note 12 and 13) 40 - 60 % Filter Characteristics Phase Compensation Range Input Sampling Rate DCLK = MCLK/K - DCLK/8 - Hz Digital Filter Output Word Rate (Both channels) OWR - DCLK/1024 - Hz High-pass Filter Corner Frequency -3 dB -0 . 5 - H z Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR 25 - 100 %FS Channel-to-channel Time-shift Error (Note 15) 1.0 µs Input/Output Characteristics High-level Input Voltage All Pins Except XIN and SCLK and RESET XIN SCLK and RESET VIH

0.6 VD+

(VD+) – 0.5 0.8VD+ V V V Low-level Input Voltage (VD = 5 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET VIL 0.8 1.5 0.2VD+ V V V Low-level Input Voltage (VD = 3.3 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET VIL 0.48 0.3 0.2VD+ V V V High-level Output Voltage Iout = +5 mA VOH (VD+) - 1.0 - - V Low-level Output Voltage Iout =- 5m A( V D=+ 5 V ) Iout = -2.5 mA (VD = +3.3V) VOL - 0.4 0.4 V V Input Leakage Current (Note 16) Iin -± 1 ± 1 0 µ A 3-state Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -5 - p F

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
• Logic Levels: Logic 0 = 0 V, Logic 1 = VD+. Notes: 17. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 18. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. Parameter Symbol Min Typ Max Unit Rise Times (Note 17) Any Digital Output trise - 1.0 µs ns Fall Times (Note 17) Any Digital Output tfall - 1.0 µs ns Start-up Oscillator Start-up Time XTAL = 4.096 MHz (Note 18) tost -6 0- m s Serial Port Timing Serial Clock Frequency SCLK - - 2 MHz Serial Clock Pulse Width High Pulse Width Low 200 200 ns ns SDI Timing CS Falling to SCLK Rising t 3 50 - - ns Data Set-up Time Prior to SCLK Rising t 4 50 - - ns Data Hold Time After SCLK Rising t 5 100 - - ns SDO Timing CS Falling to SDO Driving t 6 -2 0 5 0 n s SCLK Falling to New Data Bit (hold time) t 7 -2 0 5 0 n s CS Rising to SDO Hi-Z t 8 -2 0 5 0 n s E2PROM mode Timing Serial Clock Pulse Width Low Pulse Width High t10 DCLK DCLK MODE setup time to RESET Rising t 11 50 ns RESET rising to CS falling t 12 48 DCLK CS falling to SCLK rising t 13 100 8 DCLK SCLK falling to CS rising t 14 16 DCLK CS rising to driving MODE low t 15 50 ns SDO setup time to SCLK rising t 16 100 ns

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Figure 1. CS5467 Read and Write Timing Diagrams

6.7 Energy Pulse Outputs on page 20 for more information on pulse output pins.

1. Timing is proportional to the frequency of DCLK.

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 21. VA+ and AGND must satisfy [(VA+) - (AGND)]  + 6.0 V.

1. VD+ and AGND must satisfy [(VD+) - (AGND)]  + 6.0 V.
2. Applies to all pins including continuous over-v oltage conditions at the analog input pins.
3. Transient current of up to 10 0 mA will not cause SCR latch-up.
4. Maximum DC input current for a power supply pin is ±50 mA.
5. Total power dissipation, including all input currents and output currents.

Figure 2. Timing Diagram for E1, E2, and E3

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the other calculations are shown in Figures 3, 4, and 5.

4.1 Analog-to-Digital Converters

streams. The converters sa mple at a rate of DCLK/8. simplifies anti-alias filter design.

4.2 Decimation Filters

tude roll-off of the decimation filters.

4.3 Phase Compensation

4000 Hz, the delay range is ±250 uS, a phase shift of

Figure 3. Signal Flow for V1, I1, P1, Q1 Measurements Figure 4. Signal Flow for V2, I2, P2, Q2 Measurements

4.4 DC Offset and Gain Correction

The system and chip inherently have gain and offset er- rors which can be removed using the gain and offset registers. (See Section 9. System Calibration on page 40). Each measurement channel has its own registers. For every channel, the output of the IIR filter is added to the offset register and multiplied by the gain register.

4.5 High-pass Filters

Optional high-pass filters (HPF in Figures 3 and 4) re- move any DC from the selected signal paths. Subse- quently, DC will also be removed from power, and all low-rate results. (see Figures 5). Each energy channel has a current and voltage path. If an HPF is enabled in only one path, a phase-matching filter (PMF) is applied to the other path which matches the amplitude and phase delay of the HPF in the band of interest, but passes DC. For more information, see 6.5 High-pass Filters on page 20. The HPF filter multi- plexers drive the I1, V1, I2, and V2 result registers.

4.6 Low-Rate Calculations

Low-rate results are derived from sample-rate results integrated over N samples, where N is the value stored in the Cycle Count register. The low-rate interval is the sample interval multiplied by

4.7 RMS Results

The root mean square ( RMS in Figure 5) calculations are performed on N instantaneous voltage and current samples, using the formula: IRMS In n0= N1–

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4.8 Power and Energy Results

factor is determined by the active power. Epsilon register, which is based on line frequency. Figure 5. Low-rate Calculations Figure 6. Two-channel Power Summation

4.9 Peak Voltage and Current

Peak current ( I1PEAK, I2PEAK) and peak voltage (V1PEAK, V2PEAK) are the largest current and voltage samples detected in the previous low-rate interval.

4.10 Power Offset

The power offset registers, P1OFF (P2OFF) can be used to offset erroneous power sources resident in the sys- tem not originating from the power line. Residual power offsets are usually caused by crosstalk into current paths from voltage paths or from ripple on the meter or chip’s power supply, or from inductance from a nearby transformer. These offsets can be either positive or negative, indicat- ing crosstalk coupling either in phase or out of phase with the applied voltage input. The power offset regis- ters can compensate for either condition. To use this feature, meas ure the average power at no load using either Single or Continuous Conversion com- mands. Take the measured result (from the P1AVG (P2AVG) register), invert (negate) the value and write it to the associated power offset register, P1OFF (P2OFF).

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5.1 Analog Pins

reference output are also available.

5.1.1 Voltage1 & Voltage2 Inputs

ly 70.7% of maximum peak voltage.

5.1.2 Current1 & Current2 Inputs

mately 70.7% of maximum peak voltage.

5.1.3 Power Fail Monitor Input

of the voltage reference input (VREFIN).

5.1.4 Voltage Reference Input

is recommended at the VREFIN pin.

5.1.5 Voltage Reference Output

The CS5467 generates a 2.5 V reference (VREFOUT).

5.1.6 Crystal Oscillator

5.2 Digital Pins

5.2.1 Reset Input

quence begins, setting default register values.

5.2.2 CPU Clock Output

troller clock. Two phase choices are available.

5.2.3 Interrupt Output

5.2.4 Energy Pulse Outputs

Figure 7. Oscillator Connections

5.2.5 Serial Interface

The CS5467 provides 5 pins, SCLK, SDI, SDO, CS, and MODE for communication between a host microcon- troller or serial E 2PROM and the CS5467. MODE is an input that, when high, indicates to the CS5467 that a serial E2PROM is being used instead of a host microcontroller. It has a weak pull-down allowing it to be left unconnected if microcontroller mode is used. SCLK is used to shift and qualify serial data. Serial data changes as a result of t he falling edge of SCLK and is valid during the rising edge. It is a Schmitt-trigger input for host microcontrollers, and a driven output for serial E 2PROMs. SDI is the serial data input to the CS5467. SDO is the serial data output from the CS5467. It’s out- put drivers are disabled whenever CS is de-asserted, al- lowing other devices to drive the SDO line. CS is the chip select input for the serial bus. A high logic level de-asserts it, tri-stating the SDO pin and clearing the serial interface. A low logic level enables the serial port. This pin may be tied low for systems not requiring multiple SDO drivers. CS is a driven output when inter- facing to serial E2PROMs.

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6.1 Clock Divider

requiring a faster clock and using the CPUCLK output.

6.2 CPU Clock Inversion

6.3 Interrupt Pin Behavior

and IINV bits in the Configuration register as shown. DCLK cycles, where DCLK = MCLK/K.

6.4 Current Input Gain Ranges

range of the current inputs.

6.5 High-pass Filters

HPF in the band of interest, but passes DC.

6.6 Cycle Count

6.7 Energy Pulse Outputs

ride others, so read the following paragraphs carefully. E2MODE[1:0] in the Modes register. Note: E2MODE[1:0]=3 is a special mode. monitor status, voltage1 sign, or total apparent energy.

10 L o w P u l s e

11 H i g h P u l s e

Table 1. Interrupt Configuration Table 2. Current Input Gain Ranges Table 3. High-pass Filter Configuration Table 4. E2 Pin Configuration

6.8 No Load Threshold

their magnitude is less than the LoadMIN register value.

6.9 Energy Pulse Width

E1, E2, or E3 pins that are configured to output pulses. sign, pulse widths and output rates do not apply.

4000 Hz (a period of 250 uS) t pw = PulseWidth x

250 uS. By default, PulseWidth is set to 1.

6.10 Energy Pulse Rate

EPULSE, SPULSE, or QPULSE) value.

6.11 Voltage Sag/Current Fault Detection

mined level for a specified interval of time. fault) disables the detect feature for the given channel. Table 5. E3 Pin Configuration Table 6. E1 / E2 Modes Table 7. E3 Pin with E1MODE enabled

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rectified and compared to the associated level register .

6.12 Epsilon

phase shift used in the quadrature power calculation. output word rates (OWR) can be used. has been automatically updated.

6.13 Temperature Measurement

a transistor to determine temperature. range of ±128 degrees on the Celsius (°C) scale. Gain (TGAIN) and Temperature Offset (TOFF) registers. tions of the binary point of these registers. These are the actual default values for these registers. er. (See Section 9. System Calibration on page 40). degrees to cover the -40°C to +85°C range. Figure 8. Sag and Fault Detect

7.1 Initialization

application circuit to reset the part. cates when the initialization program has completed.

7.2 Power-down States

sleep mode, a complete initialization occurs.

7.3 Voltage Tamper Correction

Figure 9. Fixed RMS Voltage Selection

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7.4 Command Interface

Commands and data are transferred most-significant bit (MSB) first. Figure 1 on page 12, defines the serial port timing. Commands are clocked in on SDI using SCLK. They are a single byte (8 bits) long and fall into one of four basic types: 1. Register Read 2. Register Write 3. Synchronizing 4. Instructions Register reads will cause up to four bytes of register data to be clocked out, MSB first on the SDO pin by SCLK. During this time, other commands can be clocked in on the SDI pin. Other commands will not in- terrupt read data, except another register read, which will cause the new read data to appear on SDO. Synchronizing can be sent while read data is being clocked out if no other commands need to be sent. Synchronizing commands are also used to synchronize the serial port to a byte boundary. The CS and RESET pins will also synchronize the serial port. Register writes require three bytes of write data to fol- low, clocked in on the SDI pin, MSB first by SCLK. Instructions are commands that will interrupt any in- struction currently executing and begin the new instruc- tion. These include conversions, calibrations, power control, and soft reset. (See Section 7.6 Commands on page 25).

7.5 Register Paging

Read and Write commands access one of 32 registers within a specified page. The Register Page Select reg- ister’s ( Page) default value is 0. To access registers in another page, write the desired page number to the Page register. The Page register is always at address 31 and is accessible from within any page.

7.6 Commands

All commands are 1 byte (8 bits) long. Many command values are unused and should NOT be written by the application program. All commands except register reads, register writes, or synchronizing commands will abort any conversion, calibration, or any initialization sequence currently executing. This includes reset. No commands other than reads or synchronizing should be executed until the reset sequence completes.

7.6.1 Conversion

Executes a conversion (measurement) program. CC Continuous/Single Conversion 0 = Perform a Single Conversion (0xE0) 1 = Perform Continuous Conversion (0xE8)

7.6.2 Synchronization (SYNC0 and SYNC1)

The serial interface is bidirectional. While reading data on the SDO output, the SDI input must be receiving commands. If no command is needed during a read, SYNC0 or SYNC1 commands can be sent while read data is received on SDO. The serial port is normally initialized by de-asserting CS . An alternative method of initialization is to send 3 or more SYNC1 commands followed by a SYNC0. This is useful in systems where CS is not used and tied low.

7.6.3 Power Control (Stand-by, Sleep, Wake-up/Halt and Software Reset)

The CS5467 has two power-down states, stand-by and sleep. In stand-by, all circuitry except the voltage ref- erence and clocks are turned off. In sleep mode, all circuitry except the command decoder is turned off. A Wake-up/Halt command restores full-power operation after stand-by and issues a hardware reset after sleep. The Software Reset command is a program that emulates a pin reset and is not a power control function. S[1:0] 00 = Software Reset 01 = Sleep 10 = Wake-up/Halt 11 = Stand-by B7 B6 B5 B4 B3 B2 B1 B0

1110 C C 000

1111111 S Y N C

10 S 1 S 0 0000

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7.6.4 Calibration

The CS5467 can perform gain and offset calibrations using either DC or AC signals. Proper input levels must be applied to the current inputs and voltage input before performing calibrations. CAL[5:4]* 00 = DC Offset 01 = DC Gain 10 = AC Offset 11 = AC Gain CAL[3:0] 0001 = Current for Channel 1 0010 = Voltage for Channel 1 0100 = Current for Channel 2 1000 = Voltage for Channel 2 Note: Anywhere from 1 to all 4 channels can be calibrated simultaneously. B7 B6 B5 B4 B3 B2 B1 B0 1 0 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

7.6.5 Register Read and Write

Read and Write commands provide access to on-chip registers. After a Read command, the addressed data can be clocked out the SDO pin by SCLK. After a Write command, 24 bits of write data must follow. The data is transferred to the addressed register after the 24th data bit is received. Registers are organized into pages of 32 addresses each. To access a desired page, write its number to the Page register at address 31. W/R Write/Read control 0 = Read 1 = Write RA[4:0] Register address. Page 0 Registers Address RA[4:0] Name Description 0 00000 Config Configuration 1 00001 I1 Instantaneous Current Channel 1 2 00010 V1 Instantaneous Voltage Channel 1 3 00011 P1 Instantaneous Power Channel 1 4 00100 P1 AVG Active Power Channel 1 5 00101 I1 RMS RMS Current Channel 1 6 00110 V1 RMS RMS Voltage Channel 1 7 00111 I2 Instantaneous Current Channel 2 8 01000 V2 Instantaneous Voltage Channel 2 9 01001 P2 Instantaneous Power Channel 2 10 01010 P2 AVG Active Power Channel 2 11 01011 I2 RMS RMS Current Channel 2 12 01100 V2 RMS RMS Voltage Channel 2 13 01101 Q1 AVG Reactive Power Channel 1 14 01110 Q1 Instantaneous Quadrature Power Channel 1 15 01111 Status Internal Status 16 10000 Q2 AVG Reactive Power Channel 2 17 10001 Q2 Instantaneous Quadrature Power Channel 2 18 10010 I1 PEAK Peak Current Channel 1 19 10011 V1 PEAK Peak Voltage Channel 1 20 10100 S1 Apparent Power Channel 1 21 10101 PF1 Power Factor Channel 1 22 10110 I2 PEAK Peak Current Channel 2 23 10111 V2 PEAK Peak Voltage Channel 2 24 11000 S2 Apparent Power Channel 2 25 11001 PF2 Power Factor Channel 2 26 11010 Mask Interrupt Mask 27 11011 T Temperature 28 11100 Ctrl Control 29 11101 E PULSE Active Energy Pulse Output 30 11110 S PULSE Apparent Energy Pulse Output

31 R 11111 Q PULSE Reactive Energy Pulse Output

31 W 11111 Page Register Page Select

Warning: Do not write to unpublished register locations. B7 B6 B5 B4 B3 B2 B1 B0 0W / R RA4 RA3 RA2 RA1 RA0 0

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Address RA[4:0] Name Description 0 00000 I1 OFF Current DC Offset Channel 1 1 00001 I1 GAIN Current Gain Channel 1 2 00010 V1 OFF Voltage DC Offset Channel 1 3 00011 V1 GAIN Voltage Gain Channel 1 4 00100 P1 OFF Power Offset Channel 1 5 00101 I1 ACOFF Current AC (RMS) Offset Channel 1 6 00110 V1 ACOFF Voltage AC (RMS) Offset Channel 1 7 00111 I2 OFF Current DC Offset Channel 2 8 01000 I2 GAIN Current Gain Channel 2 9 01001 V2 OFF Voltage DC Offset Channel 2 10 01010 V2 GAIN Voltage Gain Channel 2 11 01011 P2 OFF Power Offset Channel 2 12 01100 I2 ACOFF Current AC (RMS) Offset Channel 2 13 01101 V2 ACOFF Voltage AC (RMS) Offset Channel 2 14 01110 PulseWidth Pulse Output Width 15 01111 PulseRate Pulse Output Rate (frequency) 16 10000 Modes Mode Control 17 10001 Epsilon Ratio of Line to Sample Frequency 19 10011 N Cycle Count (Number of OWR Samples in One Low-rate Interval) 20 10100 Q1 WB Wideband Reactive Power from Power Triangle Channel 1 21 10101 Q2 WB Wideband Reactive Power from Power Triangle Channel 2 22 10110 T GAIN Temperature Sensor Gain 23 10111 T OFF Temperature Sensor Offset 25 11001 T SETTLE Filter Settling Time for Conversion Startup 26 11010 Load MIN No Load Threshold 27 11011 VF RMS Voltage RMS Fixed Reference 28 11100 G System Gain 29 11101 Time System Time (in samples) RA[4:0] Name Description 0 00000 V1Sag DUR V Sag Duration Channel 1 1 00001 V1Sag LEVEL V Sag Level Channel 1 4 00100 I1Fault DUR I Fault Duration Channel 1 5 00101 I1Fault LEVEL I Fault Level Channel 1 8 01000 V2Sag DUR V Sag Duration Channel 2 9 01001 V2Sag LEVEL V Sag Level Channel 2 12 01100 I2Fault DUR I Fault Duration Channel 2 13 01101 I2Fault LEVEL I Fault Level Channel 2 Address RA[4:0] Name Description 26 11010 T MEAS Temperature Measurement Warning: Do not write to unpublished register locations.

1. REGISTER DESCRIPTIONS 1. “Default” = bit states after power-on or reset 2. DO NOT write a “1” to any unpublished register bit. 3. DO NOT write to any unpublished register address.

8.1 Page Register

8.1.1 Page – Address: 31, Write-only, can be written from ANY page. Default = 0 Register Read and Write commands contain only 5 address bits. But the internal address bus of the CS5467 is 12 bits wide. Therefore, registers are organized into “Pages”. There are 128 pages of 32 registers each. The Page register provides the 7 high-order address bits and selects one of the 128 register pages. Not all pages are used, Page is a write-only integer containing 7 bits.

8.2 Page 0 Registers

8.2.1 Configuration (Config) – Address: 0

Default = 1 (K=1) PC[7:0] Phase compensation for channel 1. Sets a delay in voltage, relative to current. Phase is signed and in the range of -1.0  value  1.0 sample (OWR) intervals. EWA Allows the E1 and E2 pins to be configured as open-drain outputs. 0 = Normal Outputs 1 = Open-drain Outputs IMODE, IINV Interrupt configuration. Selects INT pin behavior. 00 = Low Logic Level When Asserted 01 = High Logic Level When Asserted 10 = Low-going Pulse on New Interrupt 11 = High-going Pulse on New Interrupt iCPU Inverts the CPUCLK output. 0=D e f a u l t 1 = Invert CPUCLK. K[3:0] Clock divider. Divides MCLK by K to gene rate internal clock DCLK. (DCLK = MCLK/K). K is unsigned and in the range of 1 to 16. When zero, K = 16. At reset, K = 1. MSB LSB 26 25 24 23 22 21 20 23 22 21 20 19 18 17 16 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 15 14 13 12 11 10 9 8 EWA - - IMODE IINV - - - 76543210 - - -i C P U K 3K 2K 1K 0

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8.2.2 Instantaneous Current (I1, I2), Voltage (V1, V2), and Power (P1, P2)

I1 (I2) and V1 (V2) contain instantaneous current and voltage, respectively, which are multiplied to yield instan- taneous power, P1 (P2). These are two's complement values in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

8.2.3 Active Power (P1AVG , P2AVG )

Address: 4 (P1AVG ), 10 (P2AVG ) Instantaneous power is averaged over each low-rate interval (N samples) to compute active power, P1AVG (P2AVG). These are two's complement values in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

8.2.4 RMS Current (I1RMS , I2RMS ) and Voltage (V1RMS , V2RMS )

Address: 5 (I1RMS), 6 (V1RMS), 11 (I2RMS), 12 (V2RMS) I1RMS (I2RMS) and V1RMS (V2RMS) contain the root mean square (RMS) values of I1 (I2) and V1 (V2), calcu- lated each low-rate interval. These are unsigned values in the range of 0  value  1.0, with the binary point to the left of the MSB.

8.2.5 Instantaneous Quadrature Power (Q1, Q2)

Address: 14 (Q1), 17 (Q2) Instantaneous quadrature power, Q1 (Q2), the product of voltage1 (voltage2) shifted 90 degrees and current1 (current2). These are two's complement values in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

8.2.6 Reactive Power (Q1Avg , Q2AVG )

Address: 13 (Q1AVG), 16 (Q2AVG) Reactive power Q1AVG (Q2AVG) is Q1 (Q2) averaged over every N samples. These are two's complement values in the range of -1.0  value  1.0, with the binary point to the right of the MSB. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

8.2.7 Peak Current (I1PEAK, I2PEAK ) and Peak Voltage (V1PEAK, V2PEAK )

Address: 18 (I1PEAK), 19 (V1PEAK), 22 (I2PEAK), 23 (V2PEAK) Peak current, I1PEAK (I2PEAK) and peak voltage, V1PEAK (V2PEAK) are the instantaneous current and voltage samples with the greatest magnitude detected during the last low-rate interval. These are two's complement values in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

8.2.8 Apparent Power (S1, S2)

Address: 20 (S1), 24 (S2) Apparent power S1 (S2) is the product of V1RMS and I1RMS (V2RMS and I2RMS), These are two's complement values in the range of 0  value  1.0, with the binary point to the right of the MSB.

8.2.9 Power Factor (PF1, PF2)

Address: 21 (PF1), 25 (PF2) Power factor is calculated by dividing active power by apparent power. The sign is determined by the active power sign. These are two's complement values in the range of -1.0 value  1.0, with the binary point to the right of the MSB.

8.2.10 Temperature (T) – Address: 27

T contains results from the on-chip temperature measurement. By default, T uses the Celsius scale, and is a two's complement value in the range of -128.0  value  128.0 (oC), with the binary point to the right of bit 16. T can be rescaled by the application using the TGAIN and TOFF registers.

8.2.11 Active, Apparent, and Reactive Energy Pulse Outputs (EPULSE , SPULSE , QPULSE )

Address: 29 (EPULSE), 30 (SPULSE), 31 (QPULSE) These drive the pulse outputs when configured to do so. These are two's complement values in the range of -1.0  value  1.0, with the binary point to the right of the MSB. Refer to 4.8 Power and Energy Results on page 16. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

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8.2.12 Internal Status (Status) and Interrupt Mask (Mask)

Address: 15 (Status); 26 (Mask) Default = 1 ( Status), 0 (Mask) The Status register indicates a variety of conditions within the chip. Writing a '1' to a Status register bit will clear that bit if the condition that set it has been removed. Writing a '0' to any bit has no effect. The Mask register is used to control the activation of the INT pin. Writing a '1' to a Mask register bit will allow the corresponding Status register bit to activate the INT pin when set. DRDY Data Ready. During conversion, this bit indi cates that low-rate results have been updated. It indicates completion of other commands and the reset sequence. I1OR (I2OR) Current Out of Range. Set w hen the measured current would cause the I1 (I2) register to overflow. V1OR (V2OR) Voltage Out of Range. Set when the measured voltage would cause the V1 (V2) register to overflow. CRDY Conversion Ready. Indicates that sample rate (output word rate) results have been updat- ed. I1ROR (I2ROR) RMS Current Out of Range. Set when RMS current would cause the I1RMS (I2RMS) regis- ter to overflow. V1ROR (V2ROR) RMS Voltage Out of Range. Set when RMS voltage would cause the V1RMS (V2RMS) reg- ister to overflow. E1OR (E2OR) Energy Out of Range. Set when average power would cause P1AVG (P2AVG) to overflow. I1FAULT (I2FAULT)Indicates when a current fault condition has occurred. V1SAG (V2SAG) Indicates when a voltage sag condition has occurred. TUP Indicates when the Temperature register ( T) has been updated. V1OD (V2OD) Modulator oscillation has been detected in the voltage1 (voltage2) A/D. I1OD (I2OD) Modulator oscillation has been detected in the current1 (current2) A/D. LSD Low Supply Detect. Set when the voltage on the PFMON pin falls below the specified low level. The LSD bit cannot be reset until the voltage rises above the specified high level. FUP Frequency Updated. Indicates the Epsilon register has been updated. IC Invalid Command. Normally logic 1. Set to 0 when an invalid command is received. It may also indicate loss of serial command synchronization and the part may need to be re-ini- tialized. 23 22 21 20 19 18 17 16 DRDY I2OR V2OR CRDY I2ROR V2ROR I1OR V1OR 15 14 13 12 11 10 9 8 E2OR I1ROR V1ROR E1OR I1FAULT V1SAG I2FAULT V2SAG 76543210 T U P V 2 O DI 2 O DV 1 O DI 1 O D L S D F U P IC

8.2.13 Control (Ctrl) – Address: 28

Default = 0 PC[7:0] Phase compensation for channel 2. Sets a delay in voltage relative to current. Phase is signed and in the range of -1.0  value  1.0 sample (OWR) intervals. I1gain (I2gain) Sets the gain of the current1 (current2) input. 0 = Gain is set for ±250mV range. 1 = Gain is set for ±50mV range. STOP Terminates E 2PROM command sequence (if used). 0 = No Action 1 = Stop E 2PROM Commands. INTOD Converts INT output pin to an open drain output. 0 = Normal Output 1 = Open-drain Output NOCPU Saves power by disabling the CPUCLK output pin. 0 = CPUCLK Enabled 1 = CPUCLK Disabled NOOSC Disables the crystal oscillator, making XIN a logic-level input. 0 = Crystal Oscillator Enabled 1 = Crystal Oscillator Disabled 23 22 21 20 19 18 17 16 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 15 14 13 12 11 10 9 8 --- I 2 g a i n --- S T O P 76543210 - - I1gain INTOD - NOCPU NOOSC -

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8.3 Page 1 Registers

8.3.1 DC Offset for Current (I1OFF , I2OFF ) and Voltage (V1OFF , V2OFF )

Address: 0 (I1OFF ), 2 (V1OFF ), 7 (I2OFF ), 9 (V2OFF ) Default = 0 DC offset registers I1OFF & V1OFF (I2OFF & V2OFF ) are initialized to zero on reset. During DC offset calibra- tion, selected registers are written with the inverse of the DC offset measured. The application program can also write the DC offset register values. These are two's complement values in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

8.3.2 Gain for Current (I1GAIN , I2GAIN ) and Voltage (V1GAIN , V2GAIN )

Address: 1 (I1GAIN ), 3 (V1GAIN ), 8 (I2GAIN ), 10 (V2GAIN ) Default = 1.0 Gain registers I1GAIN & V1GAIN (I2GAIN & V2GAIN) are initialized to 1.0 on reset. During AC or DC gain calibra- tion, selected register are written with the multiplicative inverse of the gain measured. These are unsigned fixed-point values in the range of 0  value  4.0, with the binary point to the right of the second MSB.

8.3.3 Power Offset (P1OFF , P2OFF )

Address: 4 (P1OFF ), 11 (P2OFF ) Default = 0 Power offset P1OFF (P2OFF ) is added to instantaneous power and averaged over a low-rate interval to yield P1AVG (P2AVG ) register results. It can be used to reduce systematic energy errors. These are two's comple- ment values in the range of -1.0  value  1.0, with the binary point to the right of the MSB.

8.3.4 AC Offset for Current (I1ACOFF , I2ACOFF ) and Voltage (V1ACOFF , V2ACOFF )

Address: 5 (I1ACOFF ), 6 (V1ACOFF ), 12 (I2ACOFF ), 13 (V2ACOFF ) Default = 0 AC offset registers I1ACOFF & V1ACOFF (VACOFF & V2ACOFF ) are initialized to zero on reset. These are added to the RMS results before being stored to the RMS result registers. They can be used to reduce systematic errors in the RMS results. These are two's complement values in the range of -1.0  value  1.0, with the bi- nary point to the right of the MSB. MSB LSB MSB LSB MSB LSB MSB LSB

8.3.5 Mode Control (Modes) – Address: 16

Default = 0 VFIX Use internal RMS voltage reference instead of voltage input for average active power. 0 = Use voltage input. 1 = Use internal RMS voltage reference, VFRMS. E1MODE[1:0] E1 , E2, and E3 alternate output mode (when enabled by E2MODE). 00 = E1, E2 = P1AVG, P2AVG 01 = E1, E2 = S1, S2 10 = E1, E2 = Q1AVG, Q2AVG 11 = E1, E2 = Q1WB, Q2WB E2MODE[1:0] E2 Output Mode 00 = Energy Sign 01 = Total Apparent Energy 10 = Not Used 11 = Enable E1MODE VHPF2:IHPF2 High-pass Filter Enable for Energy Channel 2 00 = No Filter 01 = HPF on Current, PMF on Voltage 10 = HPF on Voltage, PMF on Current 11 = HPF on both Voltage and Current VHPF1:IHPF1 High-pass Filter Enable for Energy Channel 1 00 = No Filter 01 = HPF on Current, PMF on Voltage 10 = HPF on Voltage, PMF on Current 11 = HPF on both Voltage and Current E3MODE[1:0] E3 Output Mode (with E1MODE disabled) 00 = Total Reactive Energy (default) 01 = Power Fail Monitor 10 = Voltage1 Sign 11 = Total Apparent Energy E3MODE[1:0] E3 Output Mode (with E1MODE enabled) 00 = Power Fail Monitor 01 = Energy Sign 10 = Not Used 11 = Not Used POS Positive Energy Only. Suppresses negative values in P1AVG and P2AVG. If a negative value is calculated, zero will be stored instead. AFC Enables automatic line frequency measurement which sets Epsilon every time a new line frequency measurement completes. Epsilon is used to control the gain of the 90 degree phase shift integrator used in quadrature power calculations. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 - E1MODE1 E1MODE0 - - E2MODE1 E2MODE0 VHPF2 76543210 IHPF2 VHPF1 IHPF1 - E3MODE1 E3MODE0 POS AFC

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8.3.6 Line to Sample Frequency Ratio (Epsilon) – Address: 17

Default = 0.0125 (4.0 kHz x 0.0125 or 50 Hz) Epsilon is the ratio of the input line frequency to the output word rate (OWR). It can either be written by the ap- plication program or calculated automatically from the line frequency (from the voltage input) using the AFC bit in the Modes register. It is a two's complement value in the range of -1.0  value  1.0, with the binary point to the right of the MSB. Negative values are not used.

8.3.7 Pulse Output Width (PulseWidth) – Address: 14

Default = 1 (250 uS at OWR = 4 kHz) PulseWidth sets the duration of energy pulses. The actual pulse duration is the contents of PulseWidth divided by the output word rate (OWR). PulseWidth is an integer in the range of 1 to 8,388,607.

8.3.8 Pulse Output Rate (PulseRate) – Address: 15

Default= -1 PulseRate sets the full-scale frequency for E1, E2, E3 pulse outputs. For a 4 kHz sample rate, the maximum pulse rate is 2 kHz. This is a two's complement value in the range of -1  value  1, with the binary point to the left of the MSB. Refer to 6.10 Energy Pulse Rate on page 21 for more information.

8.3.9 Cycle Count (N) – Address: 19

Default = 4000 Determines the number of output word rate (OWR) samples to use in calculating low-rate results. Cycle Count (N) is an integer in the range of 10 to 8,388,607. Values less than 10 should not be used.

8.3.10 Wideband Reactive Power (Q1WB , Q2WB )

Address: 20 (Q1WB ), 21 (Q2WB ) Wideband reactive power is calculated using vector subtraction. (See Section 4.8 Power and Energy Results on page 16). The value is signed, but has a range of 0 value  1.0. The binary point is to the right of the MSB. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

8.3.11 Temperature Gain (TGAIN ) – Address: 22

Default = 0x2F02C3 Refer to 6.13 Temperature Measurement on page 22 for more information.

8.3.12 Temperature Offset (TOFF ) – Address: 23

Default = 0xF3D35A Refer to 6.13 Temperature Measurement on page 22 for more information.

8.3.13 Filter Settling Time for Conversion Startup (TSETTLE ) – Address: 25

Default = 30 Sets the number of output word rate (OWR) samples that will be used to allow filters to settle at the beginning of Conversion and Calibration commands. This is an integer in the range of 0 to 8,388,607 samples.

8.3.14 No Load Threshold (LoadMIN ) – Address: 26

Default = 0 LoadMIN is used to set the no load threshold. When the magnitude of the EPULSE register is less than LoadMIN, EPULSE will be zeroed. If the magnitude of the QPULSE register is less than LoadMIN, Qpulse will be zeroed. LoadMIN is a two’s compliment value in the range of -1.0 value  1.0, with the binary point to the right of the MSB. Negative values are not used.

8.3.15 Voltage Fixed RMS Reference (VFRMS ) – Address 27

Default = 0.7071068 (full scale RMS) If the application program detects that the meter has possibly been tampered with in such a manner that the voltage input is no longer working, it may choose to use this internal RMS reference instead of the disabled voltage input by setting the VFIX bit in the Modes register. This is a two's complement value in the range of 0  value  1.0, with the binary point to the right of the MSB. Negative values are not used. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

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8.3.16 System Gain (G) – Address: 28

Default = 1.25 System Gain (G) is applied to all channels. By default, G = 1.25, but can be finely adjusted to compensate for voltage reference error. It is a two's complement value in the range of -2.0 value  2.0, with the binary point to the right of the second MSB. Values should be kept within 5% of 1.25.

8.3.17 System Time (Time) – Address: 29

Default = 0 System Time (Time) is measured in output word rate (OWR) samples. This is an unsigned integer in the range of 0 to 16,777,215 samples. At OWR = 4.0 kHz, OWR will overflow every 1 hour, 9 minutes, and 54 seconds. Time can be used by the application to manage real-time events. MSB LSB MSB LSB

8.4 Page 2 Registers

8.4.1 Voltage Sag and Current Fault Duration (V1SagDUR , V2SagDUR , I1FaultDUR , I2FaultDUR )

Address: 0 (V1SagDUR ), 8 (V2SagDUR ), 4 (I1FaultDUR ), 12 (I2FaultDUR ) Default = 0 Voltage sag duration, V1SagDUR (V2SagDUR) and current fault duration, I1FaultDUR (I2FaultDUR) determine the count of output word rate (OWR) samples utilized to determine a sag or fault event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature.

8.4.2 Voltage Sag and Current Fault Level (V1SagLEVEL , V2SagLEVEL , I1FaultLEVEL , I2FaultLEVEL )

Address: 1 (V1SagLEVEL ), 9 (V2SagLEVEL ), 5 (I1FaultLEVEL ), 13 (I2FaultLEVEL ) Default = 0 Voltage sag level, V1SagLEVEL (V2SagLEVEL ) and current fault level, I1FaultLEVEL (I2FaultLEVEL ) establish an input level below which a sag or fault is triggered. These are two's complement values in the range of -1.0  value  1.0, with the binary point to the right of the MSB. Negative values are not used.

8.5 Page 5 Register

8.5.1 Temperature Measurement (TMEAS ) – Address: 26

Default = 0 The Temperature Measurement (TMEAS) register is used to cycle-steal voltage channel2 for temperature measurement. Writing a one to the LSB causes the temperature to be measured and the Temperature register (T) to be updated. Refer to 6.13 Temperature Measurement on page 22 for more information. MSB LSB MSB LSB MSB LSB

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9.1 Calibration

the voltage and current RMS calculations. tion can be performed on any channel independently. The data flow of the calibration is shown in Figure 10.

9.1.1 Offset Calibration

VIN2 or current inputs IIN1  (IIN2of the CS5467.

9.1.1.1 DC Offset Calibration

set to 1.0 prior to performing DC offset calibration.

9.1.1.2 AC Offset Calibration

first be cleared prior to performing the calibration. = READABLE/WRITABLE REGISTERS. Figure 10. Calibration Data Flow Figure 11. System Calibration of Offset

9.1.2 Gain Calibration

Figure 12 shows the basic setup for gain calibration. levels during calibration or normal operation.

9.1.2.1 AC Gain Calibration

9.1.2.2 DC Gain Calibration

quent conversions will use the new gain value.

9.1.3 Calibration Order

as AC gain and offset may interact.

9.1.4 Temperature Sensor Calibration

be known in order to calibrate the temperature sensor. culate TGAIN and TOFF register values from them.

9.1.4.1 Temperature Offset Calibration

should be done mid-scale if any gain error exists. VBE0 value. Recalculate TOFF using this new value.

9.1.4.2 Temperature Gain Calibration

quired to calibrate temperature gain. T register) difference fo r the two temperatures. register by multiplying it’s value by this correction factor. Figure 12. System Calibration of Gain.

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makes the CS and SCLK pins become driven outputs.

10.1 E2PROM Configuration

2PROM is shown in Figure 13. sends Read commands to the E2PROM on SDO.

10.2 E2PROM Code

1. Set any Configuration or Control register bits, such as

HPF enables and phase compensation settings.

1. Write any calibration data to gain and offset registers.
2. Set energy output pulse width, rate, and formats.
3. Execute a Continuous Conversion command.
4. Set the STOP bit in the Control register (last).

Write Modes Register, turn high-pass filters on. Write value of 0x7FC4A9 to I1GAIN register. Write value of 0xFFB253 to V1GAIN register. Write value of 0x7FC4A9 to I2GAIN register. Write value of 0xFFB253 to V2GAIN register. Set LSD bit to 1 in the Mask register. terminate E2PROM command sequence.

• Atmel AT25010, AT25020 or AT25040
• National Semiconductor NM25C040M8 or NM25020M8
• Xicor X25040SI These serial E 2PROMs expect a specific 8-bit com- mand (00000011) in order to perform a memory read. The CS5467 has been hardware programmed to trans- mit this 8-bit command to the E 2PROM after reset. CS5467 EEPROM MODE SCLK SDI SDO CS SCK SO SI CS Connector to Calibrator VD 5 K 5 K Pulse Output Counter

Figure 13. Typical Interface of E2PROM to CS5467

1. BASIC APPLICATION CIRCUITS

and voltage dividers are used to sense the line voltages.

20 IIN1+

4.096 MHz

Figure 14. Typical Connection Diagram (Single-phase, 3-wire – Direct Connect to Power Line)

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1. PACKAGE DIMENSIONS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-150 Controlling Dimension is Millimeters 28L SSOP PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

1. ORDERING INFORMATION 14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Temperature Package CS5467-ISZ (lead free) -40 to +85 °C 28-pin SSOP Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5467-ISZ (lead free) 260 °C 3 7 Days

46 DS714F3

1. REVISION HISTORY Revision Date Changes PP1 FEB 2007 Initial release. PP2 FEB 2007 Corrections to implicitly state that temperature measurement is a secondary func- tion of voltage2 channel. Updated typical connection diagram. Changed Phase Compensation Range from ±2.8° to ±5.4°. F1 MAR 2007 Updated to F1 for quality process level (QPL). F2 JAN 2010 Increased on-chip reference temper ature coefficient from 25 ppm / °C typ. to 40 ppm / °C typ. F3 APR 2011 Removed lead-containing (Pb) device ordering information. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.