CS5461A CIRRUS | Alldatasheet
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Technical content
Features
Energy Data Linearity: ±0.1% of Reading over 1000:1 Dynamic Range On-chip Functions: - Instantaneous Voltage, Current, and Power - IRMS and VRMS, Apparent and Active (Real) Power - Energy-to-pulse Conversion for Mechanical Counter/Stepper Motor Drive - System Calibrations and Phase Compensation - Temperature Sensor - Voltage Sag Detect Meets Accuracy Spec for IEC, ANSI, & JIS. Low Power Consumption Current Input Optimized for Sense Resistor. GND-referenced Signals with Single Supply On-chip 2.5 V Reference (25 ppm/°C typ) Power Supply Monitor Simple Three-wire Digital Serial Interface “Auto-boot” Mode from Serial E2PROM. Power Supply Configurations: VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V
Description
The CS5461A is an integrated power measure- ment device which combines two analog-to-digital converters, power calculation engine, energy-to-frequency converter, and a serial interface on a single chip. It is designed to accurately measure instantaneous current and voltage, and calculate VRMS, IRMS, instanta- neous power, apparent power, and active power for single-phase, 2- or 3-wire power metering applications. The CS5461A is optimized to interface to shunt resistors or current transformers for current mea- surement, and to resistive dividers or potential transformers for voltage measurement. The CS5461A features a bi-directional serial in- terface for communication with a processor, and a programmable energy-to-pulse output func- tion. Additional functionality to facilitate system-level calibration, temperature sensor, voltage sag detection, and phase compensation. ORDERING INFORMATION: See Page 41. VA+ VD+ IIN+ IIN- VIN+ VIN- VREFIN VREFOUT AGND XIN XOUT CPUCLK DGND CS SDO SDI SCLK INT Voltage Reference System Clock Clock Generator Serial Interface E-to-F Power Monitor PFMON RESET Digital Filter Calibration MODE Power Calculation Engine 4th Order ∆Σ Modulator 2nd Order ∆Σ Modulator Temperature Sensor Digital Filter PGA HPF Option HPF Option x10 AUG ‘05 DS661F1
- OVERVIEW The CS5461A is a CMOS monolithic power measurement device with a computation engine and an en- ergy-to-frequency pulse output. The CS5461A combines a programmable-gain amplifier, two ∆Σ ana- log-to-digital converters (ADCs), system calibration and a computation engine on a single chip. The CS5461A is designed for power measurement applications and is optimized to interface to a cur- rent-sense resistor or transformer for current measurement, and to a resistive divider or potential trans- former for voltage measurement. The voltage and current channels provide programmable gains to accommodate various input levels from a wide variety of sensing elements. With single +5 V supply on VA+/AGND, both of the CS5461A’s input channels can accommodate common mode as well as signal levels between (AGND - 0.25 V) and VA+. Additionally, the CS5461A is equipped with a computation engine that calculates IRMS, VRMS, apparent power and active (real) power. To facilitate communication to a microprocessor, the CS5461A includes a simple three-wire serial interface which is SPI™ and Microwire™ compatible. The CS5461A provides three outputs for energy registration. E1 and E2 are designed to directly drive a mechanical counter or stepper motor, or interface to a microprocessor. The pulse output E3 is designed to assist with meter cal- ibration.
- PIN DESCRIPTION Clock Generator Crystal Out Crystal In 1,24 XOUT, XIN - The output and input of an inverting amplifier. Oscillation occurs when connected to a crystal, providing an on-chip system clock. Alternatively, an external clock can be supplied to the XIN pin to provide the system clock for the device. CPU Clock Output CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load. Control Pins and Serial Data I/O Serial Clock Input SCLK - A Schmitt Trigger input pin. Clocks data from the SDI pin into the receive buffer and out of the transmit buffer onto the SDO pin when CS is low. Serial Data Output SDO -Serial port data output pin.SDO is forced into a high impedance state when CS is high. Chip Select CS - Low, activates the serial port interface. Mode Select MODE - High, enables the “auto-boot” mode. The mode pin is pulled low by an internal resistor. High Frequency Energy Output E3 - Active low pulses with an output frequency proportional to the active power. Used to assist in system calibration. Reset RESET - A Schmitt Trigger input pin. Low activates Reset, all internal registers (some of which drive output pins) are set to their default states. Interrupt INT - Low, indicates that an enabled event has occurred. Energy Output 21,22 E1, E2 - Active low pulses with an output frequency proportional to the active power. Indicates if the measured energy is negative. Serial Data Input SDI - Serial port data input pin. Data will be input at a rate determined by SCLK. Analog Inputs/Outputs Differential Voltage Inputs 9,10 VIN+, VIN- - Differential analog input pins for the voltage channel. Differential Current Inputs 15,16 IIN+, IIN- - Differential analog input pins for the current channel. Voltage Reference Output VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magni- tude of 2.5 V and is referenced to the AGND pin on the converter. Voltage Reference Input VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator. Power Supply Connections Positive Digital Supply VD+ - The positive digital supply. Digital Ground DGND - Digital Ground. Positive Analog Supply VA+ - The positive analog supply. Analog Ground AGND - Analog ground. Power Fail Monitor PFMON - The power fail monitor pin monitors the analog supply. If PFMON’s voltage threshold is not met, a Low-Supply Detect (LSD) bit is set in the status register. VREFIN Voltage Reference Input VREFOUT Voltage Reference Output VIN- Differential Voltage Input VIN+ Differential Voltage Input MODE Mode Select CS Chip Select SDO Serial Data Ouput SCLK Serial Clock DGND Digital Ground VD+ Positive Digital Supply CPUCLK CPU Clock Output XOUT Crystal Out AGND Analog Ground VA+ Positive Analog Supply IIN- Differential Current Input IIN+ Differential Current Input PFMON Power Fail Monitor High Frequency Energy Output RESET Reset INT Interrupt Energy Output 1 SDI Serial Data Input XIN Crystal In Energy Output 2
- CHARACTERISTICS & SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS ANALOG CHARACTERISTICS Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V. MCLK = 4.096 MHz. Parameter Symbol Min Typ Max Unit Positive Digital Power Supply VD+ 3.135 5.0 5.25 V Positive Analog Power Supply VA+ 4.75 5.0 5.25 V Voltage Reference VREFIN 2.5 V Specified Temperature Range TA -40 +85 Parameter Symbol Min Typ Max Unit Linearity Performance Active Power Accuracy All Gain Ranges (Note 1) Input Range 0.1% - 100% PActive ±0.1 Current RMS Accuracy All Gain Ranges (Note 1) Input Range 1.0% - 100% Input Range 0.3% - 1.0% Input Range 0.1% - 0.3% IRMS ±0.1 ±0.2 ±3.0 Voltage RMS Accuracy All Gain Ranges (Note 1) Input Range 5% - 100% VRMS ±0.1 Analog Inputs (Both Channels) Common Mode Rejection (DC, 50, 60 Hz) CMRR dB Common Mode + Signal All Gain Ranges -0.25 VA+ V Analog Inputs (Current Channel) Differential Input Range (Gain = 10) [(IIN+) - (IIN-)] (Gain = 50) IIN 500 100 mVP-P mVP-P Total Harmonic Distortion (Gain = 50) THD dB Crosstalk with Voltage Channel at Full Scale (50, 60 Hz) -115 dB Input Capacitance (Gain = 10) (Gain = 50) IC pF pF Effective Input Impedance EII kΩ Noise (Referred to Input) (Gain = 10) (Gain = 50) NI 22.5 4.5 µVrms µVrms Offset Drift (Without the high-pass filter) OD 4.0 µV/°C Gain Error (Note 2) GE ±0.4 Analog Inputs (Voltage Channel) Differential Input Range {(VIN+) - (VIN-)} VIN 500 mVP-P Total Harmonic Distortion THD dB Crosstalk with Current Channel at Full Scale (50, 60 Hz) -70 dB Input Capacitance All Gain Ranges IC 0.2 pF Effective Input Impedance EII MΩ Noise (Referred to Input) NV 140 µVrms Offset Drift (Without the high-pass Filter) OD 16.0 µV/°C Gain Error (Note 2) GE ±3.0
ANALOG CHARACTERISTICS (Continued) Applies when the HPF option is enabled. Applies before system calibration. All outputs unloaded. All inputs CMOS level. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to AGND. Then the CS5461A is commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB): When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at which the LSD bit can be permanently reset back to 0. VOLTAGE REFERENCE Notes: The voltage at VREFOUT is measured across the temperature range. From these measurements the following formula is used to calculate the VREFOUT Temperature Coefficient:. Specified at maximum recommended output of 1 µA, source or sink. Parameter Symbol Min Typ Max Unit Temperature Channel Temperature Accuracy T Power Supplies Power Supply Currents (Active State) IA+ ID+ (VA+ = VD+ = 5 V) ID+ (VA+ = 5 V, VD+ = 3.3 V) PSCA PSCD PSCD 1.3 2.9 1.7 mA mA mA Power Consumption Active State (VA+ = VD+ = 5 V) (Note 3) Active State (VA+ = 5 V, VD+ = 3.3 V) Stand-By State Sleep State PC 16.5 mW mW mW µW Power Supply Rejection Ratio (DC, 50 and 60 Hz) (Note 4) Voltage Channel Current Channel PSRR dB dB PFMON Low-voltage Trigger Threshold (Note 5) PMLO 2.3 2.45 V PFMON High-voltage Power-On Trip Point (Note 6) PMHI 2.55 2.7 V Parameter Symbol Min Typ Max Unit Reference Output Output Voltage VREFOUT +2.4 +2.5 +2.6 V Temperature Coefficient (Note 7) TCVREF ppm/°C Load Regulation (Note 8) ∆VR mV Reference Input Input Voltage Range VREFIN +2.4 +2.5 +2.6 V Input Capacitance pF Input CVF Current nA PSRR 150 Veq log (V R E F O U T M A X - V R E F O U T M IN ) V R E F O U T A V G T A M A X - T A M IN 1 .0 x 1 0 T C V R E F =
Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V. MCLK = 4.096 MHz. Notes: All measurements performed under static conditions. 10. If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz. 11. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification. 12. The frequency of CPUCLK is equal to MCLK. 13. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the full-scale signal applied to the channel input. 14. Configuration Register bits PC[6:0] are set to “0000000”. 15. The MODE pin is pulled low by an internal resistor. Parameter Symbol Min Typ Max Unit Master Clock Characteristics Master Clock Frequency Internal Gate Oscillator (Note 10) MCLK 2.5 4.096 MHz Master Clock Duty Cycle CPUCLK Duty Cycle (Note 11 and 12) Filter Characteristics Phase Compensation Range (Voltage Channel, 60 Hz) -2.8 +2.8 Input Sampling Rate DCLK = MCLK/K DCLK/8 Hz Digital Filter Output Word Rate (Both Channels) OWR DCLK/1024 Hz High-pass Filter Corner Frequency -3 dB 0.5 Hz Full Scale Calibration Range (Referred to Input) (Note 13) FSCR 100 %F.S. Channel-to-channel Time-shift Error (Note 14) 1.0 µs Input/Output Characteristics High-level Input Voltage All Pins Except XIN and SCLK and RESET XIN SCLK and RESET VIH
0.6 VD+
(VD+) - 0.5
0.8 VD+
V V V Low-level Input Voltage (VD = 5 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET VIL 0.8 1.5
0.2 VD+
V V V Low-level Input Voltage (VD = 3.3 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET VIL 0.48 0.3 V V V High-level Output Voltage Iout = +5 mA VOH (VD+) - 1.0 V Low-level Output Voltage Iout = -5 mA VOL 0.4 V Input Leakage Current (Note 15) Iin ±10 µA 3-state Leakage Current IOZ ±10 µA Digital Output Pin Capacitance Cout pF
Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V. Logic Levels: Logic 0 = 0 V, Logic 1 = VD+. Notes: 16. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF. 17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. Parameter Symbol Min Typ Max Unit Rise Times Any Digital Input Except SCLK (Note 16) SCLK Any Digital Output trise 1.0 100 µs µs ns Fall Times Any Digital Input Except SCLK (Note 16) SCLK Any Digital Output tfall 1.0 100 µs µs ns Start-up Oscillator Start-Up Time XTAL = 4.096 MHz (Note 17) tost ms Serial Port Timing Serial Clock Frequency SCLK MHz Serial Clock Pulse Width High Pulse Width Low 200 200 ns ns SDI Timing CS Falling to SCLK Rising ns Data Set-up Time Prior to SCLK Rising ns Data Hold Time After SCLK Rising 100 ns SDO Timing CS Falling to SDO Driving ns SCLK Falling to New Data Bit (hold time) ns CS Rising to SDO Hi-Z ns Auto-Boot Timing Serial Clock Pulse Width Low Pulse Width High t10 MCLK MCLK MODE setup time to RESET Rising t11 ns RESET rising to CS falling t12 MCLK CS falling to SCLK rising t13 100 MCLK SCLK falling to CS rising t14 MCLK CS rising to driving MODE low (to end auto-boot sequence). t15 ns SDO guaranteed setup time to SCLK rising t16 100 ns
Figure 1. CS5461A Read and Write Timing Diagrams
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 18. VA+ and AGND must satisfy {(VA+) - (AGND)} ≤ + 6.0 V. 19. VD+ and AGND must satisfy {(VD+) - (AGND)} ≤ + 6.0 V. 20. Applies to all pins including continuous over-voltage conditions at the analog input pins. 21. Transient current of up to 100 mA will not cause SCR latch-up. 22. Maximum DC input current for a power supply pin is ±50 mA. 23. Total power dissipation, including all input currents and output currents. Parameter Symbol Min Typ Max Unit DC Power Supplies (Notes 18 and 19) Positive Digital Positive Analog VD+ VA+ -0.3 -0.3 +6.0 +6.0 V V Input Current, Any Pin Except Supplies (Notes 20, 21, 22) IIN ±10 mA Output Current, Any Pin Except VREFOUT IOUT 100 mA Power Dissipation (Note 23) PD 500 mW Analog Input Voltage All Analog Pins VINA - 0.3 (VA+) + 0.3 V Digital Input Voltage All Digital Pins VIND -0.3 (VD+) + 0.3 V Ambient Operating Temperature TA -40 Storage Temperature Tstg -65 150
optimized to simplify interfacing to sensing elements. ulator samples the amplified signal for digitization. range and simplified anti-alias filter design.
4.1 Digital Filters
the low-pass filtering operation.
4.2 Voltage and Current Measurements
set adjustment and a gain calibration (See Section 7. taneous voltage and current registers. ery cycle count (referred to as a computational cycle).
4.3 Power Measurements
er and is designed for system calibration. multiplied by the time duration of the computation cycle. Figure 2. Data Flow.
The apparent power is the combination of the active power and reactive power, without reference to an im- pedance phase angle, and is calculated by the CS5461A using the following formula: The apparent power is registered once every computa- tion cycle.
4.4 Linearity Performance
The linearity of the VRMS, IRMS, and active power mea- surements (before calibration) will be within ±0.1% of reading over the ranges specified, with respect to the in- put voltage levels required to cause full-scale readings in the IRMS and VRMS registers. Refer to Linearity Per- formance Specifications on page 7. Until the CS5461A is calibrated, the accuracy of the CS5461A (with respect to a reference line-voltage and line-current level on the power mains) is not guaranteed to within ±0.1%. See Section 7. System Calibration on page 33. The accuracy of the internal calculations can often be improved by selecting a value for the Cycle Count Register that will cause the time duration of one computation cycle to be equal to (or very close to) a whole-number of power-line cycles (and N must be greater than or equal to 4000). S VRMS IRMS
5.1 Analog Inputs
as the voltage and current channel inputs, respectively. and voltage channel is ±250 mVP.
5.1.1 Voltage Channel
programmable gain of up to 4x.
5.1.2 Current Channel
Energy Pulse Output on page 16. mum input range should be adjusted accordingly.
5.2 High-pass Filters
the voltage and current channel respectively.
5.3 Performing Measurements
represents the maximum possible value. Table 1. Current Channel PGA Configuration
5.4 Energy Pulse Output
4.096 MHz/(MCLK/K) to get the actual pulse rate out-
5.4.1 Normal Format
tive power. The E2 pin is the energy direction indicator. Table 2. E1 and E2 Pulse Output Format Figure 3. Normal Format on pulse outputs E1 and E2
5.4.2 Alternate Pulse Format
5.4.3 Mechanical Counter Format
5.4.4 Stepper Motor Format
configures the E1 and E2 pins for stepper motor format. Figure 4. Alternate Pulse Format on E1 and E2 Figure 5. Mechanical Counter Format on E1 and E2
will lead E2. When energy is negative, E2 will lead E1.
5.4.5 Pulse Output E3
has no energy direction indicator.
5.4.6 Anti-creep for the Pulse Outputs
Control Register for E1 and E2. cy of the registered energy will be maintained.
5.4.7 Design Examples
Figure 6. Stepper Motor Format on E1 and E2
el signal is applied to the channel inputs.
5.5 Voltage Sag-detect Feature
sag duration is specified in terms of ADC cycles.
5.6 On-chip Temperature Sensor
utilized to assist in compensating for temperature drift. ues allowing for temperature scale conversions. indicates when the Temperature Register is updated. Figure 7. Voltage Sag Detect
Temperature Offset Register (Toff).
5.7 Voltage Reference
5.8 System Initialization
cillator to stabilize. The CS5461A will then initialize. eight-XIN-clock-period delay is enabled. and ready to receive commands.
5.9 Power-down States
Section 5.8 System Initialization on page 20).
5.10 Oscillator Characteristics
then DCLK is 3 MHz, which is a valid value for DCLK. Figure 8. Oscillator Connection
5.11 Event Handler
that has been set in the Status Register. and IINV bits of the Configuration Register. least one DCLK cycle (DCLK = MCLK/K).
5.11.1 Typical Interrupt Handler
The steps below show how interrupts can be handled. 4) Read the Status Register. 6) Branch to the proper interrupt service routine. 9) Return from interrupt service routine.
5.12 Serial Port Overview
register reads currently being transmitted. mands do not affect operations currently in progress. Register writes must be followed by three bytes of data. register reads can return up to four bytes of data.
5.12.1 Serial Port Interface
Drive the CS pin high, then low. as the state of the part may be unknown. Table 3. Interrupt Configuration
5.13 Commands
All commands are 8-bits in length. Any byte that is not listed in this section is invalid. Commands that write to regis- ters must be followed by 3 bytes of data. Commands that read data can be chained with other commands (e.g., while reading data, a new command can be sent which can execute during the original read). All commands except reg- ister reads, register writes, and SYNC0 & SYNC1 will abort any currently executing commands.
5.13.1 Start Conversions
Initiates acquiring measurements and calculating results. The device has two modes of acquisition. Modes of acquisition/measurement 0 = Perform a single computation cycle 1 = Perform continuous computation cycles
5.13.2 SYNC0 and SYNC1
The serial port can be initialized by asserting CS or by sending three or more consecutive SYNC1 commands fol- lowed by a SYNC0 command. The SYNC0 or SYNC1 can also be sent while sending data out. SYNC 0 = Last byte of a serial port re-initialization sequence. 1 = Used during reads and serial port initialization.
5.13.3 Power-Up/Halt
If the device is powered-down, Power-Up/Halt will initiate a power on reset. If the part is already powered-on, all computations will be halted.
5.13.4 Power-down and Software Reset
To conserve power the CS5461A has two power-down states. In stand-by state all circuitry, except the analog/digital clock generators, is turned off. In the sleep state all circuitry, except the instruction decoder, is turned off. Bringing the CS5461A out of sleep state requires more time than out of stand-by state, because of the extra time needed to re-start and re-stabilize the analog oscillator. S[1:0] Power-down state 00 = Software Reset 01 = Halt and enter stand-by power saving state. This state allows quick power-on 10 = Halt and enter sleep power saving state. 11 = Reserved SYNC
5.13.5 Register Read/Write
The Read/Write informs the command decoder that a register access is required. During a read operation, the ad- dressed register is loaded into an output buffer and clocked out by SCLK. During a write operation, the data is clocked into an input buffer and transferred to the addressed register upon completion of the 24th SCLK. W/R Write/Read control 0 = Read 1 = Write RA[4:0] Register address bits (bits 5 through 1) of the read/write command. Address RA[4:0] Name Number of A/D conversions used in one computation cycle (N)). 00110 PulseRateE1,2 Sets the E1 and E2 energy-to-frequency output pulse rate. 00111 I Instantaneous Current 01000 V Instantaneous Voltage 01001 P Instantaneous Power 01010 PActive Active (Real) Power 01011 IRMS RMS Current 01100 VRMS RMS Voltage 01110 Poff Power Offset 01111 Status Status 10000 IACoff Current AC (RMS) Offset 10001 VACoff Voltage AC (RMS) Offset 10010 PulseRateE3 Sets the E3 energy-to-frequency output pulse rate. 10011 T Temperature 10100 SYSGain System Gain 10101 PW Pulse width register for mechanical counter output mode 10111 VSAGDuration Voltage Sag Duration 11000 VSAGLevel Voltage Sag Level Threshold 11010 Mask Interrupt Mask 11100 Ctrl Control 11101 TGain Temperature Sensor Gain 11110 Toff Temperature Sensor Offset 11111 S Apparent Power Note: For proper operation, do not attempt to write to unspecified registers. W/R RA4 RA3 RA2 RA1 RA0
5.13.6 Calibration
The CS5461A can perform system calibrations. Proper input signals must be applied to the current and voltage channel before performing a designated calibration. CAL[4:0]* Designates calibration to be performed 01001 = Current channel DC offset 01010 = Current channel DC gain 01101 = Current channel AC offset 01110 = Current channel AC gain 10001 = Voltage channel DC offset 10010 = Voltage channel DC gain 10101 = Voltage channel AC offset 10110 = Voltage channel AC gain 11001 = Current and Voltage channel DC offset 11010 = Current and Voltage channel DC gain 11101 = Current and Voltage channel AC offset 11110 = Current and Voltage channel AC gain *Values for CAL[4:0] not specified should not be used. CAL4 CAL3 CAL2 CAL1 CAL0
- REGISTER DESCRIPTION “Default” => bit status after power-on or reset Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
6.1 Configuration Register
Address: 0 Default = 0x000001 PC[6:0] Phase compensation. A 2’s complement number which sets a delay in the voltage channel rel- ative to the current channel. When MCLK = 4.096 MHz and K = 1, the phase adjustment range is approximately ±2.8 degrees with each step approximately 0.04 degrees (assuming a power line frequency of 60 Hz). If (MCLK/K) is not 4.096 MHz, the values for the range and step size should be scaled by the factor 4.096 MHz / (MCLK/K). Default setting is 0000000 = 0.0215 de- gree phase delay at 60 Hz (when MCLK = 4.096 MHz). Igain Sets the gain of the current PGA. 0 = Gain is 10x (default) 1 = Gain is 50x EWA Allows the E1 and E2 pins to be configured as open-collector output pins. 0 = Normal outputs (default) 1 = Only the pull-down device of the E1 and E2 pins are active IMODE, IINV Interrupt configuration bits. Select the desired pin behavior for indication of an interrupt. 00 = Active-low level (default) 01 = Active-high level 10 = High-to-low pulse 11 = Low-to-high pulse EPP Allows the E1 and E2 pins to be controlled by the EOP and EDP bits. 0 = Normal operation of the E1 and E2 pins. (default) 1 = EOP and EDP bits defines the E1 and E2 pins. EOP EOP defines the value of the E1 pin when EPP = 1. 0 = Logic level low (default) EDP EDP defines the value of the E2 pin when EPP = 1. 0 = Logic level low (default) ALT Alternate pulse format, E1 and E2 becomes active low alternating pulses with an output fre- quency proportional to the active power. 0 = Normal (default), Mechanical Counter or Stepper Motor Format 1 = Alternate Pulse Format, also MECH = 1 VHPF (IHPF) Enables the high-pass filter on the voltage (current) channel. 0 = High-pass filter disabled (default) 1 = High-pass filter enabled PC6 PC5 PC4 PC3 PC2 PC1 PC0 Igain EWA IMODE IINV EPP EOP EDP ALT VHPF IHPF iCPU
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPUCLK should not be active during the sample edge. 0 = Normal operation (default) 1 = Minimize noise when CPUCLK is driving rising-edge logic K[3:0] Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be- tween 1 and 16. A value of “0000” will set K to 16 (not zero). K = 1 at reset.
6.2 Current and Voltage DC Offset Register ( IDCoff ,VDCoff )
Address: 1 (Current DC Offset); 3 (Voltage DC Offset) Default = 0x000000 The DC Offset registers (IDCoff,VDCoff) are initialized to 0.0 on reset. When DC Offset calibration is performed, the register is updated with the DC offset measured over a computation cycle. DRDY will be asserted at the end of the calibration. This register may be read and stored for future system offset compensation. The value is repre- sented in two's complement notation and in the range of -1.0 ≤IDCoff, VDCoff < 1.0, with the binary point to the right of the MSB.
6.3 Current and Voltage Gain Register ( Ign ,Vgn )
Address: 2 (Current Gain); 4 (Voltage Gain) Default = 0x400000 = 1.000 The gain registers (Ign,Vgn) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed, the register is updated with the gain measured over a computation cycle. DRDY will be asserted at the end of the calibration. This register may be read and stored for future system gain compensation. The value is in the range 0.0 ≤Ign,Vgn < 3.9999, with the binary point to the right of the second MSB.
6.4 Cycle Count Register
Address: 5 Default = 0x000FA0 = 4000 Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions, the computation cycle frequency is (MCLK/K)/(1024∗N). A one second computational cycle period occurs when MCLK = 4.096 MHz, K = 1, and N = 4000. MSB LSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-17 2-18 2-19 2-20 2-21 2-22 2-23 MSB LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-16 2-17 2-18 2-19 2-20 2-21 2-22 MSB LSB 223 222 221 220 219 218 217 216
6.5 PulseRateE1,2 Register
Address: 6 Default = 0xFA000 = 32000.00 Hz PulseRateE1,2 sets the frequency of the E1 and/or E2 pulses. The smallest valid frequency is 2-4 with 2-5 incre- mental steps. A pulse rate higher than (MCLK/K)/8 will result in a pulse rate setting of (MCLK/K)/8. The value is represented in unsigned notation, with the binary point to the right of bit 5.
6.6 Instantaneous Current, Voltage and Power Registers ( I , V , P )
Address: 7 (Instantaneous Current); 8 (Instantaneous Voltage); 9 (Instantaneous Power) I and V contain the instantaneous measured values for current and voltage, respectively. The instantaneous voltage and current samples are multiplied to obtain Instantaneous Power (P). The value is represented in two's complement notation and in the range of -1.0 ≤I, V, P < 1.0, with the binary point to the right of the MSB.
6.7 Active (Real) Power Registers ( PActive )
Address: 10 The instantaneous power is averaged over each computation cycle (N conversions) to compute Active Power (PActive). The value is represented in two's complement notation and in the range of -1.0 ≤PActive< 1.0, with the binary point to the right of the MSB.
6.8 IRMS and VRMS Registers ( IRMS , VRMS )
Address: 11 (IRMS); 12 (VRMS) IRMS and VRMS contain the Root Mean Square (RMS) value of I and V, calculated over each computation cycle. The value is represented in unsigned binary notation and in the range of 0.0 ≤IRMS, VRMS < 1.0, with the binary point to the left of the MSB.
6.9 Power Offset Register ( Poff )
Address: 14 Default = 0x000000 Power Offset (Poff) is added to the instantaneous power being accumulated in the Pactive register and can be used to offset contributions to the energy result that are caused by undesirable sources of energy that are in- herent in the system. The value is represented in two's complement notation and in the range of -1.0 ≤Poff < 1.0, with the binary point to the right of the MSB. MSB LSB 218 217 216 215 214 213 212 211 2-1 2-2 2-3 2-4 2-5 MSB LSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-17 2-18 2-19 2-20 2-21 2-22 2-23 MSB LSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-17 2-18 2-19 2-20 2-21 2-22 2-23 MSB LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-18 2-19 2-20 2-21 2-22 2-23 2-24 MSB LSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-17 2-18 2-19 2-20 2-21 2-22 2-23
6.10 Status Register and Mask Register ( Status , Mask )
Address: 15 (Status); 26 (Mask) Default = 0x000001 (Status Register), 0x000000 (Mask Register) The Status Register indicates status within the chip. In normal operation, writing a '1' to a bit will cause the bit to reset. Writing a '0' to a bit will not change it’s current state. The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in a Mask bit will allow the corresponding bit in the Status Register to activate the INT pin when the status bit is asserted. DRDY Data Ready. During conversions, this bit will indicate the end of computation cycles. For cali- brations, this bit indicates the end of a calibration sequence. CRDY Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate. IOR Current Out of Range. Set when the Instantaneous Current Register overflows. VOR Voltage Out of Range. Set when the Instantaneous Voltage Register overflows. IROR IRMS Out of Range. Set when the IRMS Register overflows. VROR VRMS Out of Range. Set when the VRMS Register overflows. EOR Energy Out of Range. Set when PACTIVE overflows. TUP Temperature Updated. Indicates the Temperature Register has updated. TOD Modulator oscillation detected on the temperature channel. Set when the modulator oscillates due to an input above full scale. VOD (IOD) Modulator oscillation detected on the voltage (current) channel. Set when the modulator oscil- lates due to an input above full scale. The level at which the modulator oscillates is significantly higher than the voltage (current) channel’s differential input voltage range. Note: The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the power line. This event should not be confused with a DC overload situation at the in- puts, when the IOD and VOD bits will re-assert themselves even after being cleared, multiple times. LSD Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage thresh- old (PMLO), with respect to AGND pin. The LSD bit cannot be reset until the voltage at PFMON pin rises back above the high-voltage threshold (PMHI). VSAG Indicates a voltage sag has occurred. See Section 5.5 Voltage Sag-detect Feature on page 19. IC Invalid Command. Normally logic 1. Set to logic 0 if an invalid command is received or the Sta- tus Register has not been successfully read. DRDY CRDY IOR VOR IROR VROR EOR TUP TOD VOD IOD LSD VSAG IC
6.11 Current and Voltage AC Offset Register ( VACoff , IACoff )
Address: 16 (Current AC Offset); 17 (Voltage AC Offset) Default = 0x000000 The AC Offset Registers (VACoff, IACoff) are initialized to zero on reset, allowing for uncalibrated normal operation. AC Offset Calibration updates these registers. This sequence lasts approximately (6N + 30) ADC cycles (where N is the value of the Cycle Count Register). DRDY will be asserted at the end of the calibration. These values may be read and stored for future system AC offset compensation. The value is represented in two's comple- ment notation and in the range of -1.0 ≤VACoff, IACoff < 1.0, with the binary point to the right of the MSB.
6.12 PulseRateE3 Register
Address: 18 Default = 0xFA0000 = 32000.00 Hz PulseRateE3 sets the frequency of the E3 pulses. The register’s smallest valid frequency is 2-4 with 2-5 incre- mental steps. A pulse rate higher than (MCLK/K)/8 will result in a pulse rate setting of (MCLK/K)/8. The value is represented in unsigned notation, with the binary point to the right of bit #5.
6.13 Temperature Register ( T )
Address: 19 T contains measurements from the on-chip temperature sensor. Measurements are performed during continu- ous conversions, with the default the Celsius scale (oC). The value is represented in two's complement notation and in the range of -128.0 ≤T < 128.0, with the binary point to the right of the eighth MSB.
6.14 System Gain Register ( SYSGain )
Address: 20 Default = 0x500000 = 1.25 System Gain (SYSGain) determines the one’s density of the channel measurements. Small changes in the mod- ulator due to temperature can be fine adjusted by changing the system gain. The value is represented in two's complement notation and in the range of -2.0 < SYSGain < 2.0, with the binary point to the right of the second MSB. MSB LSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-17 2-18 2-19 2-20 2-21 2-22 2-23 MSB LSB 218 217 216 215 214 213 212 211 2-1 2-2 2-3 2-4 2-5 MSB LSB -(27) 2-10 2-11 2-12 2-13 2-14 2-15 2-16 MSB LSB -(21) 2-1 2-2 2-3 2-4 2-5 2-6 2-16 2-17 2-18 2-19 2-20 2-21 2-22
6.15 Pulsewidth Register ( PW )
Address: 21 Default = 0x000200 = 512 sample periods PW sets the pulsewidth of E1 and E2 pulses in Alternate Pulse and Mechanical Counter format. The width is a function of number of sample periods. The default corresponds to a pulsewidth of 512 samples/[(MCLK/K)/1024] = 128 msec with MCLK = 4.096 MHz and K = 1. The value is represented in un- signed notation.
6.16 Voltage Sag Duration Register ( VSAGDuration )
Address: 23 Default = 0x000000 Voltage Sag Duration (VSAGDuration) defines the number of instantaneous voltage measurements utilized to de- termine a voltage level sag event (VSAGLEVEL). Setting this register to zero will disable Voltage Sag-detect. The value is represented in unsigned notation.
6.17 Voltage Sag Level Register ( VSAGLevel )
Address: 24 Default = 0x000000 Voltage Sag Level (VSAGLevel) defines the voltage level that the magnitude of input samples, averaged over the sag duration, must fall below in order to register a sag condition. This value is represented in unsigned notation and in the range of 0 ≤VSAGLevel < 1.0, with the binary point to the right of the MSB. MSB LSB 223 222 221 220 219 218 217 216 MSB LSB 222 221 220 219 218 217 216 MSB LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-17 2-18 2-19 2-20 2-21 2-22 2-23
6.18 Control Register
Register Address: 28 Default = 0x000000 FAC Determines if anti-creep is enabled for pulse output E3. 0 = Disable anti-creep (default) 1 = Enabled anti-creep EAC Determines if anti-creep is enabled for pulse output E1 and/or E2. 0 = Disable anti-creep (default) 1 = Enabled anti-creep STOP Terminates the auto-boot sequence. 0 = Normal (default) 1 = Stop sequence MECH Mechanical Counter Format, E1 or E2 becomes active low pulses with an output frequency pro- portional to the active power 0 = Normal (default) or Stepper Motor Format 1 = Mechanical Counter Format, also ALT = 0 INTOD Converts INT output pin to an open drain output. 0 = Normal (default) 1 = Open drain NOCPU Saves power by disabling the CPUCLK pin. 0 = Normal (default) 1 = Disables CPUCLK NOOSC Saves power by disabling the crystal oscillator. 0 = Normal (default) 1 = Oscillator circuit disabled STEP Stepper Motor Format, E1 and E2 becomes active low pulses with an output frequency propor- tional to the active power 0 = Normal Format (default) 1 = Stepper Motor Format, also MECH = 0 and ALT = 0 FAC EAC STOP MECH INTOD NOCPU NOOSC STEP
6.19 Temperature Gain Register ( TGain )
Address: 29 Default = 0x34E2E7 = 26.443169 Sets the temperature channel gain. Temperature gain (TGain) is utilized to convert from one temperature scale to another. The Celsius scale (oC) is the default. Values are represented in unsigned notation and in the range of 0 ≤TGain < 128, with the binary point to the right of the seventh MSB.
6.20 Temperature Offset Register ( Toff )
Address: 30 Default = 0xF3E7D0 = -0.094488 Temperature offset (Toff) is used to remove the temperature channel’s offset at the zero degree reading. Values are represented in two's complement notation and in the range of -1.0 ≤Toff < 1.0, with the binary point to the right of the MSB.
6.21 Apparent Power Register ( S )
Address: 31 Apparent power (S) is the product of the VRMS and IRMS. The value is represented in unsigned binary notation and in the range of 0.0 ≤S < 1.0, with the binary point to the left of the MSB. MSB LSB 2-1 2-11 2-12 2-13 2-14 2-15 2-16 2-17 MSB LSB -(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-17 2-18 2-19 2-20 2-21 2-22 2-23 MSB LSB 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-18 2-19 2-20 2-21 2-22 2-23 2-24
7.1 Channel Offset and Gain Calibration
age channel and current channel.
7.1.1 Calibration Sequence
7.1.1.1 Duration of Calibration Sequence
7.1.2 Offset Calibration Sequence
connected to their ground-reference level.
7.1.2.1 DC Offset Calibration Sequence
Figure 9. Calibration Data Flow Figure 10. System Calibration of Offset.
7.1.2.2 AC Offset Calibration Sequence
ed from each successive VRMS and IRMS calculation.
7.1.3 Gain Calibration Sequence
er then 1.0, AC gain calibration should be used.
7.1.3.1 AC Gain Calibration Sequence
age and current channel’s maximum input voltage level. Figure 11. System Calibration of Gain Figure 12. Example of AC Gain Calibration Figure 13. Another Example of AC Gain Calibration
ecuted. However, an AC signal should not be used for DC gain calibration.
7.1.3.2 DC Gain Calibration Sequence
Initiate a DC gain calibration. The corresponding gain register is restored to default (1.0). The DC gain calibra- tion algorithm averages the channel’s instantaneous measurements over one computation cycle (N sam- ples). The average is then divided into 1.0 and the quo- tient is stored in the corresponding gain register After the DC gain calibration, the instantaneous register will read at full-scale whenever the DC level of the input signal is equal to the level of the DC calibration signal applied to the inputs during the DC gain calibration.The HPF option should not be enabled if DC gain calibration is utilized.
7.1.4 Order of Calibration Sequences
- If the HPF option is enabled, then any dc compo- nent that may be present in the selected signal path will be removed and a DC offset calibration is not re- quired. However, if the HPF option is disabled the DC offset calibration sequence should be per- formed. When using high-pass filters, it is recommended that the DC offset register for the corresponding channel be set to zero. When performing DC offset calibration, the corresponding gain channel should be set to one. 2. If an ac offset exist, in the VRMS or IRMS calculation, then the AC offset calibration sequence should be performed. 3. Perform the gain calibration sequence. 4. Finally, if an AC offset calibration was performed (step 2), then the AC offset may need to be adjusted to compensate for the change in gain (step 3). This can be accomplished by restoring zero to the AC offset register and then perform an AC offset cali- bration sequence. The adjustment could also be done by multiplying the AC offset register value that was calculated in step 2 by the gain calculated in step 3 and updating the AC offset register with the product.
7.2 Phase Compensation
The CS5461A is equipped with phase compensation to cancel out phase shifts introduced by the measurement element. Phase Compensation is set by bits PC[6:0] in the Configuration Register. The default value of PC[6:0] is zero. With MCLK = 4.096 MHz and K = 1, the phase compensa- tion has a range of ±2.8 degrees when the input signals are 60 Hz. Under these conditions, each step of the phase compensation register (value of one LSB) is ap- proximately 0.04 degrees. For values of MCLK other than 4.096 MHz, the range and step size should be scaled by 4.096 MHz/(MCLK/K). For power-line fre- quencies other than 60Hz, the values of the range and step size of the PC[6:0] bits can be determined by con- verting the above values from angular measurement into time-domain (seconds), and then computing the new range and step size (in degrees) with respect to the new line frequency.
7.3 Active Power Offset
The Power Offset Register can be used to offset system power sources that may be resident in the system, but do not originate from the power-line signal. These sources of extra energy in the system contribute unde- sirable and false offsets to the power and energy mea- surement results. After determining the amount of stray power, the Power Offset Register can be set to cancel the effects of this unwanted energy.
- AUTO-BOOT MODE USING E2PROM
8.1 Auto-Boot Configuration
values and begin registering energy. running. Any of the valid commands can be used.
8.2 Auto-Boot Data for E2PROM
Set PulseRateE1,2 Register to 1000 Hz. Unmask bit #2 (LSD) in the Mask Register). auto-boot initialization sequence.
8.3 Suggested E2PROM Devices
ginning of the auto-boot sequence. Figure 14. Typical Interface of E2PROM to CS5461A
- BASIC APPLICATION CIRCUITS
and a current transformer to sense the line current.
4.096 MHz
120 VAC
Indicates common (floating) return. Figure 15. Typical Connection Diagram (Single-phase, 2-wire – Direct Connect to Power Line)
4.095 MHz
240 VAC
Figure 17. Typical Connection Diagram (Single-phase, 3-wire)
16 IIN+
12 VAC
Figure 16. Typical Connection Diagram (Single-phase, 2-wire – Isolated from Power Line)
Indicates common (floating) return. Figure 18. Typical Connection Diagram (Single-phase, 3-wire – No Neutral Available)
10.PACKAGE DIMENSIONS Notes: 3. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0.084 2.13 0.002 0.006 0.010 0.05 0.13 0.25 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 0.015 0.22 0.38 2,3 D 0.311 0.323 0.335 7.90 8.20 8.50 E 0.291 0.307 0.323 7.40 7.80 8.20 0.197 0.209 0.220 5.00 5.30 5.60 e 0.022 0.026 0.030 0.55 0.65 0.75 L 0.025 0.03 0.041 0.63 0.75 1.03 JEDEC #: MO-150 Controlling Dimension is Millimeters. E N 1 2 3 e A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW 24L SSOP PACKAGE DRAWING
- ORDERING INFORMATION 12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 13. REVISION HISTORY Model Temperature Package CS5461A-IS -40 to +85 °C 24-pin SSOP CS5461A-ISZ (lead free) Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5461A-IS 240 °C
365 Days
CS5461A-ISZ (lead free) 260 °C
7 Days
Initial Preliminary Release AUG 2005 Final version Updated with most-recent characterization data. MSL data added. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.