CS5451A_05 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

  • Synchronous Sampling
  • On-chip 1.2 V Reference (25 ppm/°C typ.)
  • Power Supply Configurations: - VA+ = +3 V; VA- = -2 V; VD+ = +3 V - Supply Tolerances: ±10%
  • Power Consumption - 23 mW Typical at VD+ = +3 V
  • Simple Four-wire Serial Interface
  • Charge pump driver output generates negative power supply.
  • Ground-referenced Bipolar Inputs

Description

The CS5451A is a highly integrated delta-sigma (∆Σ) an- alog-to-digital converter (ADC) developed for the power measurement industry. The CS5451A combines six ∆Σ ADCs, decimation filters, and a serial interface on a sin- gle chip. The CS5451A interfaces directly to a current transformer or shunt to measure current, and to a resis- tive divider or transformer to measure voltage. The product features a serial interface for communication with a microcontroller or DSP. The product is initialized and fully functional upon reset, and includes a voltage reference. ORDERING INFORMATION: See page 13. VREFIN VREFOUT IIN1+ IIN1- VIN1+ VIN1- VIN2+ VIN2- VIN3+ VIN3- IIN2+ IIN2- IIN3+ IIN3- VA+ VD+ AGND SE FSO SDO SCLK Voltage Reference Serial Interface RESET Decimation Filter Decimation Filter Decimation Filter Decimation Filter Decimation Filter Decimation Filter x1, 20 4th Order ∆Σ Modulator x1, 20 x1, 20 4th Order ∆Σ Modulator 4th Order ∆Σ Modulator 4th Order ∆Σ Modulator 4th Order ∆Σ Modulator 4th Order ∆Σ Modulator GAIN CPD OWRS XIN DGNDVA- Clock Pulse Output Regulator AUG ‘05 DS635F2

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  1. PIN DESCRIPTION Clock Generator Master Clock Input 25 XIN - External clock signal or oscillator input. Control Pins and Serial Data I/O Serial Clock Output 1 SCLK - Serial port clock signal that determines the output data rate for SDO pin. Rate of SCLK is dependent on the XIN frequency and state of OWRS pin. Serial Data Output 2 SDO -Serial port data output pin. Data will be output at a rate defined by SCLK. Frame Sync 3 FSO - Framing signal indicates when data samples are about to be transmitted on the SDO pin. Serial Port Enable 4 SE - When SE is low, the output pins of the serial port are tri-stated. Current Input Gain 5 GAIN - A logic high sets current channel gain to 1, a logic low sets the gain to 20. If no connection is made to this pin, it will default to logic low level (through internal 200 kΩ resistor to DGND). Output Word Rate Select OWRS - A logic low sets the output word rate (OWR) to XIN/2048 (Hz). A logic high sets the OWR to XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low level (through internal 200 kΩ resistor to DGND). Reset 24 RESET - Low activates Reset, all internal registers are set to their default states. Analog Inputs/Outputs Voltage Reference Input 7 VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator. Voltage Reference Output 8 VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magni- tude of 1.2 V and is referenced to the AGND pin on the converter. Differential Voltage Inputs 11,12 18,17 22,21 VIN3+, VIN3- - Differential analog input pins for the voltage channel 3. VIN2+, VIN2- - Differential analog input pins for the voltage channel 2. VIN1+, VIN1- - Differential analog input pins for the voltage channel 1. Differential Current Inputs 13,14 16,15 20,19 IIN3+, IIN3- - Differential analog input pins for the current channel 3. IIN2+, IIN2- - Differential analog input pins for the current channel 2. IIN1+, IIN1- - Differential analog input pins for the current channel 1. Power Supply Connections Analog Ground 6 AGND - Analog ground. Positive Analog Supply 9 VA+ - The positive analog supply. Typical +3 V ±10% relative to AGND. Negative Analog Supply 10 VA- - The negative analog supply. Typical -2 V ±10% relative to AGND. Charge Pump Drive 26 CPD - Designed to drive external charge pump circuitry that will produce a negative analog sup- ply (VA-)voltage. Digital Ground 27 DGND - Digital Ground. Positive Digital Supply 28 VD+ - The positive digital supply. Typical +3 V ±10% relative to AGND. IIN2- VIN2+ IIN2+ RESET IIN1+ IIN1- XIN VIN1- VIN2- CPD DGND VIN1+ VD+ OWRS IIN3- VIN3+ IIN3+ GAIN VA+ VA - SE VREFOUT VIN3- FSO SDO VREFIN SCLK AGND Differential Current Input 2 Differential Voltage Input 2 Differential Current Input 2 Reset Differential Current Input 1 Differential Current Input 1 Master Clock Differential Voltage Input 1 Differential Voltage Input 2 Charge Pump Drive Digital Ground Differential Voltage Input 1 Digital Supply Output Word Rate Select Differential Current Input 3 Differential Voltage Input 3 Differential Current Input 3 Current Input Gain Positive Analog Supply Negative Analog Supply Serial Port Enable Reference Output Differential Voltage Input 3 Frame Sync Serial Data Output Reference Input Serial Clock Output Analog Ground CS5451A

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  1. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS ANALOG CHARACTERISTICS
  • Min/Max characteristics and specifications are guaranteed over all Operating Conditions.
  • Typical characteristics and specifications are meas ured at nominal supply voltages and TA = 25 °C.
  • VA+ = VD+ = 3 V ±10%; VA- = -2 V ±10%; AGND = DGND = 0 V; VREFIN = +1.2 V. All voltages with respect to 0 V.
  • XIN = 4.096 MHz. Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital Positive Analog Negative Analog VD+ VA+ VA- 2.7 2.7 -2.2 3.0 3.0 -2.0 3.3 3.3 -1.8 V V V Voltage Reference Input VREF+ - 1.2 - V Parameter Symbol Min Typ Max Unit Accuracy (All Channels) Total Harmonic Distortion THD 74 - - dB Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB Common Mode + Signal on Input VA- - VA+ V Input Sampling Rate - XIN/4 - Hz Analog Inputs (Note 1) Differential Input Voltage Range Gain=20 [(I IN+) - (IIN-)] or [(VIN+) - (VIN-)] Gain=1 VIN VIN 1.6 mV P-P VP-P Bipolar Offset Gain=20 Gain=1 VOS VOS ±11.5 ±0.5 ±20 ±4.0 mV mV Crosstalk (Channel-to-channel) (50, 60 Hz) - -105 - dB Input Capacitance Gain = 20 Gain = 1 IC IC pF pF Effective Input Impedance Gain=20 Gain=1 EII EII 500 600 kΩ kΩ Noise (Referred to Input) 0-60 Hz Gain=20 Gain=1 0-1 kHz Gain=20 Gain=1 0-2 kHz Gain=20 Gain=1 2.5 3.75 µVrms µVrms µVrms µVrms µVrms µVrms Reference Output Output Voltage REFOUT 1.15 1.2 1.25 V Temperature Coefficient - 25 50 ppm/°C Load Regulation (Output Current 1 µA Source or Sink) ∆V R -6 1 0 m V Power Supply Rejection PSRR 60 - - dB Reference Input Input Voltage Range VREF+ 1.15 1.2 1.25 V Input Capacitance - - 10 pF Input CVF Current - - 1 µA

ANALOG CHARACTERISTICS (continued) Notes: 1. Specifications for Gain = 20 apply only to Current Channels. Voltage Channels are fixed to Gain = 1 2. All outputs unloaded. All inputs CMOS level. 3. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3 V, AGND = DGND = 0 V, VA- = -2 V (using charge- pump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB): DIGITAL CHARACTERISTICS (See Note 4)

  • Min/Max characteristics and specifications are guaranteed over all Operating Conditions.
  • Typical characteristics and specifications are meas ured at nominal supply voltages and TA = 25 °C.
  • VA+ = VD+ = 3V ±10%; VA- = -2 V ±10%; AGND = DGND = 0 V. All voltages with respect to 0 V.
  • XIN = 4.096 MHz Notes: 4. All measurements performed under static conditions. 5. For OWRS and GAIN pins, input leakage current is 30 µA (Max). Parameter Symbol Min Typ Max Unit Power Supplies Power Supply Currents I A+ T y p i c a l V A +=V D +=+ 3V ; V A -=- 2V ID+ with CPD ID+ without CPD PSCA PSCD PSCD 4.0 5.0 1.0 5.3 6.3 1.5 mA mA mA Power Consumption With CPD (Note 2) Without CPD PC PC mW mW Power Supply Rejection (DC) 50, 60 Hz (Note 3) Voltage Channel 50, 60 Hz (Note 3) Current Channel PSRR PSRR PSRR dB dB dB Parameter Symbol Min Typ Max Unit Master Clock Characteristics Master Clock Frequency XIN 3 4.096 5 MHz Master Clock Duty Cycle 40 - 60 % Filter Characteristics High Rate Filter Output Word Rate OWRS = 0 OWRS = 1 OWR OWR XIN/2048 XIN/1024 Hz Hz Input/Output Characteristics High-Level Input Voltage V IH 0.6 VD+ - VD+ V Low-Level Input Voltage V IL 0.0 - 0.8 V High-Level Output Voltage I out = -5.0 mA VOH (VD+) - 1.0 - - V Low-Level Output Voltage I out = 5.0 mA VOL -- 0 . 4 V Input Leakage Current (Note 5) I in -± 1 ± 1 0 µ A 3-State Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -9 - p F PSRR 20 106.07 Veq ⎧⎫log⋅=

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  • Min/Max characteristics and specifications are guaranteed over all Operating Conditions.
  • Typical characteristics and specifications are meas ured at nominal supply voltages and TA = 25 °C.
  • VA+ = VD+ = 3 V ±10%; VA- = -2 V ±10%; AGND = DGND = 0 V. All voltages with respect to 0 V.
  • Logic Levels: Logic 0 = 0 V, Logic 1 = VD+ Notes: 6. Specified using 10% and 90% points on wave-f orm of interest. Output loaded with 50 pF. 7. Device parameters are specified with XIN = 4.096 MHz. 8. Device parameters are specified with OWRS = 1. 9. After SE is asserted, the states of SDO and SCLK are FSO is undefined. Parameter Symbol Min Typ Max Unit Rise Times Any Digital Input (except XIN) (Note 6) XIN only Any Digital Output trise 1.0 µs ns ns Fall Times Any Digital Input (except XIN) (Note 6) XIN only Any Digital Output t fall 1.0 µs ns ns Serial Port Timing Serial Clock Frequency OWRS = “0” (Note 7) OWRS = “1” SCLK SCLK 500 1000 kHz kHz Serial Clock Pulse Width High (Note 7 and 8) Pulse Width Low t 0.5 0.5 SCLK SCLK SCLK falling to New Data Bit t 3 - - 50 ns FSO Falling to SCLK Rising Delay (Note 7 & 8) t 4 -0 . 5- S C L K FSO Pulse Width (Note 7 & 8) t 5 -1- S C L K SE Rising to Output Enabled (Note 9) t 6 - - 50 ns SE Falling to Output in Tri-state t 7 - - 50 ns t2t1 MSB(V1) MSB(V1) - 1 LSB(I3) SE SDO SCLK FSO

Figure 1. Serial Port Timing

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 10. Applies to all pins including continuous over-vol tage conditions at the analog input (AIN) pins. 11. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA. 12. Total power dissipation, including all input currents and output currents. Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital Positive Analog Negative Analog VD+ VA+ VA- -0.3 -0.3 -2.5 +3.5 +3.5 -0.3 V V V Input Current, Any Pin Except Supplies (Note 10 and 11) I IN -- ± 1 0 m A Output Current I OUT -- ± 2 5 m A Power Dissipation (Note 12) PDN - - 500 mW Analog Input Voltage All Analog Pins V INA (VA-) - 0.3 - (VA+) + 0.3 V Digital Input Voltage All Digital Pins V IND -0.3 - (VD+) + 0.3 V Ambient Operating Temperature T A -40 - 85 °C Storage Temperature T stg -65 - 150 °C

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range and simplified anti-alias filter design. mation rate is selectable for two output word rates. Figure 2. Typical Connection Diagram

4.1 Analog Inputs

4.1.1 Voltage Channel

4.1.2 Current Channel

4.2 Digital Filters

stream at XIN/8 and produces a fixed output word rate.

4.3 Performing Measurements

Table 3. Differential Input Voltage vs. Output Code

4.4 Serial Interface

on the SDO output synchronous with the SCLK output. en as long as the SE (serial enable) input is held high. Otherwise, these outputs will be high-impedance. always outputs valid data on the rising edge of SCLK. XIN/8 when OWRS is low or XIN/4 when OWRS is high. Table 1. Current Channel PGA Setting Table 2. Decimation Filter OWR Notes: Assume PGA gain is set to 1x.

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When data is not being transferred SCLK is held low.

4.5 System Initialization

(active) until after the power stabilizes.

4.6 Voltage Reference

nect external filtering and/or references.

4.7 Power Supply

96 SCLKs

Figure 3. One Data Frame Figure 4. Serial Port Data Transfer

charge storage and bypassin g of the negative supply. selected for a XIN clock frequency equal to 4.096 MHz. Figure 5. Generating VA- with a Charge Pump

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  1. PACKAGE DIMENSIONS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-150 28L SSOP PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW
  1. ORDERING INFORMATION 7. ENVIRONMENTAL, MANUFACTURI NG, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 8. REVISION HISTORY Model Temperature Package CS5451A-IS -40 to +85 °C 28-pin SSOP CS5451A-ISZ (lead free) Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5451A-IS 240 °C 2 365 Days CS5451A-ISZ (lead free) 260 °C 3 7 Days Revision Date Changes A1 JUL 2003 Initial Release PP1 OCT 2003 Initial release for Preliminary Product Information F1 FEB 2005 Update electrical specifications w/ most-current characterization data. F2 AUG 2005 Update electrical s pecifications w/ most-current characterization data. Added MSL data. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUD- ING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.