CS5451A CIRRUS | Alldatasheet
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Technical content
Features
On-chip 1. 2V Reference (25ppm/°C typ) Power Supply Configurations: – VA+ = +3 V; VA- = -2 V; VD+ = +3 V – Supply tolerances ±10% Power Consumption – 20 mW Typical at VD+ = +3 V Simple Four-wire Serial Interface Charge Pump Driver output generates negative power supply. Ground-Referenced Bipolar Inputs
Description
The CS5451A is a highly integrated Delta-Sigma (∆Σ) Analog-to-Digital Converter (ADC) developed for the Power Measurement Industry. The CS5451A combines six ∆Σ ADCs, decimation filters, and a serial interface on a single chip. The CS5451A interfaces directly to a cur- rent transformer or shunt to measure current, and resistive divider or transformer to measure voltage. The product features a serial interface for communication with a micro-controller or DSP. The product is initialized and fully functional upon reset, and includes a Voltage Reference. ORDERING INFORMATION: CS5451A-IS -40°C to +85°C 28-pin SSOP VREFIN VREFOUT IIN1+ IIN1- VIN1+ VIN1- VIN2+ VIN2- VIN3+ VIN3- IIN2+ IIN2- IIN3+ IIN3- VA+ VD+ AGND SE FSO SDO SCLK Voltage Reference Serial Interface RESET Decimation Filter Decimation Filter Decimation Filter Decimation Filter Decimation Filter Decimation Filter x1, 20 4th Order ∆Σ Modulator x1, 20 x1, 20 4th Order ∆Σ Modulator 4th Order ∆Σ Modulator 4th Order ∆Σ Modulator 4th Order ∆Σ Modulator 4th Order ∆Σ Modulator GAIN CPD OWRS XIN DGND VA- Clock Pulse Output Regulator OCT ‘03 DS635PP1
Control Pins and Serial Data I/O SE - Serial Port Enable When SE is low, the output pins of the serial port are 3-stated. SDO - Serial Port Output Data will be at a rate determined by SCLK. FSO - Frame Signal Output Framing signal output for data transfer from SDO pin. SCLK - Serial Clock Output A clock signal on this pin determines the output rate of data for SDO pin. Rate of SCLK is determined by XIN frequency and state of OWRS input pin. RESET - Reset When reset is taken low, all internal registers are set to their default states. GAIN - Input Gain Control Sets input gain for current channels. A logic high sets internal gain to 1, a logic low level sets the gain to 20. If no connection is made to this pin, it will default to logic low level (through internal 200 kΩ resistor to DGND). OWRS - Output Word Rate Select When OWRS is set to logic low, the output word rate (OWR) at SDO pin is XIN/2048 (Hz). When set to logic high, the OWR at SDO pin is XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low level (through internal 200 kΩ resistor to DGND). Serial Clock Output SCLK VD+ Digital Supply Serial Data Output SDO DGND Digital Ground Frame Sync FSO CPD Charge Pump Drive Serial Port Enable SE XIN Master Clock Current Input Gain GAIN RESET Reset Analog Ground AGND OWRS Output Word Rate Select Reference Input VREFIN VIN1+ Differential Voltage Input 1 Reference Output VREFOUT VIN1- Differential Voltage Input 1 Positive Analog Supply VA+ IIN1+ Differential Current Input 1 Negative Analog Supply VA- IIN1- Differential Current Input 1 Differential Voltage Input 3 VIN3+ VIN2+ Differential Voltage Input 2 Differential Voltage Input 3 VIN3- VIN2- Differential Voltage Input 2 Differential Current Input 3 IIN3+ IIN2+ Differential Current Input 2 Differential Current Input 3 IIN3- IIN2- Differential Current Input 2
Measurement and Reference Input IIN(1-3)+, IIN(1-3)- - Differential Current Inputs Differential analog input pins for current channels. VIN(1-3)+, VIN(1-3)- - Differential Voltage Inputs Differential analog input pins for voltage channels. VREFOUT - Voltage Reference Output The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of 1.2 V and is referenced to the AGND pin on the converter. VREFIN - Voltage Reference Input The voltage input to this pin establishes the voltage reference for the on-chip modulator. Power Supply Connections VA+ - Positive Analog Supply The positive analog supply is nominally +3V ±10% relative to AGND. VA- - Negative Analog Supply The negative analog supply is nominally - 2V ±10% relative to AGND. AGND - Analog Ground The analog ground pin for input signals. VD+ - Positive Digital Supply The positive digital supply is nominally +3V ±10% relative to DGND. DGND - Digital Ground The digital ground is typically at the same level as AGND. CPD - Charge Pump Drive This output pin drives the external charge pump circuitry to create a negative supply voltage.
CHARACTERISTICS AND SPECIFICATIONS Min / Max characteristics and specifications are guaranteed over all Operating Conditions Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. DGND = 0 V. All Voltages with respect to 0V. ANALOG CHARACTERISTICS Notes: All “Gain = 20” specifications apply only to the Current Channels. Voltage Channels are set to Gain=1. Effective Input Impedance (EII) varies with clock frequency (XIN) and Input Capacitance (IC) EII = 1/(IC*XIN/4) Parameter Symbol Min Typ Max Unit Accuracy (All Channels) Total Harmonic Distortion THD dB Common Mode Rejection (DC, 50, 60 Hz) CMRR dB Common Mode + Signal on Input VA- VA+ V Input Sampling Rate XIN/4 Hz Analog Inputs(Note 1) Differential Input Voltage Range Gain=20 [(IIN+) - (IIN-)] or [(VIN+) - (VIN-)] Gain=1 VIN VIN 1.6 mVP-P VP-P Bipolar Offset Gain=20 Gain=1 VOS VOS 0.500 mV mV Crosstalk (Channel-to-Channel) (50, 60 Hz) -120 dB Input Capacitance Gain = 20 Gain = 1 IC IC pF pF Effective Input Impedance (Note 2) Gain=20 Gain=1 EII EII 500 600 kΩ kΩ Noise (Referred to Input) 0-60 Hz Gain=20 Gain=1 0-1 kHz Gain=20 Gain=1 0-2 kHz Gain=20 Gain=1 2.5 3.75 µVrms µVrms µVrms µVrms µVrms µVrms Dynamic Characteristics High Rate Filter Output Word Rate OWRS = “0” OWRS = “1” OWR OWR XIN/2048 XIN/1024 Hz Hz
ANALOG CHARACTERISITCS (continued) Notes: All outputs unloaded. All inputs CMOS level. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3V, AGND = DGND = 0V, VA- = - 2V (using charge-pump circuit with CPD). In addition, a 106.0 7mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB): DIGITAL CHARACTERISTICS (See Note 5) Notes: All measurements performed under static conditions. For OWRS and GAIN pins, input leakage current is 30 µA (Max). Parameter Symbol Min Typ Max Unit Reference Output Output Voltage REFOUT 1.15 1.25 V Temperature Coefficient ppm/°C Load Regulation (Output Current 1 µA Source or Sink) ∆VR mV Power Supply Rejection PSRR dB Reference Input Input Voltage Range VREF+ 1.15 1.2 1.25 V Input Capacitance pF Input CVF Current µA Power Supplies Power Supply Currents IA+ ID+ PSCA PSCD mA mA Power Consumption (Note 3) PC mW Power Supply Rejection (DC) (see Note 4) (50, 60 Hz) PSRR PSRR dB dB Parameter Symbol Min Typ Max Unit High-Level Input Voltage VIH
0.6 VD+
V Low-Level Input Voltage VIL 0.0 0.8 V High-Level Output Voltage Iout = -5.0 mA VOH (VD+) - 1.0 V Low-Level Output Voltage Iout = 5.0 mA VOL 0.4 V Input Leakage Current (Note 6) Iin ±10 µA 3-State Leakage Current IOZ ±10 µA Digital Output Pin Capacitance Cout pF PSRR 106.07 Veq log
RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS Notes: Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital Positive Analog Negative Analog VD+ VA+ VA- 2.7 2.7 -2.2 3.0 3.0 -2.0 3.5 3.5 -1.8 V V V Voltage Reference Input VREF+ 1.2 V Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital Positive Analog Negative Analog VD+ VA+ VA- -0.3 -0.3 -2.5 +3.5 +3.5 -0.3 V V V Input Current, Any Pin Except Supplies (Note 7 and 8) IIN ±10 mA Output Current IOUT ±25 mA Power Dissipation (Note 9) PDN 500 mW Analog Input Voltage All Analog Pins VINA (VA-) - 0.3 (VA+) + 0.3 V Digital Input Voltage All Digital Pins VIND -0.3 (VD+) + 0.3 V Ambient Operating Temperature TA -40 Storage Temperature Tstg -65 150
Device parameters are specified with a 4. 000MHz clock, OWRS = 1. Specified using 10% and 90% points on wave-form of interest. Output loaded wi th 50pF. Figure 1. Serial Port Timing
vider or transformer to measure voltage. The device outputs data on a serial output port. Figure 2. Typical Connection Diagram
Table 1. Nominal Relationship for Differential Input XIN/8 Hz and decimates to XIN/2048 Hz. at XIN/8 Hz and decimates to XIN/1024 Hz.
SCLK is not active during FSO high. is forced low with a minimum pulse width of 50 ns. 1.6 VP-P on the Voltage Channels. V reference between the VREFIN and AGND pins.
96 SCLKs
Figure 3. Serial Port Data Transfer Figure 4. Close-up of One Data Frame
ternal reference can be used. ulate the VA- level to -2/3 of VA+ level.
4.5 MHz, this represents a percentage increase of
Pump Drive for External Loads. Note 18 for more detailed layout guidelines. Figure 5. Generating VA- with a Charge Pump
- PACKAGE DIMENSIONS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.0 7mm at least material condition. These dimensions apply to the flat section of the lead between 0.10 a nd 0.25mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0.084 2.13 0.002 0.006 0.010 0.05 0.13 0.25 0.064 0.069 0.074 1.62 1.75 1.88 b 0.009 0.015 0.22 0.38 2,3 D 0.390 0.4015 0.413 9.90 10.20 10.50 E 0.291 0.307 0.323 7.40 7.80 8.20 0.197 0.209 0.220 5.00 5.30 5.60 e 0.022 0.026 0.030 0.55 0.65 0.75 L 0.025 0.0354 0.041 0.63 0.90 1.03 JEDEC #: MO-150 28L SSOP PACKAGE DRAWING E N 1 2 3 e A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW
13 October 2003 Initial release for Preliminary Product Information
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