CS5343 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
! Advanced Multi-Bit ∆Σ Architecture ! 24-bit Conversion ! Supports Audio Sample Rates Up to 108 kHz ! 98 dB Dynamic Range at 5 V ! -90 dB THD+N ! Low-Latency Digital Filter ! High-Pass Filter to Remove DC Offsets ! Single +3.3 V or +5 V Power Supply ! Power Consumption Less Than 50 mW ! Master or Slave Operation ! Slave Mode Speed Auto-Detect ! Master Mode Default Settings ! 256x or 384x MCLK/LRCK Ratio ! CS5343 Supports I²S Audio Format ! CS5344 Supports Left-Justified Audio Format General Description The CS5343/4 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analog- to-digital conversion, and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 108 kHz per channel. The CS5343/4 uses a 3rd-order, multi-bit Delta-Sigma modulator followed by a digital filter, which removes the need for an external anti-alias filter. The CS5343/4 also features a high-impedance sam- pling network which eliminates costly external components such as op-amps. The CS5343/4 is available in a 10-pin TSSOP package for both Commercial (-10° to +70° C) and Automotive grades (-40° to +85° C). The CDB5343 Customer Dem- onstration Board is also available for device evaluation and implementation suggestions. Please refer to the “Ordering Information” on page 21 for complete details. The CS5343/4 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as set-top boxes, DVD-karaoke players, DVD record- ers, A/V receivers, and automotive applications. High-Pass Filter High-Pass Filter Low-Latency Digital Filters VA
3.3 V to 5 V
AUGUST '06 DS687A4 CS5343/4
- PIN DESCRIPTIONS Pin Name Pin # Pin Description SDOUT Serial Audio Data Output (Output) - Output for two’s complement serial audio data. Also selects Master or Slave Mode. SCLK Serial Clock (Input/Output) - Serial clock for the serial audio interface. LRCK Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. MCLK Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. FILT+ Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. AINL AINR Analog Input (Input) - The full-scale analog input level is specified in the Analog Characteristics specifi- cation table. VQ Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. GND Ground (Input) - Ground reference. Must be connected to analog ground. VA Power (Input) - Positive power supply for the digital and analog sections. SDOUT SCLK LRCK MCLK FILT+ VA GND AINR VQ AINL
- CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TA = 25°C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to GND.) ABSOLUTE MAXIMUM RATINGS (GND = 0 V, all voltages with respect to GND.) (Note 1) Notes: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. The maximum over/under voltage is limited by the input current. Parameter Symbol Min Typ Max Unit Power Supplies VA 3.1 4.75 3.3 5.0 3.5 5.25 V V Ambient Operating Temperature Commercial Automotive TAC TAD -10 -40 Parameter Symbol Min Max Unit DC Power Supplies VA -0.3 +6.0 V Input Current (Note 2) Iin -10 +10 mA Input Voltage (Note 3) VIN -0.7 VA+0.7 V Ambient Operating Temperature (Power Applied) TA -50 +115 Storage Temperature Tstg -65 +150
ANALOG CHARACTERISTICS - COMMERCIAL GRADE Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; source impedance less than or equal to 2.5 kΩ. Notes: Referred to the typical full-scale input voltage Dynamic Performance for Commercial Grade VA = 3.3 V VA = 5.0 V Single-Speed Mode Fs = 48 kHz Symbol Min Typ Max Min Typ Max Unit Dynamic Range A-weighted unweighted dB dB Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB THD+N -86 -75 -35 -80 -90 -78 -38 -84 dB dB dB Double-Speed Mode Fs = 96 kHz Min Typ Max Min Typ Max Unit Dynamic Range A-weighted unweighted dB dB Total Harmonic Distortion + Noise (Note 4) -1 dB -20 dB -60 dB THD+N -86 -75 -35 -80 -90 -78 -38 -84 dB dB dB Dynamic Performance for Commercial Grade - All Modes Min Typ Max Unit Interchannel Isolation dB DC Accuracy Interchannel Gain Mismatch 0.1 dB Gain Error Gain Drift ±100 ppm/°C Analog Input Characteristics Full-scale Input Voltage 0.51*VA 0.56*VA 0.57*VA Vpp Input Impedance 7.5 MΩ
ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; source impedance less than or equal to 2.5 kΩ. Notes: Referred to the typical full-scale input voltage Dynamic Performance for Automotive Grade VA = 3.3 V VA = 5.0 V Single-Speed Mode Fs = 48 kHz Symbol Min Typ Max Min Typ Max Unit Dynamic Range A-weighted unweighted dB dB Total Harmonic Distortion + Noise (Note 5) -1 dB -20 dB -60 dB THD+N -86 -75 -35 -78 -90 -78 -38 -82 dB dB dB Double-Speed Mode Fs = 96 kHz Min Typ Max Min Typ Max Unit Dynamic Range A-weighted unweighted dB dB Total Harmonic Distortion + Noise (Note 5) -1 dB -20 dB -60 dB THD+N -86 -75 -35 -78 -90 -78 -38 -82 dB dB dB Dynamic Performance for Automotive Grade - All Modes Min Typ Max Unit Interchannel Isolation dB DC Accuracy Interchannel Gain Mismatch 0.1 dB Gain Error Gain Drift ±100 ppm/°C Analog Input Characteristics Full-scale Input Voltage 0.51*VA 0.56*VA 0.57*VA Vpp Input Impedance 7.5 MΩ
DIGITAL FILTER CHARACTERISTICS Notes: Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to 0 V. MCLK=12.288 MHz; Master Mode) Notes: Device enters power-down mode when MCLK is held static. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram. Parameter Symbol Min Typ Max Unit Single-Speed Mode Fs = 4 - 54 kHz Passband (-0.1 dB) 0.489 Fs Passband Ripple -0.025 0.025 dB Stopband 0.560 Fs Stopband Attenuation dB Total Group Delay (Fs = Output Sample Rate) tgd 12/Fs s Double-Speed Mode Fs = 86 - 108 kHz Passband (-0.1 dB) 0.489 Fs Passband Ripple -0.025 0.025 dB Stopband 0.560 Fs Stopband Attenuation dB Total Group Delay (Fs = Output Sample Rate) tgd 9/Fs s High-Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB (Note 6) Hz Hz Phase Deviation @ 20 Hz (Note 6) Deg Passband Ripple dB Parameter Symbol VA = 3.3 V VA = 5.0 V Min Typ Max Min Typ Max Unit DC Power Supplies: VA 3.1 3.3 5.25 V Power Supply Current (Normal Operation) IA mA Power Supply Current (Power-Down Mode) (Note 7) IA 1.1 1.1 mA Power Consumption (Normal Operation) (Power-Down Mode) (Note 7) 3.6 5.5 mW mW Parameter Symbol Min Typ Max Unit Power Supply Rejection Ratio (1 kHz) (Note 8) PSRR dB VQ Nominal Voltage Output Impedance 0.44xVA V kΩ Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink VA 220 2.5 V kΩ uA
(% of VA) VIH Low-Level Input Voltage (% of VA) VIL High-Level Output Voltage at Io = 500 µA (% of VA) VOH Low-Level Output Voltage at Io =500 µA (% of VA) VOL Input Leakage Current Iin -10 µA
SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE (Logic “0” = GND = 0 V; Logic “1” = VA, CL = 20 pF) Parameter Symbol Min Typ Max Unit Master Mode MCLK Period (Double-Speed, 384x Mode) tclkw ns (Double-Speed, 192x Mode) ns (Double-Speed, 256x Mode) ns (Double-Speed, 128x Mode) ns (Single-Speed, 768x Mode) 325 ns (Single-Speed, 384x Mode) 651 ns (Single-Speed, 512x Mode) 488 ns (Single-Speed, 256x Mode) 976 ns MCLK Duty Cycle Output Sample Rate (Single-Speed) (Double-Speed) Fs 108 kHz kHz LRCK Duty Cycle SCLK Duty Cycle SDOUT valid before SCLK rising tstp ns SDOUT valid after SCLK rising thld ns SCLK falling to LRCK edge tslrd -20 ns Slave Mode MCLK Period (Double-Speed, 384x Mode) tclkw ns (Double-Speed, 192x Mode) ns (Double-Speed, 256x Mode) ns (Double-Speed, 128x Mode) ns (Single-Speed, 768x Mode) 325 ns (Single-Speed, 384x Mode) 651 ns (Single-Speed, 512x Mode) 488 ns (Single-Speed, 256x Mode) 976 ns MCLK Duty Cycle Input Sample Rate (Single-Speed) (Double-Speed) Fs 108 kHz kHz LRCK Duty Cycle SCLK Period tsclkw ns SCLK Duty Cycle SDOUT valid before SCLK rising tstp ns SDOUT valid after SCLK rising thld ns SCLK falling to LRCK edge tslrd -20 ns Fs
- TYPICAL CONNECTION DIAGRAM
Figure 3. Typical Connection Diagram
9 GND
5 FILT+
1 Pull-up to VA for Master Mode
2 Optional pull-up resistor for configur-
serial clocks are synchronously generated on-chip and output on the LRCK and SCLK pins, respectively. lection, as shown in Table 1. 4 to 108 kHz. Please refer to Table 2 for supported sample rate ranges in Slave Mode. Table 2. Speed Modes and the Associated Sample Rates (Fs) in Slave Mode Table 1. Master/Slave Mode Selection
available sample rates and associated clock ratios in Master Mode. MCLK/LRCK ratio of 348x is accessed with a 10 kΩ pull-up resistor from SCLK to VA as shown in Table 4. Following the power-up routine, the LRCK and SCLK pins become clock outputs. The CS5343/4 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. MCLK. Table 4 lists some common audio output sample rates and the required MCLK frequency. Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode Table 4. Speed Mode Selection in Master Mode Table 5. Common MCLK Frequencies in Master and Slave Modes
- PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measure- ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error
- PACKAGE DIMENSIONS Notes: Reference document: JEDEC MO-187 D does not include mold flash or protrusions which is 0.15 mm max. per side. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max. Exceptions to JEDEC dimension. THERMAL CHARACTERISTICS INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0.0433 1.10 0.0059 0.15 0.0295 0.0374 0.75 0.95 b 0.0059 0.0118 0.15 0.30 4, 5 c 0.0031 0.0091 0.08 0.23 D
0.1181 BSC
3.00 BSC
E
0.1929 BSC
4.90 BSC
e
0.0197 BSC
0.50 BSC
L 0.0157 0.0236 0.0315 0.40 0.60 0.80
0.0374 REF
0.95 REF
µ Controlling Dimension is Millimeters Parameter Symbol Min Typ Max Unit Allowable Junction Temperature TJ 135 Junction to Ambient Thermal Impedance (4-layer PCB) (2-layer PCB) θJA-4 θJA-2 100 170 °C/W °C/W 10LD TSSOP (3 mm BODY) PACKAGE DRAWING (Note 1) E N 1 2 3 e b A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW c
- ORDERING INFORMATION 9. REVISION HISTORY Product
Description
Order # CS5343 98 dB, Multi-Bit Audio A/D Converter, I²S Audio Format 10-TSSOP Yes Commercial -10° to +70° C Rail CS5343-CZZ Tape & Reel CS5343-CZZR CS5343 98 dB, Multi-Bit Audio A/D Converter, I²S Audio Format 10-TSSOP Yes Automotive -40° to +85° C Rail CS5343-DZZ Tape & Reel CS5343-DZZR CS5344 98 dB, Multi-Bit Audio A/D Converter, Left-Justified Audio Format 10-TSSOP Yes Commercial -10° to +70° C Rail CS5344-CZZ Tape & Reel CS5344-CZZR CS5344 98 dB, Multi-Bit Audio A/D Converter, Left-Justified Audio Format 10-TSSOP Yes Automotive -40° to +85° C Rail CS5344-DZZ Tape & Reel CS5344-DZZR CDB5343 CS5343 Evaluation Board No CDB5343 Release Changes Changes made to Serial Port diagrams. See Figure 1 and Figure 2 on page 11. Replaced block diagram on cover page. Increased minimum hold time (Thld) specification on page 10. Updated Table 4, “Speed Mode Selection in Master Mode,” on page 14. Corrected MCLK timing specifications on page 10 Corrected “Typical Connection Diagram” on page 12 Corrected Table 3, “Speed Modes and the Associated Sample Rates (Fs) in Master Mode,” on page 14 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the infor- mation only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.