CS5331A

CS5330A CIRRUS | Alldatasheet

Document overview

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Technical content

Features

• Single +5 V Power Supply
• 18-Bit Resolution
• 94 dB Dynamic Range
• Linear Phase Digital Anti-Alias Filtering 0.05dB Passband Ripple 80dB Stopband Rejection
• Low Power Dissipation: 150 mW Power-Down Mode for Portable

Applications

• Complete CMOS Stereo A/D System Delta-Sigma A/D Converters Digital Anti-Alias Filtering S/H Circuitry and Voltage Reference
• Adjustable System Sampling Rates including 32kHz, 44.1 kHz & 48kHz General Description The CS5 330A / 31A is a complete stereo analog-to- digital converter w hich performs anti-alias filtering, sampling and analog-to-digital conversion generating 18-bit values for both left and right inputs in serial form. The output sample rate can be infinitely adjusted be- tween 2 and 50 kHz. The CS5330A / 31A operates from a single +5V supply and requires only 150 mW for normal operation, mak- ing it ideal for battery-powered applications. The ADC uses delta-sigma modulation with 128X over- sampling, followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The linear-phase digital filter has a passband to 21.7 kHz, 0.05 dB passband ripple and >80 dB stop- band rejection. The device also contains a high pass filter to remov e DC offsets. The device is available in a 0.208" wide, 8-pin surface m ount package. ORDERING INFORMA TION: Mod el Temp. Range Package Type CS53 30A-KS -10° to 70°C 8-pin plastic SOIC CS53 31A-KS -10° to 70°C 8-pin plastic SOIC CS53 30A-BS -40° to +85°C 8-pin plastic SO IC CS53 31A-BS -40° to +85°C 8-pin plastic SO IC Cirrus Logic, Inc. Crystal Semiconductor Product Division P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 http://www.crystal.com MAR ’99 DS 138F2 8-Pin, Stereo A/D Converter for Digital Audio CS5330A CS5331A AINR S/H AGND AINL S/H DAC Serial Output Interface Voltage Reference Comparator Comparator LP Filter LP Filter VA+ SCLK Digital Decimation Filter Digital Decimation Filter SDATA MCLK DAC High Pass Filter High Pass Filter LRCK 4 2 3 Copyright  Cirrus Logic, Inc. 1999 (All Rights Reserved)

ANALOG CHARACTERISTICS (TA = 25°C; VA+ = 5V; -1 dBFS Input Sinewave, 997 H z; Fs = 48 kHz; MCLK = 12.288 MH z; SCLK = 3.072 MHz; Measurement Bandwidth is 10 H z to 20 kHz unless oth- erwise specified; Logic 0 = 0V, Logic 1 = VD+) Param eter Sym bol 5330A /31A-KS Min Typ Max 5330A /31A-BS Min Typ Max Units Tem perature Range TA -10 to +70 -40 to +85 °C Dynamic Performance Dynamic Range A-weighted 88 94 - 86 92 - 86 94 - 84 92 - dB dB Total Harmonic Distortion+Noise (N ote 1) -1dB -20dB -60dB THD +N - -84 75 - -72 66 - -32 26 - -84 75 - -72 66 - -32 26 dB dB dB Total Harmonic Distortion -1dB THD - 0.003 0.02 - 0.003 0.02 % Interchannel Phase Deviation - 0 - - 0 - D egree Interchannel Isolation (dc to 20 kHz) - 90 - - 90 - dB dc Accuracy Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Gain Error - - ±10 - - ±10 % Gain Drift - 150 - - 150 - ppm /°C O ffset Error (N ote 2) - - 0 - - 0 LSB Analog Input Input Impedance (Fs = 48 kHz) ZIN - 100 - - 100 - kΩ Input Bias Voltage - 2.4 - - 2.4 - V Power Supplies Power Supply Current (N ote 3) VA+ Power down IA+ - 30 42 - 100 1000 - 30 42 - 100 1000 mA µA Pow er Dissipation (N ote 3) N orm al Power Down - 150 220 - 0.5 5.25 - 150 220 - 0.5 5.25 mW mW Power Supply Rejection Ratio PSRR - 50 - - 50 - dB * Refer to Parameter Definitions at the end of this data sheet. Notes: 1.Referenced to typical full-scale input voltage (4.0 Vpp) 2.Internal highpass filter rem oves offset. 3.For max power calculations, VD = 5.25 V. CS5 330A/C S5331A

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DIGITAL FILTER CHARACTERISTICS (TA = 25 °C; VA+ = 5V ± 5% ; Fs = 48 kHz) Param eter Symbol Min Typ Max Units Passband (0.05 dB) (Note 4) 0.02 - 21.7 kHz Passband Ripple - - ±0.05 dB Stopband (N ote 4) 29 - 6115 kH z Stopband Attenuation (N ote 5) 80 - - dB G roup D elay (N ote 6) tgd - 15/Fs - s Group Delay Variation vs. Frequency Δtgd - - 0 µs High Pass Filter Characteristics Frequency Response: -3 dB (Note 4) -0.1 dB 3.7 Hz Hz Phase Deviation @ 20 Hz (Note 4) - 10 - Degree Passband Ripple - - 0 dB Notes: 4.Filter characteristics scale with output sample rate. 5.The analog modulator samples the input at 6.144 MH z for an output sample rate of 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency ( n x 6.144 MH z ±21.7kHz w here n = 0,1,2,3...). 6.Group delay for Fs = 48kHz, t gd = 15/48kHz = 312µs DIGITAL CHARACTERISTICS Param eter Symbol Min Typ Max Units High-Level Input Voltage VIH 2.4 - - V Low-Level Input Voltage VIL - - 0.8 V High-Level Output Voltage at lo = -20 µA VOH (VD+)-1.0 - - V Low-Level Output Voltage at lo = 20 µA VOL - - 0.4 V Input Leakage Current Iin - - ±10.0 µA CS5 330A/C S5331A DS1 38F2 3

ABSOLUTE MAXIMUM RATING S (AGND = 0V, all voltages with respect to ground.) Param eter Symbol Min Typ Max Units DC P ower Supply: VA+ -0.3 - +6.0 V Input C urrent, Any Pin Except Supplies (N ote 7) Iin - - ±10 mA Analog Input Voltage (Note 8) VINA -0.7 - (VA+)+0.7 V Digital Input Voltage (Note 8) VIND -0.7 - (VA+)+0.7 V Ambient Temperature (power applied) TA -55 - +125 °C Storage Temperature Tstg -65 - +150 °C Notes: 7.Any Pin except supplies. Transient currents of up to +/- 100 mA on the analog input pins will not cause SCR latch-up. 8.The m aximum over/under voltage is limited by the input current. W ARNING :Operation at or beyond these limits may result in permanent damag e to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATIN G CONDITIONS (AGND = 0V; all voltages with respect to ground) Param eter Sym bol M in Typ M ax Units DC P ower Supplies: VA+ 4.75 5.0 5.25 V Analog Input Voltage (Note 9) VIN -4 - Vpp Analog Input Bias Voltage 2.2 2.4 2.6 V Note: 9.The output codes will clip at full scale with input signals > Full Scale and < VA+. Specifications are subject to change without notice. CS5 330A/C S5331A

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SWITCHING CHARACTERISTICS (TA = 25 °C ; VA+ = 5V ± 5% ; Inputs: Logic 0 = 0V, Logic 1 = VA+ ; CL = 20 pF) Switching characteristics are guaranteed by characterization. Param eter Symbol M in Typ M ax Units Output Sample R ate Fs 2 - 50 kHz MCLK Period MCLK / LRCK = 256 t clkw 78 1000 ns MCLK Low MCLK / LRCK = 256 t clkl 31 - 1000 ns MCLK High MCLK / LRCK = 256 t clkh 31 - 1000 ns MCLK Period MCLK / LRCK = 384 t clkw 52 1000 ns MCLK Low MCLK / LRCK = 384 t clkl 20 - 1000 ns MCLK High MCLK / LRCK = 384 t clkh 20 - 1000 ns MCLK Period MCLK / LRCK = 512 t clkw 39 1000 ns MCLK Low MCLK / LRCK = 512 t clkl 13 - 1000 ns MCLK High MCLK / LRCK = 512 t clkh 13 - 1000 ns MASTER MODE SCLK falling to LRCK t mslr -10 - 10 ns SCLK falling to SDATA valid t sdo -10 - 35 ns SCLK Duty cycle - 50 - % SLAVE MODE LRCK duty cycle 25 50 75 % SCLK Period t sclkw (N ote 10) - - ns SCLK Pulse W idth Low t sclkl (N ote 11) - - ns SCLK Pulse W idth High t sclkh 20 - - ns SCLK falling to SDATA valid t dss - - (Note 12) ns LRCK ed ge to MSB v alid t lrdss - - (Note 12) ns SCLK rising to LRCK edge delay t slr1 20 - - ns LRC K edge to rising SC LK setup time t slr2 (N ote 12) - - ns Notes: 10. 1 64 F s 11. 1 128 Fs −15 ns 12. 1 256 Fs + 5 ns CS5 330A/C S5331A DS1 38F2 5

(SLAVE mode) (SLAVE mode) LRCK input sclkht dsst M SB MS B-1 sclkltslr1t slr2t tsclkw SCL K to LRCK & SDAT A - SLAVE mode (CS5331A) SCLK output tmslr SDATA tsdo LRCK output SCLK to SDATA LRC K - M A STE R mode (CS5331A) SCLK output SD ATA tsdo LRC K output tmslr SCL K to SDATA LRCK - MASTER mode (C S5330A) SDA TA SC LK input (SLAVE mode) (SLAVE mode) LRCK input sclkht dsst MSB M SB-1 MS B-2 lrdsst sclkltslr1t slr2t tsclkw SCL K to LRCK & SDAT A - SLAVE mode (C S5330A) CS5 330A/C S5331A

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Figure 1. T ypical Connection Diagram

The C S5330A and CS5331A are 18-bit, 2-chan- nel An alog-to-Digital C onverters designed for digital audio applications. Each device uses two one-bit delta-sigma mo dulators which simultane- ously samp le the analog input signals at 128 tim es the output sample rate (Fs). The resulting serial bit stream s are digitally filtered, yielding pairs of 18-bit values. This technique yields nearly ideal conversion performance independent of input frequency and amplitude. The converters do not require difficult-to-design or expensive anti-alias filters and do not require external sam- ple-and-hold am plifiers or a voltage reference. The CS5 330A and CS5331A differ only in the output serial data form at. These formats are dis- cussed in the following sections and shown in Figures 2 and 3. An on-chip voltage reference provides for a sin- gle-ended input signal range of 4.0 V pp. O utput data is available in serial form, coded as 2’s com plement 18-bit numbers. Typical power con- sumption is 150 mW whi ch c an be further reduced to 0 .5 m W using the Powe r-Down mode. For more inform ation on delta-sigma m odula- tion, see the references at the end of this data sheet. SYSTE M DES IGN Very few external comp onents are required to support the ADC. Normal pow er supply decou- pling com ponents and a resistor and capacitor on each input for anti-aliasing are all that’s required, as shown in Figure 1. Master C lock The master clock (MC LK) runs the digital filter and is used to generate the delta-sigma m odula- tor sam pling clock. Table 1 show s som e com m on m aster clock frequencies. The output samp le rate is equal to the frequency of the Left / Right C lock (LRC K). The serial nature of the output data results in the left and right data words being read at different tim es. How ever, the w ords w ithin an LR CK cycle represent sim ultaneously sampled analog inputs. The serial clock (SC LK) shifts the digitized audio data from the internal data registers via the SD ATA pin. Serial Data Interface The C S5330A and C S5331A can be operated in either Master mode, where SC LK and LR C K are outputs, or SL AV E m ode, w here SC LK and LR C K are inputs. M aster Mode In Master mode, SCLK and LR C K are outputs w hich are internally derived from MC LK. The C S5330A/31A w ill divide M C LK by 4 to gener- ate a SC LK wh ich is 64× Fs and by 256 to generate LR CK. T he CS5 330A a nd CS5 331A can be placed in the Master mo de wi th a 47 kohm pu ll-down resistor on the SD ATA pin as show n in Figure 1. Slave Mode LR C K and SCLK be come i nputs in SL AVE mo de. LR CK must be externally derived from M C LK a nd be equal to Fs. The frequency of SC LK sh ould be equal to 64× LR CK, though other frequencies are possible. M C LK frequencies of 256×, 384×, and 512× Fs are supported. The ratio of the applied M C LK to LRCK (kH z) MCLK (MHz) 256× 384× 512× 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 T able 1. Com m on Clock Frequencies CS5 330A/CS5331A

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Figure 1 shows the analog input connections. The analog inputs are presented to the m odula- tors via the AINR and AINL p ins. Each analog input w ill accept a maximum of 4 Vpp centered at +2.4 V. The CS5 330A /31A sam ples the analog inputs at 128× Fs, 6.144 MHz f or a 48 kHz sam ple-rate. The digital filter rejects all noise above 29 kHz except for frequencies right around 6.144 MHz ± 21.7 kHz (and mu ltiples of 6.144 MH z). Most audio signals do not have significant energy at 6.144 MHz. N evertheless, a 150 Ω resistor in se- ries wi th ea ch an alog input and a 10 nF capacitor across the inputs will attenuate any noise energy at 6.144 MHz, in addition to pro- viding the optim um source im pedance for the mod ulators. The use of capacitors which have a large voltage coefficient must be avoided since these will degrade signal linearity. It is also im- portant that the self-resonant frequency of the capacitor be well above the modulator sam pling frequency. Gen eral purpose ceramics and film capacitors do not meet these requirements. How- ever, NPO and COG capacitors are acceptable. If active circuitry precedes the ADC, it is recom- men ded that the above RC filter is placed between the active circuitry and the AINR a nd AINL pins. The above exam ple frequencies scale linearly with Fs. High Pass Filter The operational am plifiers in the input circuitry driving the CS5330A /31A may g enerate a small DC o ffset into the A /D converter. T he CS 5330A/31A includes a high pass filter after the decim ator to remo ve any DC o ffset which could result in recording a DC l evel, possibly yielding "clicks" when switching between de- vices in a multichannel system. The characteristics of this first-order high pass filter are outlined below for Fs equal 48 kHz. This filter response scales linearly w ith sam ple rate. Frequency response:-3 dB @ 3.7 Hz -0.1 dB @ 20 Hz Phase deviation:10 degrees @ 20 Hz Passband ripple:None Initialization and Power-Dow n The Initialization and Powe r-Down sequence is shown in Figure 4. Upon initial powe r-up, the digital filters and delta-sigma mod ulators are re- set and the internal voltage reference is powered dow n. The device will rem ain in the Initial Powe r-Down mo de until M C LK is presented. O nce MCLK is available, the C S5330A/31A w ill mak e a master/slave mo de decision based upon the presence/absence of a 47 kohm pull-dow n re- sistor on SD ATA as shown in Figure 1. The master/slave decision is made d uring initial pow er-up as shown in Figure 4. In master mode, SC LK and LR C K are outputs w here the MCLK / LR C K frequency ratio is 256×. LR C K will appear as an ou tput 127 M C LK cycles into the initialization sequence. At this time, powe r is applied to the internal voltage reference and the analog inputs will move to ap- proxim ately 2 .4 Volts. SD ATA is s tatic low during the initialization and high pass filter set- tling sequence, which requires 11,265 LRCK cycles (235 ms at a 48 kH z output sample rate). In slave mo de, SC LK a nd L R CK are inputs w here the MCLK / LR C K frequency ratio must be either 256×, 384× or 512×. Once the M C LK and LR CK are detected, MC LK occurrences are counted over one LR CK period to determine the M C LK / LRC K frequency ratio. At this tim e, pow er is applied to the internal voltage reference and the analog inputs will m ove to approxi- m ately 2.4 Volts. SD ATA is static high during the initialization and h igh pass filter settling se- quence, which requires 11,265 LR C K cycles (235 ms at a 48 kHz sam ple rate). CS5 330A/CS5331A

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Slave Mod e, or the MCLK p in in M aster Mode. M C LK, and LRC K for slave mode, are restored. plemen ted by gating the MCLK signal. the ADC di gital outputs only to C MO S inputs. Figure 4. CS5330A/31A Initialization and Power-Dow n Sequence

teristics of the digital filter included in the ADC. system sample rate, i.e. 48kHz. Figure 5. CS5330A/31A Digital Filter Stopband Rejection Figure 7. CS5330A/31A Digital Filter Passband Ripple Figure 8. CS5330A/31A Digital Filter T ransition Band Figure 6. CS5330A/31A Digital Filter T ransition Band Call Applications Engineering. Call Applications Engineering.

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VA + - Positive Analog Powe r, PIN 7. Positive analog supply (Nom inally +5V). A GND - An alog Ground, PIN 6. An alog ground reference. A nalog Inputs AINL - Analog Left Channel Input, PIN 8. An alog input for the left channel. Typically 4Vpp for a full-scale input signal. AIN R - Analog Right Channel Input, PIN 5. An alog input for the right channel. Typically 4Vpp for a full-scale input signal. Digital Inputs MCLK - M aster Clock Input, PIN 4. Source for the delta-sigma mod ulator sampling and digital filter clock. Sample rates and digital filter characteristics scale to the MCLK frequency. Digital Inputs or Outputs SCLK - Serial Data Clock, PIN 2. SCLK is an input clock at any frequency from 32× tο 64× the output word rate. SCLK c an also be an output clock at 64× if in the M aster Mode. Data is clocked out on the falling edge of SCLK. LRCK - L eft/Right Clock, PIN 3. LRCK se lects the left or right channel for output on SD ATA. The LR C K frequency must be at the output sample rate. LRCK is an output clock if in M aster M ode. Although the outputs of each channel are transmitted at different tim es, the tw o w ords in an LRCK cycle represent simultaneously sam pled analog inputs. Digital Outputs SD ATA - A udio Serial Data Output, PIN 1. Tw o’s comp lement MS B -first serial data is output on this pin. A 47 kohm resistor on this pin will place the CS5330A /31A into Master Mode. SERIAL DATA OUTPUT SDA TA A INL LEF T ANA LOG INPUT SER IAL DATA CLOCK SC LK VA+ ANALOG POWER LEFT/RIGH T CLOCK LRCK AGND ANALOG GROUND MAS TER C LOCK MC LK A INR R IGH T ANA LOG INPUT CS5 330A/C S5331A DS1 38F2 13

PARA M E TER D E FINITI O NS Resolution - The total num ber of possible output codes is equal to 2N , where N = the number of bits in the output w ord for each channel. Dyn amic Ran ge - The ratio of the full scale rms value of the signal to the rms sum of all other spectral com ponents over the specified bandw idth. Dyn am ic range is a signal-to-noise measurem ent over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion compo nents are below the noise level and do not effect the me asurement. This measurem ent technique has been accepted by the Aud io Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion+Noise (THD+N) - The ratio of the rms value of the signal to the rms sum of all other spectral compo nents over the specified band w idth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Total Harm onic Distortion - The ratio of the rms sum of all harmonics up to 20 kHz to the rms value of the signal. Interchannel Phase Deviation - The phase difference betwe en the left and right channel sam pling tim es. Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with the input under test A C grounded and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain M ismatch - The gain difference between left and right channels. Units in decibels. Gain Error - The deviation of the measured full scale amplitude from the ideal full scale amplitude value. Gain Drift - The change in gain value with temperature. U nits in ppm/°C. ideal. Units in LSB s. CS5 330A/C S5331A

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1) " Area Efficient D ecimation Filter for an 18-B it Delta- Sigma ADC" by K. Lin and J.J. Paulos . Pa- per presented at the 98th Convention of the Audio Engineering Society, Febuary 1995. and S.T. Dupuie. Paper presented at the 97th Convention of the Audio Engineering Society, Novem- ber 1994. 3) " An 18-B it Dual-C hannel Oversampling Delta-Sigma A/D C onverter, with 19-Bit Mono Applica- tion Exam ple" by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 4) " The Effects of Sampling C lock Jitter on Nyquist Sampling Analog-to-Digital C onverters, and on O versam pling De lta Sigm a ADC ’s" by Steven Harris. Paper presented at the 87th C onvention of the Au dio Engineering Society, October 1989. 5) "A Stereo 16-bit Delta-Sigma A/D Co nverter for Digital Audio" by D.R. W elland, B .P. De l Sig- C onvention of the Audio Engineering Society, N ovembe r 1988. PA CK A G E DESCRIPT IONS No te: The EIAJ Package is not a standard JEDEC package size. F G J I H B A MILLIMETERS INCHES MIN MAX MA XMINDIM H I J A B TY P1.27 0.050 TYP D 0 0.0100 0.25 E 0.070 0.0741.77 1.88 0.006 0.0100.15 0.25 8080 0.0300.0190.48 0.76 0.3190.302 0.203 0.2105.15 5.35 7.67 8.1 5.18 5.4 0.204 0.213D C 8-Pin SOIC E F 0.33 0.51 0.020 G C 0.013 CS5 330A/C S5331A DS1 38F2 15

• Notes • CS5 330A/C S5331A

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• Demonstrates recommended layout and grounding arrangements
• C S8402A Ge nerates AES/EBU , S/PD IF, & EIAJ-340 Comp atible Digital Audio
• Buffered Serial Output Interface
• Digital and Analog Patch Areas
• On-board or externally supplied system timing General Description The CDB 5330A/31A evaluation board is an excellent me ans for quickly evaluating the CS5330A/31A 18-bit, stereo A/D converter. Evaluation requires a digital signal processor, a low distortion a nalog signal source and a pow er supply. Analog inputs are pro- vided via RCA connectors for both channels. Also included is a CS84 02A digital audio interface transmitter which generates AES /EBU, S/PDIF, and EIAJ-340 comp atible audio data. The digital audio data is available via RCA phono, and optical connectors. The evaluation board may also be configured to accept external timing signals for operation in a user applica- tion during system developm ent. ORDERING INFORMA TION: CDB53 30A, CDB5331A Evaluation Board for CS5330A / CS5331A CDB5330A CDB5331A Analog Filter Digital Audio Output C S8402A D igital Audio Interface CS5330A/31A I/O forC locks and D ata Cirrus Logic, Inc. Crystal Semiconductor Product Division P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 http://www.crystal.com OC T ’97 DS 138DB2 17Copyright  Cirrus Logic, Inc. 1997 (All Rights Reserved)

CD B 5330A /31A System Overview The CDB 5330A/31A evaluation board is an ex- cellent mea ns of quickly evaluating the CS 5330A/31A. The CS 8402A digital audio in- terface transmitter provides an easy interface to digital audio signal processors, including the ma- jority of digital audio test equipm ent. The evaluation board has been designed to accept an analog input, and provide a digital output that is either optical or coax. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system developm ent. The CDB 5330A/31A schem atic has been parti- tioned into 5 schematics show n in Figures 2 through 6. Each partitioned schema tic is repre- sented in the system diagram shown in Figure 1. No tice that the the system diagram also includes the interconnections betw een the partitioned schem atics. CS 5330A/31A Ana log to Digital C onverter A d escription of the C S5330A/31A is included in the CS5 330A /31A data sheet. CS 8402A Digital Audio Interface Figure 4 shows the C S8402A circuitry which implemen ts AES /EBU, S/PDIF and EIAJ CP- 340 digital audio interface standards. T he CS 8402A circuit is hardware configured for con- sumer mo de. SW2 provides 8 DIP switches to select various mo des and bits for the CS8402A, Tables 4-5. See the CS8401A/CS8402 A data sheet for detailed information on the operation of the C S8402A and the digital audio standards. The operation of the CS8402A and a discussion of the digital audio interface are included in the 1994 C rystal Semiconductor Audio D ata Book. C S8402A D ata Format The CS8 402A data format can be set with jump- ers M0, M1, and M2. Th ese formats are shown in the C S8402A datasheet found in the 1994 Crystal Semiconductor Audio Data Book. The format selected must be com patible with the cor- responding data forma t of the CS53 30A /31A shown in Figures 2 and 3 of the CS5330A /31A datasheet. The default settings for M 0-M 2 on the evaluation board are given in Tables 2 and 3. The compa tible data formats for the CS8 402A and C S5330A/31A are: C S8402A format 1;C S5330A C S8402A format 4;C S5331A An alog input buffer The recommen ded input filter required for the C S5330A/31A has been combined with a unity gain input buffer (see Figure 2). The analog in- put filter uses a Mo torola M C 33202 single supply, dual op-amp. Pow er Supply Circuitry Power is supplied to the evaluation board by tw o binding posts (GND, +5V), Figure 6. The +5V input supplies power to the +5 Volt digital cir- cuitry (VD +), and the +5V a nalog circuitry (VA+). The analog supply is derived from the +5V binding post through a ferrite bead. Input/Output for C locks and Data The evaluation board has been designed to allow the interface to external systems via the 10-pin C LO C K I/O header, HD R 2. This header allows the evaluation board to accept externally gener- ated clocks. The schem atic for the clock/data I/O is shown in Figure 5. The 74H C 243 transceiver functions as an I/O buffer w here the M A S- TER/SL A VE j umper de termin es if the transceiver operates as a transm itter or receiver. CD B 5330A / CDB5331A

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The transceiver operates as a transmitter with the MASTE R /SLAV E jumper in the MASTER posi- tion. L R C K , SD A TA , and S C L K from the CS5330 A /31A wil l be available on H D R 2. HDR 22 must be in the 0 position and HDR 23 must be in the 1 position for MCLK to be an output and to avoid bus contention on MCLK. The transceiver operates as a receiver with the M A ST E R/SL AVE jump er in the SL AV E posi- tion. LR C K and SCLK on HD R 2 become inputs. H ow ever, the recomme nded mo de of operation is to generate MCLK on the evaluation board with HDR 23 in the 0 position and HDR 22 in the 1 position. These default settings allow M C LK to be an output, with LR CK a nd SCLK as inputs. MCLK is alw ays an output from the evaluation board. Groun ding and Power Supply Decoupling The C S5330A/31A requires careful attention to pow er supply and grounding arrangemen ts to op- timize p erform ance. Figure 2 show s the recomm end ed p ow er arrangem ents. T he CS53 30A /31A is positioned over the analog ground plane, near the digital/analog ground plane split, to minimize the distance that the clocks travel. The series resistors are present on the clock lines to reduce the effects of transient currents when driving a capacitive load in master mo de, and reduce clock overshoot when apply- ing external clocks to the CS5330A/31A in slave mo de. This layout technique is used to minim ize digital noise and to insure proper power supply match- ing/sequencing. Th e decoupling capacitors are located as close to the CS 5330A/31A as possi- ble. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yield large reductions in radiated noise ef- fects. CONNEC TOR INPU T/OU TPUT SIGNAL PRESENT +5V input (VD+) for CS8402A and digital section (VA+) for CS5 330A/31A and Analog input filter op-amp GND input ground connection from pow er supply AINL input left channel analog input AINR input right channel analog input MC LK, SCLK, LRCK, SDATA input/output I/O for master, serial, left/right clocks, and serial DATA Digital O utput output digital audio interface output via coax Optical Output output digital audio interface output via optical T able 1. System Connections CD B 5330A / CDB5331A DS1 38DB2 19

JUMPER PURPOSE POSITION FUNCTION SE LECTED HDR1 CS 5330A/31A SCLK Selection for CS8402A *5330A CS 5330A Selected 5331A CS 5331A Selected HDR10 Ma ster/Slave Mode Selection *High MAS TER M ode SLAVE ModeLow HDR9 Selects source of system clocks *High MAS TER M ode (5330A Clocks) Low SLAVE Mod e (External Clocks) HDR22 HDR23 Clock I/O *0 See Input/Output for Clocks and Data section of text HDR6 Selects 256× or 512× MCLK for CS8402A *256

512 See CS8402A data sheet for details

HDR5 (M2) CS 8402A m ode select *Low See CS8402A data sheet for details HDR4 (M1) *Low HDR 3 (M0) *High * D efault setting from factory Ta ble 2. CDB5330A Jum per Selectable O ptions JUMPER PURPOSE POSITION FUNCTION SE LECTED HDR1 CS 5330A/31A SCLK Selection for CS8402A 5330A CS 5330A Selected *5331A CS 5331A Selected HDR10 Ma ster/Slave Mode Selection *High MAS TER M ode SLAVE ModeLow HDR9 Selects source of system clocks *High MAS TER M ode (5331A Clocks) Low SLAVE Mod e (External Clocks) HDR22 HDR23 Clock I/O *0 See Input/Output for Clocks and Data section of text HDR6 Selects 256× or 512× MCLK for CS8402A *256 HDR5 (M2) CS 8402A m ode select *High See CS8402A data sheet for details HDR4 (M1) *Low HDR3 (M0) *Low * D efault setting from factory Ta ble 3. CDB5331A Jum per Selectable O ptions CD B 5330A / CDB5331A

20 DS 138DB2

3 PR O=0 Consumer Mode C0=0

2 C3 C3,C4,C5 - Emphasis (1 of 3 bits)

5 C2 C 2 - Co py/Copyright

6 C15 C 15 - Generation Status

0 - Definition is based on category code. Table 4. CS8402A Switch D efinitions - Consum er M ode

3 PR O =0 Professional Mode C0 =1(default)

1 CRE Local Sample Address Counter & Reliability Flags

4 C1 C 1 - Audio

Figure 1. System Block Diagram and Signal Flow

22 DS 138DB2

Figure 2. C S5330A /31A and Connections

Figure 3. MCLK Genera tion and Power Down

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Figure 4. CS8402A D igital A udio Transm itter Connections Schott Corp. Transform er Part 121960-602 available through Schott Corp., Wa yzata, M N .

Figure 5. I/O Interface for Clocks and D ata Figure 6. Powe r Supply

26 DS 138DB2

Figure 7. CDB5330A/31A C om ponent Side Silkscreen

Figure 8. CDB5330A/31A C om ponent Side (top)

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Figure 9. CDB5330A /31A Solder Side (bottom)