CS5326

CS5326 CIRRUS | Alldatasheet

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Semiconductor Corporation 53 16 & 18-Bit, Stereo A/D Converters for Digital Audio Features General Description The CS5326, CS5327, CS5328 & CS5329 are complete @ Complete CMOS Stereo A/D System | analog-to-digital converters for stereo digital audio sys- Delta-Sigma A/D Converters tems. They perform sampling, _analog-to-digital Rigital Anti-Alias Filtering conversion and anti-aliasing filtering, generating 16 or S/H Circuitry and Voltage Reference | 18bit values for both left and right inputs in serial form. . . The output word rate can be up to 50 kHz per channel. ® Adjustable System Sampling Rates a a 30 kHz to 50 kHz The ADCs use delta-sigma modulation with 64X over- sampling, followed by digital filtering and decimation, © Low Noise and Distortion which removes the need for an external anti-alias filter. 3 dB dynamic range, a The CS5926 & CS5327 are 16-bit ADCs, achieving yy 2 range, - 95 dB dynamic range. The CS5328 & CS5329 are 18-bit 100 3B dynamic range, 19-Bit Mono | apcs with 97 dB dynamic range in stereo mode and 0.0015% THD 100 dB dynamic range in mono mode. @ Internal 64X Oversampling The CS5326 & CS5328 have digital filters which are F - Ae cies compatible with CD requirements. The CS5327 & @ Linear Phase Digital Anti-Alias Filtering | cs5329 have filters which guarantee no aliasing. The 0.001dB Passband Ripple filters have linear phase, 0.001 dB passband ripple, and 86dB Stopband Rejection >86 dB stopband rejection. @ Low Power Dissipation: 450 mW The ADC's are housed in a 0.6" wide 28-pin plastic DIP. Power-Down Mode for Portable Applications ORDERING INFORMATION: — Page 3-23 ee CLKIN APD _ACAL ACLKA —DCLKA SCLK UR -- 23. .ve v7. top y20 15. | 14 pe —— a “46 VREF *"-—)_Voltage Reference ] . Serial Output Interface > SDATA 2 ~ AINE SED LIX : [— : >>| UP Filter -— ZEROL a Were Digits Begenation SiH Filter 7 —— Comparator} - — 4 DAC } TsT1 27. —_ be TST2 AINA SAO frre PS Digital BeSnation a ZEROR Ex La Abe FS Filter 3} tsT3 SH Y oe - 8 Nc

1 Comparator ee | re |

AND > LY pac | ena, ee aaaHe” asd : SRAM | S445 425 B24 ayo [107 hie dio” VA+ VA- VL+ LGND DCAL DPD = VD1+ VD2+ DGND iii i Crystal Semiconductor Corporation MAR '92 P.O. Box 17847, Austin, TX 78760 DS35F1 (512) 445-7222 FAX: (512) 445-7581 35

naw saw CS5326, CS5327, CS5328, CS5329 ST ANALOG CHARACTERISTICS (ta = 25°C; VA+, VL+,VD1+,VD2+ = 5V; VA- = -5V; Full-Scale In- put Sinewave, 4kHz; CLKIN = 6.144MHz; SCLK = 3.072 MHz; Source Impedance = 509 with 10 nF to AGND; Measurement Bandwidth is 10 Hz to 20 kHz; Digital inputs: Logic 1 = VD+, Logic 0 = DGND; unless otherwise specified.) Specification Parameter* Symbol min typ) max Units Resolution 85926, CS5327 16 Bits $5328, CS5329 18 Bits Dynamic Performance | Dynamic Range 685326, CS5327 92.7 95.7 oB 85328, C$5329 947 97.4 3B (Note 1) Mono CS5328, CS5329 100.1 3B Signal-to- 685326, C$5327 907 © 92.7 a8 | (Noise + Distortion) 85928, CS5329 | S/(N+D) 925 94.5 a8 | (Note 1) Mono c8328, $5329 | 7 a8 [Total Harmonic Distortion | 1 Vin= + FS | THD 0.003 0.0015 % Vin = -20 dB 0.001 % Interchannel Isolation (dc to 20 kHz) 100106 Er) de Accuracy Interchannel Gain Mismatch 0.01 0.05 4B Gain Error | sd +1 +5 % Bipolar Offset Error (€S5326, CS5327 +5 +15 | LSB (16-bit) (After Calibration) 85328, C$5329 +20 +60 | LSB (18-bit) Analog Input Input Voltage Range (4 Full Scale) VIN Volts Power Supplies Power Supply Current (VA+) + (VL#) TA+ 25 35 mA with APD,DPD low VA- IA 25 35 mA (Normal Operation) (VD1+) + (VD2+) ID+ 40 55 mA Power Supply Current (V+) + (VL+) I+ 10 15 uA with APD,DPD high VA ; o& 10 15 uA (Power-Down Mode) (vD14) + (VD24) 1D+ 5 7 mA Power Consumption (APD, DPD Low) PON 450 625 mw (APD, DPD High) PDS 25 35 mw Power Supply Rejection Ratio (dc to 26 kHz) pSRR dB | (26 kHz to 3.046 MHz) 8 Notes: 1. Mono means connecting AINL & AINR together and adding together the output words from each channel. * Refer to Parameter Definitions at the end of this data sheet. Specifications are subject to change without notice.

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manawa ne CS5326, CS5327, CS5328, CS5329 ey DIGITAL FILTER CHARACTERISTICS (Ta = 25° C; VAs, VL+ ,VD1+,VD2+= 5V + 5%; VA- = -5V 4 5%; CLKIN=6.144MHz) ! Parameter | ‘Symbol Min Typ | Max Units ] Passband (3 dB) CSS5326,CS5328 “oO 235 kHz | (-3dB) CS5327, CS5329 0 21.6 kHz (-0.001 dB) CS5326, CS5328 oO 21.8 kHz (0.001 dB) 88327, CS5329 0 20.0 kHz Passband Ripple | 0.001 4B | Stopband ‘CS5326, CS5328 26 3046 kHz —_685827,685329 24 3052 kHz ‘Stopband Attenuation (Note 2) 86 3B Group Delay ~ j tod A274/CLKIN | - s f Group Delay Variation vs. Frequency | Alga 0.0 “us Notes: 2. The analog modulator samples the input at 3.072MHz for a CLKIN of 6.144MHz. There is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for 1 x 3.072MHz +21.8kHz for the CS5326 & CS5328, of n x 3.072MHz +20.0kHz for the CS5327 & CS5329 , where n = 0,1,2,3...). DIGITAL CHARACTERISTICS (Ta = 25 °C; VAs, VL+ ,VD1+,VD2+= 5V + 5%; VA- = -5V + 5%) Parameter ‘Symbol Min Units [High-Level Input Vollage (CLIN) | MIM os) 10 jt Low-Level Input Voltage (CLKIN) ee ee _- 1.0 Vv | High-Level Input Voltage (except CLKIN) | VIH_—— | 70%VD+ : _I = v | Low-Level Input Voltage (except CLKIN) | Vit | ~_| S08 NPe |v High-Level Output Voltage at lo = -20uA VOH _ 44 - | _ | Vv | Low-Level Output Voltage at lo = 20uA Vou : : \\ O41 ve Input Leakage Current lin 5 1.0 : uA RECOMMENDED OPERATING CONDITIONS (AGND, LGND, DGND = OV; all voltages with respect to ground) _ ; DC Power Supplies: Positive Digital VD1+,V02+ 476 5.0 5.25 v Positive Logic vis 475 5.0 VAt | v Positive Analog VAs 475 5.0 5.25 v Negative Analog vA. -478 -50 5.25 v CLKIN Frequency fox sa | : 64 MHz SCLK Frequency f tok 2 | : 1 Hz UR Frequency tla fouq 128 : Fou 128 He | Notes: 3. The ADCs accept input voltages up to the analog supplies (VA+, VA-). They will produce a positive full-scale output for inputs above 3.68 V and negative full-scale output for inputs below -3.68 V. These values are subject to the gain error tolerance specification. DS35F1 37

faeusecna: PETS CS5326, CS5327, CS5328, CS5329 SS SWITCHING CHARACTERISTICS (Ta = 25°C; VA+, VL+, VD1+ , VD2+ = 5V + 5%; VA- = -5V 4 5%; Inputs: Logic 0 = OV, Logic 1 = VD+; Ci = 20 pF) Parameter ‘Symbol Min Typ Max | Units CLKIN Period 1 telkw 155 - 260 | ons | CLKIN High tetkh [50 | : : bad CLKIN Rising to ACLKA edge (Note 4) tetka ee 100 ACLKA Falling to LR Edge (Note 4) tacir [oof 140 CLKIN Rising to L/R Edge (Note 4) ACLKA to CLKIN phase correct telr 170 ACLKA to CLKIN phase unknown) 30 [SenK Pee wiath Low [tea é ee SCLK Pulee Width High Veoh Ce [ne SCLK Period Usctkw 155 [| - | [ ons | SCLK Rising to SDATA Valid [tas : : ns UF edge to MSB Valid __ Mirdss - : s SCLK Rising to LR edge ____tsetkir 40 : ns DPD, APD pulse width thd 150 : ns | CLKIN Falling to APD Falling tapdclk -30 [ - | ns Notes: 4, It is recommended that L/R be generated by dividing ACLKA by 64. If CLKIN is used to generate L/R, a longer CLKIN to L/R delay may be tolerated if the phase of ACLKA is determined through the use of the APD pin. When high, the APD pin resets the divide-by-two circuit that generates ACLKA from CLKIN (that is, ACLKA is reset to "0"). APD should be brought low on a falling edge of CLKIN. This falling edge should be chosen such that LR edges nominally occur at ACLKA falling edges. ABSOLUTE MAXIMUM RATINGS (aan, LGNO, DGND = OV, all voltages with respect to ground.) _Parameter Symbol! Min Max | Units DC Power Supplies: Positive Analog VA+ 0.3 +6.0 Tv Negative Analog VA- +03 -6.0 hoy Positive Logic VL+ 03 (VA+) +03 v Positive Digital V01+,VD2+ -0.3 +6.0 jv Input Current, Any Pin Except Supplies tn | | to | mw ‘Analog Input Voltage (AIN and ZERO pins) Vina (VA+ )+ 0.3 v Digital Input Voltage Vino 0.3 (vD+) +03 v Ambient Temperature (power applied) th -55 +125 *c | Storage Temperature 65 +150 “c WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 3-8 DS35F1

anima en $5326, CS5327, CS5328, CS5329 ened “scan tsoikd souk a I \\fN hte Nsw UR | opines ad pte SDATA {sa \\ wees { wse2 } Serial Data Timing toh otk — 7 aml cuKN j LA LEAS ee A i ee | Channel Selection Timing Using LR Derived From CLKIN/128 _ _ P\\ fy on, LL ap tee — DCLKA a h - po Sect " XK Channel Selection Timing Using LAR Derived from ACLKA/64 - ‘ea + APD, DPD j \\ Power Down Timing mm" rm i lanl — I tepdetk APD \\ _ ACLKA \\ ACLKA Phase Determination using APD DS35F1 3-9

ideal conversion performance independent of in- the power-down mode. 21! nc sta 3 +5V logic supply. Figure 1. Typical Connection Diagram

Figure 2. Data Output Timing sheet. the MSB, which is clocked out by the L/R edge. SYSTEM DESIGN WITH THE CS5326/7/8/9 _ edge for internal housekeeping purposes. All timing and control inputs to the ADC can be Aue 0 interference effects. 32 kHz, 44,1 kHz and 48 kHz, requiring master right data words being read at different times. 6.144 MHz, respectively. sent simultaneously sampled inputs.

remo na S5326, CS5327, CS5328, CS5329 SS be shorter than the smaller delay shown in the tor in parallel with a 0.1 F ceramic capacitor at- Switching Characteristics table (see Note 4.). tached to this pin eliminates the effects of high frequency noise. Note the negative value of Analog Connections VREF when using polarized capacitors. No load The analog inputs are presented to the modula- —_usTent may be taken from the VREF output pin. tors via the AINR and AINL pins. The analog . input signal range is determined by the internal The analog input level used as zero during the voltage reference value, which is typically -3.68 _ ffset calibration period (described later) is input volts. The input signal range therefore is typically 0" the ZEROL and ZEROR pins. Typically, these + 3.68 volts. pins are directly attached to AGND. For the ulti- mate in offset nulling, networks can be attached The ADC samples the analog inputs at ' ZEROR and ZEROL whose impedances match 3.072 MHz for a 6.144 MHz CLKIN. For the ‘he impedances present on AINL and AINR. CS5326 & CS5328 the digital filter rejects all bop noise between 26 kHz and (3.072 MHz26 kHz), PowerDown and Offset Calibration For the CS5327 & CS5329 the digital filter re- The ADC has a power-down mode wherein typi- jects all noise between 24 kHz and cal consumption drops to 20 mW. In addition, (3.072 MHz-24 kHz). However, the filter will not exiting the power-down state initiates the offset reject frequencies right around 3.072 MHz. Most calibration procedure. This can be important for audio signals do not have significant energy at digital audio applications since any initial offset 3.072 MHz. Nevertheless, a 51 Q resistor in se- __ manifests itself as an audible power-on click. ries with the analog input, and a 10 nF NPO or COG capacitor to ground will attenuate any noise © APD and DPD are the analog and digital power- energy at 3.072 MHz, in addition to providing the down pins. When high, they place the analog and optimum source impedance for the modulators. digital sections in the power-down mode. The use of capacitors which have a large voltage Bringing these pins low takes the part out of coefficient (such as general purpose ceramics) power-down mode. DPD going low initiates a should be avoided since these can degrade signal _ calibration cycle, whereas APD going low sets linearity. If active circuitry precedes the ADC, it the phase of the ACLKA signal. If not using the is recommended that the above RC filter is power down feature and if not using APD to set placed between the active circuitry and the AINR the phase of ACLKA, APD should be tied to and AINL pins. ground. When using the power down feature, DPD and APD may be tied together if the capaci- The on-chip voltage reference output is brought tor on VREF is not greater than 10 pF, as stated out to the VREF pin. A 10 pF electrolytic capaci-__in the "Power-Up Considerations" section. f— Cal Perios —* — — Filter Delay Time (4096 x UR clocks) | | (-100 LR periods) | 05888 @ asieiey | (-2ms @ 48 kHz) Po | \\ toy Nom: . 4] | al Operation ocr {oo Figure 3, Initial Calibration Cycle Timing

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mise nae CS5326, CS5327, CS5328, CS5329 a During the offset calibration cycle, the digital potentially large values of data in these registers section of the part measures and stores the value with the correct values. of the calibration input of each channel in regis- ters. The calibration input value is subtracted The modulators settle very quickly (a matter of from all future outputs. The calibration input may microseconds) after the analog section is powered be obtained from either the analog input pins on, either through the application of power, or by (AINL and AINR) or the zero pins (ZEROL and __ exiting the power-down mode. The voltage refer- ZEROR) depending on the state of the ACAL ence, however, can take a much longer time to pin. With ACAL low, the analog input pin volt- reach a final value due to the presence of large ages are measured, and with ACAL high, the zero external capacitance on the VREF pin; allow ap- pin voltages are measured. proximately 5 ms/F. The calibration period is long enough to allow the reference to settle for As shown in Figure 3, the DCAL output is high capacitor values of up to 10 UF. If a larger ca- during calibration, which takes 4096 L/R clock _pacitor is used, additional time between APD cycles. If DCAL is connected to the ACAL input, _going low and DPD going low should be allowed the calibration routine will measure the voltage for VREF settling before a calibration cycle is in- on ZEROR and ZEROL. These should be con- tiated, nected directly to ground or through a network matched to that present on the analog input pins. Grounding and Power Supply Decoupling Internal offsets of each channel will thus be : measured and subsequently subtracted. AS with any high resolution converter, the ADC requires careful attention to power supply and Alternatively, ACAL may be permanently con- _ 8'unding arrangements if its potential perform- nected low and DCAL utilized to ground the Nee is to be realized. Figure 1 shows powering user's front end. In this case, the calibration rou- ‘the part from single +5 volt supplies. Analog tine will measure and store not only the internal found and digital ground should be connected offsets but also any offsets present on the front together near to where the supplies are brought end. onto the printed circuit board. Decoupling capaci- tors should be as near to the ADC as possible, During calibration, the digital output of both With the low value ceramic capacitor being the channels is forced to a 2’s complement zero. Sub- nearest. The VREF decoupling capacitors, par- traction of the calibration input from conversions _ ticularly the 0.1 UF, must be positioned to after calibration substantially reduces any minimize the electrical path from VREF to Pin | power-on click that might otherwise be experi- | AGND and to minimize the path between VREF enced. A short delay of approximately 100 output _—_and the capacitors. words will occur following calibration for the digital filter to begin accurately tracking audio The printed circuit board layout should have band signals. The transition is simply the natural Separate analog and digital regions and ground filter response and is, of course, graceful. planes, with the ADC straddling the boundary. An evaluation board is available which demon- Power-up Considerations strates the optimum layout and power supply wae oe arrangements, as well as allowing fast evaluation Upon initial application of power to the supply f wpe . of the ADC. pins, the data in the calibration registers will be indeterminate. A calibration cycle should always To minimize digital noise, connect the ADC digi- be initiated after application of power to replace tal outputs only to CMOS inputs. DsaFT SSS BS

must be taken to ensure that the ACLKA phases ADC. are synchronized if simultaneous sampling is de- . able, the parts may be synchronized to within ‘he Dynamic Range value of 94.63 dB. several nanoseconds by using the circuit shown . APD signal is used to reset the internal divide. !!2 4B. Figure 4. Connections for Synchronization of Multiple CS5326/7/8/9 ADC’s.

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put signal of | kHz at -10 dB. This is very ating the noise in its transition band. Figure 5. CS5326 FFT Plot with -10 dB, 1 kHz Input Figure 6. CS5326 FFT Plot with -10 dB, 9 kHz Input Figure 7. CS5326 FFT Plot with -80 dB, 1 kHz Input Figure 8. CSS326 FFT Plot with -80 dB, 9 kHz Input

20 SieD) 24 78 dB = wt |

20 B yl —g—

Figure 9. CS5327 FFT Plot with -10 dB, 1 kHz Input Figure 10. CS$326, CS5327 Signal to Noise+Distortion

Figure 11. CS5328 FFT Plot with -10 dB, 1kHz Input —_—_—Figure 12. CS$329 FFT Plot with -10 dB, 1 kHz Input Figure 13, CS5328 in Mono Mode FFT Plot with Figure 14. CS5328 Signal to Noise+Distortion Ratio vs. measured data from a CS5326 shows both the provement over Figure 11. input levels. tortion versus Input Level for the 18-bit CS5328. Notice the improvement in values over Figure 10. A Differential Non-Linearity test is also shown.

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mwasawa naw €S5326, CS5327, C5328, C5329 el PIN DESCRIPTIONS ANALOG GROUND AGND (!' 8 5 VREF VOLTAGE REFERENCE OUTPUT LEFT CHANNEL ANALOG INPUT — AINL qe a AINR = RIGHT CHANNEL ANALOG INPUT LEFT CHANNEL ZERO INPUT ZEROL [3 26] ZEROR RIGHT CHANNEL ZERO INPUT POSITIVE ANALOG POWER VA+ q ‘ 2 VL+ ANALOG SECTION LOGIC POWER NEGATIVE ANALOG POWER VA- Cs 2 J LGND ANALOG SECTION LOGIC GROUND ~ ANALOG POWER DOWN INPUT APD (|¢ 23 1 CLKIN MASTER CLOCK INPUT ANALOG CALIBRATE INPUT ACAL (7 22 0 ACLKA ANALOG SECTION CLOCK OUTPUT NO CONNECT NC qe a NC NO CONNECT DIGITAL CALIBRATE OUTPUT DCAL Cis 20 1) DCLKA DIGITAL SECTION CLOCK INPUT DIGITAL POWER DOWN INPUT DPD (10 1 DGND DIGITAL GROUND TEST TST1 Cc 8] VD2+ DIGITAL SECTION POSITIVE POWER TEST TST2 Gz v bh VD1+ DIGITAL SECTION POSITIVE POWER TEST TST3 (3 16 [1 SDATA SERIAL DATA OUTPUT LEFT/RIGHT SELECT INPUT UR Oo. _ 1s SCLK SERIAL DATA CLOCK INPUT Power Supply Connections VA+ - Positive Analog Power, PIN 4. Positive analog supply. Nominally +5 volts. VL+ - Positive Logic Power, PIN 25. Positive logic supply for the analog section. Nominally +5 volts. VA- - Negative Analog Power, PIN 5. Negative analog supply. Nominally -5 volts. AGND - Analog Ground, PIN 1. Analog ground reference. LGND - Logic Ground, PIN 24 Ground for the logic portions of the analog section. VD1+, VD2+ - Positive Digital Power, PINS 17, 18. Positive supply for the digital section. Nominally +5 volts. DGND - Digital Ground, PIN 19. Digital ground for the digital section. Analog Inputs AINL, AINR - Left and Right Channel Analog Inputs, PINS 2, 27 Analog input connections for the left and right input channels. Nominally £3.68 volts full scale. ey DS35F1 319

awa new CS5326, CS5327, CS5328, CS5329 Cl ZEROL, ZEROR - Zero Level Inputs for Left and Right Channels, PINS 3, 26. Analog zero level inputs for the left and right channels. The levels present on these pins can be used as zero during the offset calibration cycle. Normally connected to AGND, optionally through networks matched to the analog input networks... Analog Outputs VREF - Voltage Reference Output, PIN 28. Nominally -3.68 volts. Normally connected to a 0.1F ceramic capacitor in parallel with a 10F or larger electrolytic capacitor. Note the negative output polarity. Digital Inputs CLKIN - Master Input Clock, PIN 23. This clock is internally divided by 2 to set the modulators sample rate. Sampling rates, output rates, and digital filter characteristics scale to CLKIN frequency. CLKIN frequency of 6.144 MHz corresponds to an output word rate of 48 kHz per channel. DCLKA - Digital Section Input Clock, PIN 20. This clock is used to clock the modulator output data into the digital section. Must be connected to ACLKA. SCLK - Serial Output Data Clock, PIN 15. Data bits are output on the rising edge of SCLK. UR - Left/Right Select, PIN 14. _ Select the left or right channel for output on SDATA. The rising edge of L/R starts the MSB of the left channel data. Thereafter, CLKIN, SCLK and L/R should run synchronously. L/R must be equal to CLKIN/128. Although the outputs of each channel are transmitted at different times, the two words in a LR cycle represent simultaneously sampled analog inputs. APD - Analog Power Down, PIN 6. Analog section power-down command. When high the analog circuitry is in power-down mode. It also causes the analog section to reset the clock output (ACLKA). APD is normally connected to DPD when using the power down feature. DPD - Digital Power Down, PIN 10 Digital section power-down command. Bringing DPD high puts the digital section into power-down mode. Upon retuming low, the ADC starts an offset calibration cycle. This takes 4096 L/R periods (85.33 ms with a 6.144 MHz clock). DCAL is high during the calibrate cycle and goes low upon completion. DPD is normally connected to APD. A calibration cycle should always be initiated after applying power to the supply pins. Ee 3-20 DS35F1

misao nana CS5326, CS5327, CS5328, CS5329 aren a ACAL - Analog Calibrate, PIN 7. Analog section calibration command. When high, causes the left and right channel modulator inputs to be internally connected to ZEROL and ZEROR inputs respectively. May be connected to DCAL. Digital Outputs ACLKA - Analog Section Output Clock, PIN 22. This clock is CLKIN/2. It is used by the digital section to clock in the modulator output data. ACLKA must be connected to DCLKA. The phase of ACLKA may be reset by using APD. SDATA - Serial Data Output, PIN 16. Data bits are presented MSB first, in 2's complement format. DCAL - Digital Calibrate Output, PIN 9. This pin rises immediately upon entering the power-down state (DPD brought high). It returns low 4096 L/R periods after leaving the power down state (DPD brought low), indicating the end of the offset calibration cycle (which = 85.33 ms with a 6.144 MHz CLKIN). May be connected to ACAL. (See Figure 3) Miscellaneous NC - No Connection, PINS 8,21. These two pins are bonded out to test outputs. They must not be connected to any external component or any length of PC trace. TST1, TST2, TST3 -Test Inputs, PINS 11, 12, 13. Allows access to the ADC test modes, which are reserved for factory use. Must be tied to DGND. ee DS35F1 321

manawa n nw CS5326, CS5327, CS5328, CS5329 SS PARAMETER DEFINITIONS Resolution - The total number of possible output codes is equal to 2N’ where N = the number of bits in the output word for each channel. Signal-to-Noise plus Distortion Ratio - The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Total Harmonic Distortion - The ratio of the rms sum of all harmonics up to 20 kHz to the rms value of the signal. Units in percent. Dynamic Range - Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured over the specified bandwidth, and with an input signal 60dB below full-scale. Units in decibels. Interchannel Phase Deviation - The difference between the left and right channel sampling times. Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with the input under test grounded and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels. Gain Error -The deviation of the gain value from the typical number given in the analog specifications table. Gain Drift - The change in gain value with temperature. Units in ppm/°C. (1/2 LSB below AGND). Units in LSBs. Differential Non-Linearity - The deviation of a code’s width from the ideal width. Units in LSB’s.

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maw len CS5326, CS5327, CS5328, CS5329 SS REFERENCES _ (All reprinted in the back of this data book) 1) "A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio" by D.R. Welland, B.P. Del Sig- Convention of the Audio Engineering Society, November 1988. 2)" The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC’s" by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 3)" An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Applica- tion Example" by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. Ordering Guide Model Resolution Filter Enters Stopband Temperature Package CS5326-KP 16-bits 26 kHz 0°C to 70 °C 28-pin Plastic DIP CS5327-KP 16-bits 24 kHz O°C to 70 °C 28-pin Plastic DIP CS5328-KP 18-bits 26 kHz O°C to 70 °C 28-pin Plastic DIP CS5329-KP 18-bits 24 kHz 0°C to 70 °C 28-pin Plastic DIP CDB5326 CS5326 Evaluation Board CDB5327 CS5327 Evaluation Board CDB5328 CS5328 Evaluation Board CDB5329 CS5329 Evaluation Board DS35F1 a ST?