CS5321-BL

CS5321_06 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

‰ CMOS A/D Converter Chipset ‰ Dynamic Range - 130 dB @ 25 Hz Bandwidth - 121 dB @ 411 Hz Bandwidth ‰ Delta-sigma Architecture - Fourth-order Modulator - Variable Oversampling: 64X to 4096X - Internal Track-and-hold Amplifier ‰ CS5321 Signal-to-distortion: 115 dB ‰ Clock-jitter-tolerant Architecture ‰ Input Voltage Range: +4.5 V ‰ Flexible Filter Chip - Hardware- or Software-selectable Options - Seven Selectable Filter Corners (-3 dB) Frequencies: 25, 51, 102, 205, 411, 824 and 1650 Hz ‰ Low Power Dissipation: <100 mW

Description

The CS5321/CS5322 chipset functions as a unique A/D converter intended for very high-resolution measurement of signals below 1600 Hz. It is specif- ically designed for applications that require both a high dynamic range and a low total harmonic distor- tion. The chipset performs sampling, A/D conversion, and anti-alias filtering. The CS5321 uses Delta-Sigma modulation to pro- duce highly accurate conversions. The ∆Σ modulator oversamples, virtually eliminating the need for external analog anti-alias filters. The CS5322 linear-phase FIR digital filter decimates the output to any one of seven selectable update peri- ods: 16, 8, 4, 2, 1, 0.5, and 0.25 milliseconds. Data is output from the digital filter in a 24-bit serial format.

ORDERING INFORMATION

See page 36. RSEL Vdd1 AINR AIN+ AIN- Vss1 AGND Analog Modulator MDATA MCLK MFLG RESET R/W H/S SCLK SID SOD ERROR DRDY ORCAL DECA DECB DECC CSCLKINSYNCVD+ TDATA PWDN USEOR DGND VD+ DGND CSEL Digital Filter CS5321 CS5322 Vss2 DGND Vdd2 LPWR OFST MDATA HBR MSYNC VREF+ VREF- NOV ‘06 DS454F3

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1. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ... 36

Figure 4. CS5322 Digital Filter Passband Ripple, f Figure 22. 1024 Point FFT Plot with -20 dB Input,

100 Hz Input, ten averages 22

Figure 23. 1024 Point FFT Plot with Full Scale Input, Figure 24. 1024 Point FFT Plot with Full Scale Input,

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1. CHARACTERISTICS AND SPECIFICATIONS CS5321 ANALOG CHARACTERISTICS (TA = (See Note 1); Vss1, Vss2 = -5 V; Vdd1, Vdd2 = +5 V; VD+ = 5 V; AGND = DGND = 0 V; HBR = Vdd LPWR = 0, MCLK = 1.024 MHz; Device connected as shown in Figure 20, CS5322 used for filtering; Logic 1 = VD+, Logic 0 = 0V; unless otherwise specified.) Notes: 1. CS5321-BL is guaranteed from -55 o to +85o C, CS5322-BL is guaranteed from -40o to +85o C. 2. f O = CS5322 output word rate. Refer to “CS5322 FILTER CHARACTERISTICS” on page 8 for details on the FIR Filter. 3. Characterized with full scale input signal of 50 Hz; fo = 500 Hz. 4. Characterized with input signals of 30 Hz and 50 Hz , each 6 dB down from full scale with fo = 1000 Hz. 5. Specification is for the parameter over the specif ied temperature range and is for the CS5321 device only (VREF = +4.5 V). It does not include the effects of external components; OFST = 0. 6. Drift specifications are guaranteed by design and/or characterization. 7. The offset after calibration specification ap plies to the effective offset voltage for a ±4.5 volt input to the CS5321 modulator, but is relative to the output digital codes from the CS5322 after ORCAL and USEOR have been made active. 8. The CS5322 offset calibration is performed digitally and includes ± full scale (±4.5 volts into CS5321). Calibration of offsets greater than ±5% of full scale will begin to subtract from the dynamic range. Parameter* CS5321 Symbol Min Typ Max Unit Dynamic Performance Dynamic Range (Note 2) HBR = 1 f O = 4000 Hz OFST = 1 f O = 2000 Hz fO = 1000 Hz fO = 500 Hz fO = 250 Hz fO = 125 Hz fO = 62.5 Hz HBR = 0 f O = 4000 Hz OFST = 1 f O = 2000 Hz fO = 1000 Hz fO = 500 Hz fO = 250 Hz fO = 125 Hz fO = 62.5 Hz DR 116 103 118 121 124 127 129 130 115 118 121 124 126 127 dB dB dB dB dB dB dB dB dB dB dB dB dB dB Signal-to-Distortion (Note 3) HBR = 1 HBR = 0 SDR 108 110 115 120 dB dB Intermodulation Distortion (Note 4) IMD - 110 - dB DC Accuracy Full Scale Error (Note 5) FSE - 1 - % Full Scale Drift (Note 5,6) TC FS -5- ppm/°C Offset (Note 5) V ZSE -1 0 - m V Offset after Calibration (Note 7) - ±100 - µV Offset Calibration Range (Note 8) - 100 - %F.S. Offset Drift (Note 5,6) TC ZSE -6 0- µ V / ° C

CS5321 ANALOG CHARACTERISTICS (Continued) Notes: 9. The upper bandwidth limit is dete rmined by the CS5322 digital filter. 10. This input voltage range is for the configuratio n shown in Figure 20, the System Connection Diagram, and applies to signal from dc to f3 Hz. Refer to CS5322 Filter Characteristics for the values of f3. 11. All outputs unloaded. All logic inputs forced to V dd or GND respectively. 12. LPWR = 0. 13. The CS5321 power dissipation can be reduced under the following conditions: a) LPWR=1; MCLK=512 kHz, HBR=1 b) LWPR=1; MCLK=1.024 MHz, HBR=0 14. Characterized with a 100 mVp-p sine wave applied separately to each supply. * Refer to Parameter Definitions (immediately following pin descriptions at the end of this data sheet). Specifications are subject to change without notice. Parameter* CS5321 Symbol Min Typ Max Unit Input Characteristics Input Signal Frequencies (Note 9) BW DC - 1600 Hz Input Voltage Range (Note 10) V IN -4.5 - +4.5 V Input Overrange Voltage (Note 10) I OVR --5 % F . S . Power Supplies DC Power Supply Currents (Note 11) LPWR = 0 Positive Supplies Negative Supplies LPWR = 1 Positive Supplies Negative Supplies 5.5 5.5 3.0 3.0 7.5 7.5 4.5 4.5 mA mA mA mA Power Consumption (Note 11) Normal Operating Mode (Note12) Lower Power Mode (Note 13) P DN PDL mW mW Power Down P D -2- m W Power Supply Rejection (dc to 128 kHz) (Note 14) PSR - 60 - dB

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Notes: 15. Guaranteed by design, characterization, or test.

1. If MCLK is removed, the modulat or will enter the power down mode.
2. Excludes MCLK input. MCLK should be driven with a si gnal having rise and fall times of 25 ns or faster.

Figure 1. Rise and Fall Times Figure 2. CS5321 Interface Timing, HBR=1

CS5321 DIGITAL CHARACTERISTICS (TA = (See Note 1); Vdd1 = Vdd2 = 5.0 V ± 5%; GND =

0 V; measurements performed under static conditions)

Notes: 18. Device is intended to be driven with CMOS logic levels. 19. Device is intended to be interfaced to CMOS logic. Resistive loads are not recommended on these pins. CS5321 RECOMMENDED OPERATION CONDITIONS (Voltages with respect to GND =

0 V, See Note 20)

Notes: 20. The maximum voltage differential between the Po sitive Supply of the CS5321 and the Positive Digital Supply of the CS5322 must be less than 0.25 V. CS5321 ABSOLUTE MAXIMUM RATINGS * (Voltages with respect to GND = 0 V) Notes: 21. Transient currents of up to 100 mA will not cause SCR latch up. *WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Min Typ Max Units High-Level Input Drive Voltage (Note 18) V IH (Vdd)-0.6 - - V Low-Level Input Drive Voltage (Note 18) V IL -- 1 . 0 V High-Level Output Voltage IOUT = -40 µA (Note 19) V OH (Vdd)-0.3 - - V Low-Level Output Voltage IOUT = +40 µA (Note 19) V OL -- 0 . 3 V Input Leakage Current I LKG -- ± 1 0 µ A Digital Input Capacitance C IN -9 - p F Digital Output Capacitance C OUT -9 - p F Parameter Symbol Min Typ Max Units DC Supply: Positive Negative Vdd1,Vdd2 Vss1,Vss2 4.75 -4.75 5.0 -5.0 5.25 -5.25 V V Ambient Operating Temperature -BL T A -55 - +85 °C Parameter Symbol Min Max Units DC Supply: Positive Negative Vdd1,Vdd2 Vss1,Vss2 -0.3 +0.3 6.0 -6.0 V V Input Current, Any Pin Except Supplies (Note 21) I in -± 1 0 m A Output Current I out -2 5 m A Total Power (all supplies and outputs) P t -1 W Digital Input Voltage V IND -0.3 (V dd)+0.3 V Storage Temperature T stg -65 150 °C

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Notes: 22. G SB = -130 dB for all Output Word Rates. Figure 3. CS5322 Filter Response Figure 4. CS5322 Digital Filter Passband Ripple Figure 5. CS5322 Digital Filter Passband Ripple Figure 6. CS5322 Digital Filter Passband Ripple

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CS5322 POWER SUPPLY (TA = (See Note 1); VD+ = 5 V; CLKIN = 1.024 MHz) CS5322 SWITCHING CHARACTERISTICS (TA = (See Note 1); VD+ = 5 V ± 5%; DGND = 0 V; Inputs: Logic 0 = 0 V Logic 1 = VD+; CL = 50 pF (Note 23) 23. Guaranteed by design, characterization and/or test. Parameter CS5322-BL Min Typ Max Unit Power Supply Current: ID+ (Note 11) - 2.2 4 mA Power Dissipation: (Note 11) PWDN Low PWDN High 0.6 2.5 mW mW Parameter Symbol Min Typ Max Units CLKIN Frequency f c 0.512 1.024 1.2 MHz CLKIN Duty Cycle 40 - 60 % Rise Times: Any Digital Input Any Digital Output trise - 100 100 ns ns Fall Times: Any Digital Input Any Digital Output tfall - 100 100 ns ns Serial Port Read Timing DRDY to Data Valid t ddv - - 25 ns RSEL Setup Time before Data Valid t rss 50 - - ns Read Setup before CS Active t rsc 20 - - ns Read Active to Data Valid t rdv - - 50 ns SCLK rising to New SOD bit t rdd - - 50 ns SCLK Pulse Width High t rph 30 - - ns SCLK Pulse Width Low t rpl 30 - - ns SCLK Period t rsp 100 - - ns SCLK falling to DRDY falling t rst - - 50 ns CS High to Output Hi-Z t rch - - 20 ns Read Hold Time after CS Inactive t rhc 20 - - ns Read Select Setup to SCLK falling t rds 20 - - ns Serial Port Write Timing Write Setup Before CS Active t wsc 20 - - ns SCLK Pulse Width Low t wpl 30 - - ns SCLK Pulse Width High t wph 30 - - ns SCLK Period t wsp 100 - - ns Write Setup Time to First SCLK falling t wws 20 - - ns Data Setup Time to First SCLK falling t wds 20 - - ns Write Select Hold Time after SCLK falling t wwh 20 - - ns Write Hold Time after CS Inactive t whc 20 - - ns Data Hold Time after SCLK falling t wdh 20 - - ns

Figure 13. CS5322 Serial Port Timing

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Figure 14. TDATA Setup/Hold Timing

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Notes: 24. If MCLK is removed, the modul ator will enter the power down mode.

1. Excludes MCLK input. MCLK should be driven with a signal having rise and fall times of 25 ns or faster.
2. Only the rising edge of MSYNC relative to MCLK is used to synchronize the device. MSYNC can return

low at any time as long as it remains high for at least one MCLK cycle. Figure 17. CS5321/CS5322 Interface Timing

CS5322 DIGITAL CHARACTERISTICS (TA = (See Note 1); VD+ = 5.0 V ± 5%; GND = 0 V; measurements performed under static conditions) Notes: 27. Device is intended to be driven with CMOS logic levels. 28. Device is intended to be interfaced to CMOS logic. Resistive loads are not recommended on these pins. CS5322 RECOMMENDED OPERATION CONDITIONS (Voltages with respect to GND = 0V ) Notes: 29. The maximum voltage differential between the Po sitive Supply of the CS5321 and the Positive Digital Supply of the CS5322 must be less than 0.25 V. CS5322 ABSOLUTE MAXIMUM RATINGS * (Voltages with respect to GND = 0 V) Notes: 30. Transient currents of up to 100 mA will not cause SCR latch up. *WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Min Typ Max Units High-Level Input Drive Voltage V IH (VD+)-0.3 - - V Low-Level Input Drive Voltage V IL -- 0 . 3 V High-Level Input Threshold (Note 27) (VD+)-1.0 - - V Low-Level Input Threshold (Note 27) - - 1.0 V High-Level Output Voltage IOUT = -40 µA (Note 28) V OH (VD+)-0.6 - - V Low-Level Output Voltage IOUT = +1.6 mA (Note 28) V OL -- 0 . 4 V Input Leakage Current All pins except MFLG, SOD I LKG -- ± 1 0 µ A Three-State Leakage Current I OZ -- ± 1 0 µ A Digital Input Capacitance C IN -9 - p F Digital Output Capacitance C OUT -9 - p F Parameter Symbol Min Typ Max Units DC Supply: (Note 29) Positive Negative VD+ VD- 4.75 -4.75 5.0 -5.0 5.25 -5.25 V V Ambient Operating Temperature -BL T A -40 - +85 °C Parameter Symbol Min Typ Max Units DC Supply: (Note 29) Positive Negative VD+ VD- -0.3 0.3 (VD+)+0.3 -6.0 V V Input Current, Any Pin Except Supplies (Note 30) I in -- ± 1 0 m A Digital Input Voltage VIND -0.3 - (VD+)+0.3 V Storage Temperature T stg -65 - 150 °C

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converter embedded in a negative feedback loop. anti-alias filter for the CS5321 modulator output. Figure 18. CS5321 Block Diagram

Figure 19. CS5322 Block Diagram

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2.1 Analog Input

The CS5321 modulator uses a switched capacitor architecture for its signal and voltage reference in- puts. The signal input uses three pins; AINR, AIN+, and AIN-. The AIN- pin acts as the return pin for the AINR and AIN+ pins . The AINR pin is a switched capacitor "rough charge" input for the AIN+ pin. The input impedance for the rough charge pin (AINR) is 1/fC where f is two times the modulator sampling clock rate and C is the internal sampling capacitor (about 40 pF). Using a 1.024 MHz master clock (HBR = 1) yields an input im- pedance of about 1/(512 kHz)X(40 pF) or about 50 kΩ. Internal to the chip the rough charge input pre- charges the sampling capa citor used on the AIN+ input, therefore the eff ective input impedance on the AIN+ pin is orders of magnitude above the im- pedance seen on the AINR pin. The analog input structure inside the VREF+ pin is very similar to the AINR pin but includes addition- al circuitry whose operating current can change over temperature and from device to device. There- fore, if gain accuracy is important, the VREF+ pin should be driven from a low source impedance. The current demand of the VREF+ pin will produce a voltage drop of approximately 45 mV across the 200 Ω source resistor of Figure 20 and Figure 21 Option A with MCLK = 1.024 MHz, HBR = 1, and temperature = 25°C. When the CS5321 modulator is operated with a 4.5 V reference it will accept a 9 V p-p input signal, but modulator loop stability can be adversely affected by high frequency out-of-band signals. Therefore, input signals must be band-limited by an input fil- ter. The -3 dB corner of the input filter must be equal to the modulator sampling clock divided by 64. The modulator sampling clock is MCLK/4 when HBR = 1 or MCLK /8 when HBR = 0. With MCLK = 1.024 MHz, HBR = 1, the modulator sampling clock is 256 kHz which requires an input filter with a -3 dB corner of 4 kHz. The bandlimit- ing may be accomplished in an amplifier stage ahead of the CS5321 modulator or with the RC in- put filter at the AIN+ and AINR input pins. The RC filter at the AIN+ and AINR pins is recommended to reduce the "charge kick" that the driving ampli- fier sees as the switched capacitor sampling is per- formed. Figure 20 illustrates the CS5321 and CS5322 sys- tem connections. The i nput components on AINR and AIN+ should be iden tical values for optimum performance. In choosi ng the components the ca- pacitor should be a minimum of 0.1 µF (C0G di- electric ceramic prefer red). For minimum board space, the RC components on the AINR input can be removed, but this will force the driving amplifi- er to source the full dynamic charging current of the AINR input. This can increase distortion in the driving amplifier and re duce system performance. In choosing the RC filter components, increasing C and minimizing R is preferred. Increasing C reduc- es the instantaneous voltage change on the pin, but may require paralleling capacitors to maintain smaller size (the recommended 0.1 µF C0G ceram- ic capacitor is larger than other similar-valued ca- pacitors with different di electrics). Larger resistor values will increase the voltage drop across the re- sistor as the recharging current charges the switched capacitor input.

2.2 The OFST Pin

The CS5321 modulator can produce "idle tones" which occur in the passband when the input signal is steady state dc signal within about ±50 mV of bipolar zero. In the CS5321 these tones are about 135 dB down from full scale. The user can force these idle tones "out-of-band" by adding 100 mV of dc offset to the signal at the AIN input. Alternately, if the user circuitry has a low offset voltage such that the input signal is within ±50 mV of bipolar zero when no AC signal is present, the OFST pin on the CS5321 can be activated. When OFST = 1, +100 mV of input referred offset will be

2.3 Input Range and Overrange

AIN- pin must remain at GND potential. plied between the VREF+ and VREF- input pins. for voltage reference requirements. tor to recover from this error condition.

0.1 F 68 µF+

14 GND7

Figure 20. System Connection Diagram

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2.4 Voltage Reference

2.5 Clock Source

with a CMOS-compatible clock on the MCLK pin. Figure 21. 4.5 Voltage Reference with two filter options

modifies the sampling clock rate of the modulator. for the same output word rate from the CS5322.

2.6 Low Power Mode

than 128 kHz will greatly degrade performance.

2.7 Digital Interface and Data Format

determined by the modulator over sampling clock. still be converted properly. Table 1. Output Coding for the CS5321 and

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2.8 Performance

point FFTs were averaged to produce the plots. kHz. Dynamic range is 122 dB.

100 Hz signal source is interpreted by the signal

processing software to be increased noise. allow more time for amplifier settling. Figure 22. 1024 Point FFT Plot with -20 dB Input, 100 Hz

100 Hz Input, HBR = 1, ten averages

100 Hz Input, HBR = 0, ten averages

2.9 Power Supply Considerations

The system connection di agram, Figure 20, illus- trates the recommended power supply arrange- ments. There are two pos itive power supply pins for the CS5321 and two negative power supply pins. Power must be supplie d to all four pins and each of the supply pins should be de-coupled with a 0.1 µF capacitor to the nearest ground pin on the device. When used with the CS5322 digital filter, the max- imum voltage differential between the positive sup- plies of the CS5321 and the positive digital supply of the CS5322 must be less than 0.25 V. Operation beyond this constraint may result in loss of analog performance in the CS5321/22 system perfor- mance. Many seismic or portable data acquisition systems are battery powered and utilize dc-dc converters to generate the necessary supply voltages for the sys- tem. To minimize the effects of power supply inter- ference, it is desirabl e to operate the dc-dc converter at a frequency which is rejected by the digital filter, or locked to the modulator sample clock rate. A synchronous dc-dc converter, whose operating frequency is derived fr om the 1.024 MHz clock used to drive the CS5322, will minimize the poten- tial for "beat frequenc ies" appearing in the pass- band between dc and the co rner frequency of the digital filter.

2.10 Power Supply Rejection Ratio

The PSRR of the CS5321 is frequency dependent. The CS5322 digital filter attenuation will aid in re- jection of power supply noise for frequencies above the corner frequency setting of the CS5322. For frequencies between dc and the corner frequen- cy of the digital filter, the PSRR is nearly constant at about 60 dB.

2.11 RESET Operation

The RESET pin puts the CS5322 into a known ini- tialized state. RESET is recognized on the next CLKIN rising edge after the RESET pin has been brought high (RESET=1). All internal logic is ini- tialized when RESET is active. Normal device operation begins on the second CLKIN rising edge afte r RESET is brought low. The CS5322 will remain in an idle state, not per- forming convolutions, unt il triggered by a SYNC event. A RESET operation clears memory, sets the data output register, offset register, and status flags to all zeroes, and sets the confi guration register to the state of the corresponding hardware pins (PWDN, ORCAL, DECC, DECB, DECA, USEOR, and CSEL). The reset state is entered on power on, in- dependent of the RESET pin. If RESET is low, the first CLKIN will exit the power on reset state.

2.12 Power-down Operation

The PWDN pin puts the CS5322 into the power- down state. The power-down state is entered on the first CLKIN rising edge after the PWDN pin is brought high. While in the power-down state, the MCLK and MSYNC signals to the CS5321 analog modulator are held low. The loss of the MCLK sig- nal to the modulator causes it to power-down. The signals on the MDATA a nd MFLG pins are ig- nored. The serial interface of the CS5322 remains active allowing read and write operations. Informa- tion in the data register, offset register, configura- tion register, and convolution data memory are maintained during power-down. The internal con- troller requires 64 clock cy cles after PWDN is as- serted before CLKIN stops. The CS5322 exits the power-down state on the first CLKIN rising edge after the PWDN pin is brought low. The CS5322 then enters an idle state until trig- gered by a SYNC event.

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To avoid possible high curr ent states while in the power down state, the following conditions apply: 1) CLKIN must be active fo r at least 64 clock cy- cles after PWDN entry. 2) CSEL and TDATA must not both be asserted high.

2.13 SYNC Operation

The SYNC pin is used to start convolutions and synchronize the CS5322 and CS5321 to an external sampling source or timing reference. The SYNC event is recognized on the first CLKIN rising edge after the SYNC pin goe s high. SYNC may remain high indefinitely. Only the sequence of SYNC ris- ing followed by CLKIN rising generates a SYNC event. The SYNC event aligns the output sample and causes the filter to begi n convolutions. The first SYNC event causes an immediate DRDY provided DRDY is low. Subsequent data ready events will occur at a rate determined by the decimation rate inputs DECC, DECB, and DECA. Multiple SYNC events can be applied with no effect on operation if they are perfectly timed according to the decima- tion rate. Any SYNC event not in step with the dec- imation rate will cause a realignment and loss of data.

2.14 Serial Read Operation

Serial read is used to obtain status or conversion data. The CS , R/W, SCLK, RSEL, and SOD pins control the read operation. The serial read opera- tion is activated when CS goes low (CS=0) with the R/W pin high (R/W=1). The RSEL pin selects be- tween conversion data (data register) or status in- formation (status register). The selected serial bit stream is output on the SOD (Serial Output Data) pin. On read select, SCLK can either be high or low, the first bit appears on the SOD pin and should be latched on the falling edge of SCLK. After the first SCLK falling edge, each SCLK rising edge shifts out a new bit. Status r eads are 16 bits, and data reads are 24 bits. Both streams are supplied as MSB first, LSB last. In the event more SCLK pulses are supplied than necessary to clock out th e requested information, trailing zeroes will be output for data reads and trailing LSB’s for status reads. If the read operation is terminated before all the bits are read, the inter- nal bit pointer is reset to the MSB so that a re-read will give the same data as the first read, with one exception. The status error flags are cleared on read and will not be available on a re-read. The status error flags must be read before entering the power-down state. If an error has occurred be- fore entering powerdown a nd the status bit (ER- ROR) has not been read, the status bits (ERROR, OVERWRITE, MFLG, ACC1 and ACC2) may not be cleared on status reads. Upon exiting the power- down state and entering normal operation, the user may be flagged that an error is still present. The SOD pin floats when read operation is deacti- vated (R/W =1, CS =1). This enables the SID and SOD pins to be tied together to form a bi-direction- al serial data bus. There is an internal nominal 100 kΩ pull-up resistor on the SOD pin.

2.15 Serial Write Operation

Serial write is used to write data to the configura- tion register. The CS , R/W , SCLK and SID pins control the serial write operation. The serial write operation is activated when CS goes low (CS =0) with R/W pin low (R/W=0). Serial input data on the SID pin is sampled on the falling edge of SCLK. The input bits are stored in a temporary buffer until either the write operation is terminated or 8 bits have been received. The data is then parallel loaded into the configuration register. If fewer than 8 bits are input before the write termi- nation, the other bits may be indeterminate.

2.16 Offset Calibration Operation

ibration, the offset register value is not used. ples will have the offset subtracted from the output. will start on the first SYNC signal.

2 ORCAL Self-offset calibration

3 USEOR Use Offset Register

4 CSEL Channel Select

5 Reserved Factory use only

6 DECC Filter BW selection

7 DECB Filter BW selection

Table 2. Configuration Data Bits

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2.17 Status Bits

bits of the Status Register. has a nominal 100 kΩ internal pull-up resistor. served, and the new data word is lost. status register read or RESET.

2 OVERWRITE Error O verwrite Error

3 MFLG Error Modulator Flag Error

4 ACC1 Error Accumulator 1 Error

5 ACC2 Error Accumulator Error

6 DRDY Data Ready

8 ORCALD Offset calibration done

9 PWDN Standby mode

10 ORCAL Self-offset Calibration

11 USEOR Use Offset Register

12 CSEL Channel Select

13 Reserved Factory use only

14 DECC Bandwidth Selection Status

15 DECB Bandwidth Selection Status

16 DECA Bandwidth Selection Status

Table 3. Status Data (from the SOD Pin)

The DRDY bit reflects the state of the DRDY pin. loaded at the normal end of conversion time. during that sample and is otherwise low. CA) provide configuration readback for the user. rate of the filter and are defined in Table 4. Table 4. Bandwidth Selection: Truth Table

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2.18 Board Layout Considerations

All of the 0.1 µF filter capacitors on the power sup- plies, AIN+, and AINR, should be placed very close to the chip and connect to the nearest ground pin on the device. The capacitors between VREF+ and VREF- should be located as close to the chip as possible. The 0.l µF capacitors on the AIN+ and AINR pins should be placed with their leads on the same axis, not side-by-side. If these capacitors are placed side-by-side their electric fields can interact and cause increased distortion. The chip should be surrounded with a ground plan e. Trace fill should be used around the analog input components.

1. CS5321 PIN DESCRIPTIONS Power Supplies Vdd1 – Positive Power One, PIN 2 Positive supply voltage. Nominally +5 V olts. Vdd2 – Positive Power Two, PIN 22 Positive supply voltage. Nominally +5 V olts. Vss1 – Negative Power One, PIN 3 Negative supply voltage. Nominally -5 V olts. Vss2 – Negative Power Two, PIN 21 Negative supply voltage. Nominally -5 V olts. GND1 through GND11 – Ground, PINS 1, 4, 7, 11, 12, 13, 14, 15, 16, 19, 23. Ground reference. Analog Inputs AIN+ - Positive An alog Input, PIN 9 Nominally ± 4.5V AIN- - Negative An alog Input, PIN 8 This pin is tied to ground.

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AINR - Analog I nput Rough, PIN 10 Allows a non-linear current to bypass the main ex ternal anti-aliasing filt er which if allowed to happen, would cause harmonic distortion in the modulator. Please refer to the System Connection Diagram and the Analog Input and V oltage Reference section of the data sheet for recommended use of this pin. VREF+ – Positive Voltage Reference Input, PIN 5 This pin accepts an external +4.5 V voltage reference. VREF- – Negative Voltage Reference Input, PIN 6 This pin is tied to ground. Digital Inputs MCLK – Clock Input, PIN 20 A CMOS-compatible clock input to this pi n (nominally 1.024 MHz) provides the necessary clock for operation of the modulator and data output portions of the A/D converter. MCLK is normally supplied by the CS5322 MSYNC – Modulator Sync, PIN 25 A transition from a low to high level on this input will re-initialize the CS5321. MSYNC resets a divider-counter to align the MDATA output bit stream from the CS5321 with the timing inside the CS5322. OFST - Offset, PIN 28 When high, adds approxima tely 100 mV of input referred of fset to guarantee that any zero input limit cycles are out of band if pr esent. When low, zero offset is added. LPWR - Low Powe r Mode, PIN 27 The CS5321 power dissipation ca n be reduced from its nomin al value of 55 mW to 30 mW under the following conditions: LPWR=1; MCLK = 512 kHz, HBR=1; or LPWR=1; MCLK = 1.024 MHz, HBR=0 HBR – High Bit Rate, Pin 26 Selects either 1 ⁄4 MCLK (HBR=1) or 1 ⁄8MCLK (HBR=0) for the modulator sampling clock. Digital Outputs MDATA – Modulator Data Output, PIN 18 Data will be presented in a one-bit serial da ta stream at a bit rate of 256 kHz (HBR=1) or 128 kHz (HBR=0) with MCLK operating at 1.024 MHz. MDATA – Modulator Data Output, PIN 17 Inverse of the MDATA output. MFLG – Modulator Flag, PIN 24 A transition from a low to high level signals that the CS5321 m odulator is unstable due to an overrange on the analog input

1. CS5322 PIN DESCRIPTIONS Power Supplies VD+ – Positive Digital Power, Pin 8, 21 Positive digital supply voltage. Nominally +5 volts. DGND – Digital Ground, Pin 9, 20 Digital ground reference. Digital Outputs MCLK – Modulator Cl ock Output, Pin 7 A CMOS-compatible clock output (nominally 1.024 MHz) that provi des the necessary clock for operation of the modulator. MSYNC – Modulator Sync, Pin 5 The transition from a low to high level on this output will re-initialize the CS5321. ERROR - Error Flag, Pin 23 This signal is the output of an open pull-up NOR ga te with a nominal 100 k Ω pull-up resistor to which the error status data (OVERWRITE error, MFLG error, ACC1 error and ACC2 error) are inputs. When low, it notifies the host proc essor that an error condition exists. The ERROR signal can be wire OR’d together with other filters’ outputs. Th e value of the internal pull-up resistor is 100 k Ω. DRDY - Data Ready, Pin 22 When high, data is ready to be shifted out of the serial port data register. TOP VIEW 2532 7242 6 281 12 14 16 1813 15 17 CHIP SELECT CS FRAME SYNC SYNC R/ W READ/WRITE CLOCK INPUT CLKIN RSEL REGISTER SELECT RESET RESET SCLK SERIAL CLOCK MODULATOR SYNC MSYNC SID SERIAL INPUT DATA MODULATOR FLAG MFLG SOD SERIAL OUTPUT DATA MODULATOR CLOCK MCLK CS5322 ERROR ERROR FLAG POSITIVE DIGITAL POWER VD+ DRDY DATA READY DIGITAL GROUND DGND VD+ POSITIVE DIGITAL POWER MODULATOR DATA MDATA DGND DIGITAL GROUND TEST DATA TDATA ORCAL OFFSET CALIBRATION CHANNEL SELECT CSEL DECA DECIMATION RATE CONTROL HARDWARE/SOFTWARE MODE H/S DECIMATION RATE CONTROL POWER DOWN PWDN DECB DECC DECIMATION RATE CONTROL USEOR USE OFFSET REGISTER

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SOD - Serial Output Data, Pin 24 The output coding is 2’s compleme nt with the data bits presen ted MSB first, LSB last. Data changes on the rising edge of SC LK. An internal nominal 100 k Ω pull-up resistor is included. Digital Inputs MDATA – Modulator Data, Pin 10 Data will be presented in a one-bit serial da ta stream at a bit rate of 256 kHz; (CLKIN = 1.024 MHz). TDATA - Test Data, Pin 11 Input for user test data. MFLG – Modulator Flag, Pin 6 A transition from a low to high level signals that the CS5321 m odulator is unstable due to an over-range on the analog input. A Status Bit will be set in the digital filt er indicating an error condition. An internal nominal 100 k Ω pull-down resistor included on the input pin. RESET - Filter Reset, Pin 4 Performs a hard reset on the chip, all registers and accumula tors are cleared. All signals to the device are locked out except CLKI N. The error flags in the Status Register are set to zero and the Data Register and Offset Re gister are set to zero. The confi guration register is set to the values of the corresponding input pins. SYNC must be applied to resume convol utions after RESET deasserts. CLKIN - Clock Input, Pin 3 A CMOS-Compatible clock input to this pi n (nominally 1.024 MHz) provides the necessary clock for operation the modulator and filter. SYNC - Frame Sync, Pin 2 Conversion synchronization input. This signal sy nchronizes the start of the filter convolution. More than one SYNC signal can occur with no eff ect on filter perfor mance, providing the SYNC signals are perfectly timed at inte rvals equal to the output sample period. CSEL - Channel Select, Pin 12 When high, information on the TDATA pin is presen ted to the digital filter. A low causes data on the MDATA input to be presented to the digital filter. PWDN - Powerdown, Pin 14 Powers down the filter when ta ken high. Convolution cycles in th e digital filter and the MCLK signal are stopped. The registers ma intain their data and the se rial port remains active. SYNC must be applied to resume c onvolutions after PWDN deasserts. DECA - Decimation Rate Control, Pin 18 See Table 4. DECB - Decimation Rate Control, Pin 17 See Table 4.

DECC - Decimation Rate Control, Pin 16 See Table 4. H/S - Hardware/Software Mode Select, Pin 13 When high, the device pins cont rol device operation; when low, the value entered by a prior configuration write controls device operation. CS - Chip Select, Pin 1 When high, all signal acti vity on the SID, R/W and SCLK pins is ignored. The DRDY and ERROR signals indicate the status of the chip’s internal operation. R/W - Read/Write, Pin 28 Used in conjunction with CS such that when both signals are lo w, the filter inputs data from the SID pin on the falling edge of SCLK. If CS is low and R/W is high, the filter outputs data on the SOD pin on the risi ng edge of SCLK. R/W low floats the SOD pi n allowing SID and SOD to be tied together, forming a bidirectional serial data bus. SCLK - Serial Clock, Pin 26 Clock signal generated by host pr ocessor to either input data on the SID input pin, or output data on the SOD output pin. For write, data must be valid on the SID pin on the falling edge of SCLK. Data changes on the SOD pi n on the rising edge of SCLK. SID - Serial Da ta Input, Pin 25 Data bits are presented MSB first, LSB last. Data is latched on the falling edge of SCLK. RSEL - Register Select, Pin 27 Selects conversion data when hi gh, or status data when low. USEOR - Use Offset Register, Pin 15 Use offset register value to co rrect output words wh en high. Output words will not be offset corrected when low. ORCAL - Offset Regist er Calibrate, Pin 19 Initiates an offset calibration cycle when SY NC goes high after ORCAL has been toggled from low to high. The offset value is output on the 57th word following SYNC. Subsequent words will have their offset co rrection controlled by USEOR.

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1. PARAMETER DEFINITIONS Dynamic Range The ratio of the full-scale (rms) signal to the broadband (rms) noise signal. Broadband noise is measured with the input grounded within the bandwidth of 1 Hz to f 3 Hz (See “CS5322 FILTER CHARACTERISTICS” on page 8). Units in dB. Signal-to-Distortion The ratio of the full-scale (rms) signal to the rms sum of all harmonics up to f 3 Hz. Units in dB. Intermodulation Distortion The ratio of the rms sum of the two test frequencies (30 and 50 Hz) which are each 6 dB down from full-scale to the rms sum of all intermodul ation components within the bandwidth of dc to f3 Hz. Units in dB. Full Scale Error The ratio of the difference betw een the value of the voltage re ference and analog input voltage to the full scale span (two times the voltage re ference value). This ratio is calculated after the effects of offset and the external bias com ponents are removed and th e analog input voltage is adjusted. Measurement of this pa rameter uses the circuitry illust rated in the System Connection Diagram. Units in %. Full Scale Drift The change in the Full Scale value with temperature. Units in %/ °C. Offset The difference between the analog ground and the analog voltage necessary to yield an output code from the CS5321/22 of 00 0000(H). Measurement of this parameter uses the circuit configuration illustrated in the Syst em Connection Diagram. Units in mV . Offset Drift The change in the Offset value with temperat ure. Measurement of this parameter uses the circuit configuration illustrated in th e System Connection Diagram. Units in µV/°C.

1. PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.165 0.180 4.043 4.572 A1 0.090 0.120 2.205 3.048 B 0.013 0.021 0.319 0.533 D 0.485 0.495 11.883 12.573 D1 0.450 0.456 11.025 11.582 D2 0.390 0.430 9.555 10.922 E 0.485 0.495 11.883 12.573 E1 0.450 0.456 11.025 11.582 E2 0.390 0.430 9.555 10.922 e 0.040 0.060 0.980 1.524 JEDEC #: MS-018 28L PLCC PACKAGE DRAWING D E1 E D2/E2 B e A

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1. ORDERING INFORMATION 8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 9. REVISION HISTORY Model Temperature Package CS5321-BL -55 to +85 °C 28-pin PLCC CS5321-BLZ (Lead Free) CS5322-BL -40 to +85 °C CS5322-BLZ (Lead Free) Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5321-BL 225 °C 23 6 5 D a y s CS5321-BLZ (Lead Free) 260 °C CS5322-BL 225 °C CS5322-BLZ (Lead Free) 260 °C Revision Date Changes PP3 OCT 2003 Initial Release. F1 AUG 2005 Update ordering information. MSL data added. Change CS5321 TA spec to -40 to +85 degrees. F2 SEP 2005 Change CS5321 TA spec to -55 to +85 degrees. F3 NOV 2006 Corrected Ordering Information from 28-SSOP to 28-PLCC. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRI TICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SU CH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER'S RI SK AND CIRRUS DISCLAIMS AND MAKES NO WA RRANTY, EXPRESS, ST ATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.