CS5317

CS5317 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

lComplete Voiceband DSP Front-End - 16-Bit A/D Converter - Internal Track & Hold Amplifier - On-Chip Voltage Reference - Linear-Phase Digital Filter lOn-Chip PLL for Simplified Output Phase Locking in Modem Applications l84 dB Dynamic Range l80 dB Total Harmonic Distortion lOutput Word Rates up to 20 kHz lDSP-Compatible Serial Interface lLow Power Dissipation: 220 mW

Description

The CS5317 is an ideal analog front-end for voiceband signal processing applications such as high-perfor- mance modems, passive sonar, and voice recognition systems. It includes a 16-bit A/D converter with an inter- nal track & hold amplifier, a voltage reference, and a linear-phase digital filter. An on-chip phase-lock loop (PLL) circuit simplifies the CS5317's use in applications where the output word rate must be locked to an external sampling signal. The CS5317 uses delta-sigma modulation to achieve 16-bit output word rates up to 20 kHz. The delta-sigma technique utilizes oversampling followed by a digital fil- tering and decimation process. The combination of oversampling and digital filtering greatly eases antialias requirements. Thus, the CS5317 offers 84 dB dynamic range and 80 dB THD and signal bandwidths up to 10 kHz at a fraction of the cost of hybrid and discrete solutions. The CS5317's advanced CMOS construction provides low power consumption of 220 mW and the inherent re- liability of monolithic devices.

ORDERING INFORMATION

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ANALOG CHARACTERISTICS (TA = TMIN - TMAX ; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%; CLKIN = 4.9152 MHz in CLKOR mode; 1kHz Input Sinewave; with 1.2 kΩ , .01 µF antialiasing filter.) Parameter* Min Typ Max Units Specified Temperature Range 0 to 70 °C Resolution 16 - - Bits Dynamic Performance Dynamic Rnage (Note 1) 78 84 - dB Total Harmonic Distortion 72 80 - dB Signal to Intermodulation Distorition - 84 - dB dc Accuracy Differential Nonlinearity (Note2) - ±0.4 -L S B Positive Full-Scale Error - ±150 -m V Positive Full-Scale Drift - ±500 - µV/°C Bipolar Offset Error - ±10 -m V Bipolar Offset Drift - ±50 - µV/°C Filter Characteristics Absolute Group Delay (Note 3) 78.125 - - µs Passband Frequency (Note 4) - 5 - kHz Input Characteristics AC Input Impedance (1kHz) - 80 - kΩ Analog Input Full Scale Signal Level ±2.75 -- V Power Supplies Power Dissipation (Note5) - 220 300 mW Notes: 1. Measured over the full 0 to 9.6kHz band with a -20dB input and extrapolated to full-scale. Since this includes energy in the stopband above 5kHz, additional post-filtering at the CS5317’s output can typically achieve 88dB dynamic range by improving rejection above 5kHz. This can be increased to 90dB by bandlimiting the output to 2.5kHz. 2. No missing codes is guaranteed by design. 3. Group delay is constant with respect to input analog frequency; that is, the digital FIR filter has linear phase. Group delay is determined by the formula D grp = 384/CLKIN in CLKOR mode, or 192/CLKOUT in any mode. 4. The digital filter’s frequency response scales with the master clock. Its -3dB point is determined by f-3dB = CLKIN/977.3 in CLKOR mode, or CLKOUT/488.65 in any mode. 5. All outputs unloaded. All inputs CMOS levels. * Refer to the Parameter Definitions section after the Pin Description section. CS5317

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ANALOG CHARACTERISTICS (continued) Parameter Min Typ Max Units Power Supply Rejection VA+ (Note 6) VA- VD+ VD- dB dB dB dB Specified Temperature Range 0 to 70 °C Phase-Lock Loop Characteristics VCO Gain Constant, Ko (Note 7) -4 -10 -30 Mrad/Vs VCO Operating Frequency 1.28 - 5.12 MHz Phase Detector Gain Control, Kd -3 -8 -12 µA/rad Phase Detector Prop. Delay (Note 8) - 50 100 ns Notes: 6. With 300mV p-p, 1kHz ripple applied to each supply separately. 7. Over 1.28 MHz to 5.12 MHz VCO output range, where VCO frequency = 2 * CLKOUT. 8. Delay from an input edge to the phase detector to a response at the PHDT output pin. DIGITAL CHARACTERISTICS (TA = TMIN - TMAX ; VA+, VD+ = 5V±10%; VA-, VD- = -5V±10%) All measurements performed under static conditions. Parameter Symbol Min Typ Max Units High-Level Input Voltage V IH 2.0 - - V Low-Level Input Voltage V IL -- 0 . 8 V High-Level Output Voltage (Note 9) V OH (VD+)-1.0V - - V Low-Level Output Voltage IOUT = 1.6mA V OL -- 0 . 4 V Input Leakage Current I in -- 1 0 µA 3-State Leakage Current I OZ -- ±10 µA Digital Output Pin Capacitance C out -9- p F RECOMMENDED OPERATING CONDITIONS (DGND, AGND = 0V, see Note 10.) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 5.5 -5.5 5.5 -5.5 V V V V Master Clock Frequency f clk 0.01 - 5.12 MHz Note: 10. All voltages with respect to ground. Specifications are subject to change without notice. CS5317 DS27F4 3

SWITCHING CHARACTERISTICS (TA = TMIN -TMAX ; CL=50 pF; VD+ = 5V±10%; VD- = -5V±10%) Parameter Symbol Min Typ Max Units Master Clock Frequency: CLKIN CLKG1 Mode CLKG2 Mode CLKOR Mode fclkg1 fclkg2 fclkor 5.12 kHz kHz MHz Output Word Rate: DOUT f dout -- 2 0 k H z Rise Times: Any Digital Input Any Digital Output trisein triseout 1000 ns ns Fall Times: Any Digital Input Any Digital Output tfallin tfallout 1000 ns ns CLKIN Duty Cycle CLKG1 and CKLG2 Modes Pulse Width Low Pulse Width High CLKOR Mode Pulse Width Low Pulse Width High tpwl1 tpwh1 tpwl1 tpwh1 200 200 ns ns ns ns RST Pulse Width Low t pwr 400 - - ns Set Up Times: RST High to CLKIN High CLKIN High to RST High tsu1 tsu2 ns ns Propagation Delays: DOE Falling to Data Valid CLKIN Rising to DOUT Falling (Note 11) DOE Rising to Hi-Z Output CLKOUT Rising to DOUT Falling CLKOUT Rising to DOUT Rising CLKOUT Rising to Data Valid CLKIN Rising to CLKOUT Falling (Note 12) CLKIN Rising to CLKOUT Rising (Note 12) t phl1 tphl2 tplh1 tplh2 tplh3 tplh4 tplh5 tplh6 150 100 200 200 ns CLKOUT cycles ns ns ns ns ns Notes: 11. CLKIN only pertains to CLKG1 and CLKG2 modes. 12. Only valid in CLKOR mode. ABSOLUTE MAXIMUM RATINGS (DGND, AGND = 0V, all voltages with repect to groung) Parameter Symbol Min Max Units DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- -0.3 0.3 -0.3 0.3 (VA+) + 0.3 -6.0 6.0 -6.0 V V V V Input Current, Any Pin Except Supplies (Note 13) I in - ±10 mA Analog Input Voltage (AIN and VREF pins) V INA (VA-) - 0.3 (VA+) + 0.3 V Digital Input Voltage V IND -0.3 (VD+) + 0.3 V Ambient Operating Temperature T A -55 125 °C Storage Temperature T stg -65 150 °C Notes: 13. Transient currents up to 100mA will not cause SCR latch-up. WARNING:Operating this device at or beyond these extremes may result in permanent damage to the device. Normal operation of the part is not guaranteed at these extremes. CS5317

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2.0 V 0.8 V tfallintrisein 2.4 V 0.4 V triseout tfallout Rise and Fall Times DATA CLKOUT (Note 15) CLKIN DOUT DOE CLKIN tpwh1 tpwl1 CLKIN CLKOUT (Note 14) tplh5 tsu1tsu2 tpwr tplh5 tsu1 tsu2 tplh6 RST DOUT tplh1tplh2 tplh3 tphl2 tphl1 14 1015 (MSB) (Note 16) tplh4 Notes: 14. CLKIN only pertains to CLKG1 and CLKG2 modes. 15. If DOE is brought high during serial data transfer, CLKOUT, DOUT, and DATA will immediately 3-state and the rest of the serial data is lost. 16.RST must be held high except in the clock override (CLKOR) mode where it can be used to align the phases of all internal clocks. CLKIN Timing Serial Output Timing Reset Timing CS5317 DS27F4 5

The CS5317 functions as a complete data conver- sion subsystem for voiceband signal processing. The A/D converter, sample/hold, voltage refer- ence, and much of the antialiasing filtering are performed on-chip. The CS5317’s serial interface offers its 16-bit, 2’s complement output in a for- mat which easily interfaces with industry-standard micro’s and DSP’s. The CS5317 also includes a phase-locked loop that simplifies the converter’s application in sys- tems which require sampling to be locked to an external signal source. The CS5317 continuously samples its analog input at a rate set by an exter- nal clock source. On-chip digital filtering, an integral part of the delta-sigma ADC, processes the data and updates the 16-bit output register at up to 20 kHz. The CS5317 can be read at any rate up to 20 kHz. The CS5317 is a CS5316 with an on-chip sam- pling clock generator. As such, it replaces the CS5316 and should be considered for all new de- signs. In addition, a CS5316 look-alike mode is included, allowing a CS5317 to be dropped into a CS5316 socket. THEORY OF OPERATION The CS5317 utilizes the delta-sigma technique of executing low-cost, high-resolution A/D conver- sions. A delta-sigma A/D converter consists of two basic blocks: an analog modulator and a digi- tal filter. Conversion The analog modulator consists of a 1-bit A/D converter (that is, a comparator) embedded in an analog negative feedback loop with high open- loop gain. The modulator samples and converts the analog input at a rate well above the band- width of interest (2.5 MHz for the CS5317). The modulator’s 1-bit output conveys information in the form of duty cycle. The digital filter then processes the 1-bit signal and extracts a high resolution output at a much lower rate (that is, 16-bits at a 20 kHz word rate with a 5 kHz input bandwidth). An elementary example of a delta-sigma A/D converter is a conventional voltage-to-frequency converter and counter. The VFC’s 1-bit output conveys information in the form of frequency (or duty-cycle), which is then filtered (averaged) by the counter for higher resolution. In comparison, the CS5317 uses a more sophisticated multi-order modulator and more powerful FIR filtering to ex- tract higher word rates, much lower noise, and more useful system-level filtering. Filtering At the system level, the CS5317’s digital filter can be modeled exactly like an analog filter with a few minor differences. First, digital filtering re- sides behind the A/D conversion and can thus reject noise injected during the conversion proc- ess (i.e. power supply ripple, voltage reference noise, or noise in the ADC itself). Analog filtering cannot. Also, since digital filtering resides behind the A/D converter, noise riding unfiltered on a near- full-scale input could potentially saturate the ADC. In contrast, analog filtering removes the noise before it ever reaches the converter. To ad- dress this issue, the CS5317’s analog modulator and digital filter reserve headroom such that the device can process signals with 100mV "excur- sions" above full-scale and still output accurately converted and filtered data. Filtered input signals above full-scale still result in an output of all ones. An Application Note called "Delta Sigma Over- view" contains more details on delta-sigma conversion and digital filtering. CS5317

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various CS5317 operating modes. internally generates the requisite 5.12 MHz clock.

11 AINSignal

12 REFBUF

9 Clock

17 PHDT

Figure 1. System Connection Diagram with Example PLL Components

clock from a 10 kHz external sampling signal. sampling rate set by CLKIN, typically 10 kHz. is initiated by grounding the MODE pin.

5.12 MHz master clock to be driven directly into

ples updating its output register at fclkin/256. The CS5317 was designed for signal processing. system-level calibration capability. pears MSB-first in 2’s complement format. Table 1. Mode Comparisons

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the input signal at the input sample rate. by analog filtering before the signal is sampled. RC filter can be used as shown in Figure 2.

0 F 2F 3Fdc

Figure 3. CS5317 Low-Pass Filter Response will be encoded as distortion by the CS5317. pacitor such as COG-ceramic is recommended. Figure 2. Anti-alias Filter

thus will be discussed separately. Figure 3. In the process of filtering the digitized output word rate, which has aliasing implications. put tone at 28 kHz will be attenuated by 39.9 dB. crease the converter’s dynamic range to 88 dB. interface to a wide variety of micro’s and DSP’s. industry-standard processors. Figure 4. Data Output

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Data Output Characteristics & Coding Format As shown in Figure 4, the CS5317 outputs its 16- bit data word in a serial burst. The data appears at the DA TA pin on the rising edge of the same CLKOUT cycle in which DOUT falls. Data changes on the rising edge of CLKOUT, and can be latched on the falling edge. The CLKOUT rate is set by the CLKIN input (fclkin/2 in the CLKOR mode; fclkin*128 in the CLKG1 mode; and fclkin*256 in the CLKG2 mode). DOUT returns high after the last bit is transmitted. After trans- mitting the sixteen data bits, DA TA will remain high until DOUT falls again, initiating the next data output cycle. A 3-state capability is available for bus-oriented applications. The 3-state control input is termed Data Output Enable, DOE, and is asynchronous with respect to the rest of the CS5317. If DOE is taken high at any time, even during a data burst, the DA TA, DOUT and CLKOUT pins go to a high impedance state. Any data which would be output while DOE is high is lost. Power Supplies Since the A/D converter’s output is digitally fil- tered in the CS5317, the device is more forgiving and requires less attention than conventional 16- bit A/D converters to grounding and layout arrangements. Still, care must be taken at the de- sign and layout stages to apply the device properly. The CS5317 provides separate analog and digital power supply connections to isolate digital noise from its analog circuitry. Each sup- ply pin should be decoupled to its respective ground, AGND or DGND. Decoupling should be accomplished with 0.1 µF ceramic capacitors. If significant low frequency noise is present in the supplies, 10 µF tantalum capacitors are recom- mended in parallel with the 0.1 µF capacitors. The positive digital power supply of the CS5317 must never exceed the positive analog supply by more than a diode drop or the chip could be per- manently damaged. If the two supplies are de- rived from separate sources, care must be taken that the analog supply comes up first at power-up. Figure 1 shows a decoupling scheme which al- lows the CS5317 to be powered from a single set of ± 5V rails. The digital supplies are derived from the analog supplies through 10 Ω resistors to prevent the analog supply from dropping be- low the digital supply. PLL Characteristics A phase-locked loop is included on the CS5317 and is used to generate the requisite high fre- quency A/D sampling clock. A functional diagram of the PLL is shown in Figure 5. The PLL consists of a phase detector, a filter, a VCO (voltage-controlled oscillator), and a counter/di- vider. The phase detector inputs are CLKIN (θ and a sub-multiple of the VCO output signal (θ2). The inputs to the phase detector are positive-edge triggered and therefore the duty cycle of the CLKIN signal is not significant. With this type of phase detector, the lock range of the PLL is equal to the capture range and is independent of the low pass filter. The output of the phase detector is in- put to an external low pass filter. The filter characteristics are used to determine the transient response of the loop. The output voltage from the filter functions as the input control voltage to the VCO. The output of the VCO is then divided in frequency to provide an input to the phase detec- tor. The clock divider ratio is a function of the PLL mode which has been selected. Phase Detector Gain (Kd) A properly designed and operating phase-locked loop can be described using steady state linear analysis. Once in frequency lock, any phase dif- ference between the two inputs to the phase detector cause a current output from the detector during the phase error. While either the +50 µA or the -50 µA current source may be turned on, the average current flow is: CS5317 DS27F4 11

to the delta-sigma modulator sampling clock. mode the divider ratio (N) is 512. Figure 5. PLL Functional Diagram

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characteristic form in which the damping factor, ζ, and the natural frequency, ω n , are evident: = 2ζω ns + ω n 2 s2 + 2ζω ns + ω n 2 Both the natural frequency and the damping fac- tor are particularly important in determining the transient response of the phase-locked loop when subjected to a step input of phase or frequency. A family of curves are illustrated in Figure 6 that indicate the overshoot and stability of the loop as a function of the damping factor. Each response is plotted as a function of the normalized time, ω n t. For a given ζ and lock time, t, the ω n required can be determined. Alternatively, phase lock con- trol loop bandwidth may be a specified parameter. In some systems it may be desirable to reduce the -3dB bandwidth of the PLL control loop to re- duce the effects of jitter in the phase of the input clock. The 3 dB bandwidth of the PLL control loop is defined by the following equation: The equations used to describe the PLL and the 3 dB bandwidth are valid only if the frequency of CLKIN is approximately 20 times greater than the 3 dB corner frequency of the control loop. Filter Components Using the equations which describe the transfer function of the PLL system, the following exter- nal filter component equations can be determined: C = KoKd N ω n 2 R = 2ζω n N KoKd The gain factors (Ko, Kd) are specified in the Analog Characteristics table. In the event the sys- tem calls for very low bandwidth, hence a corresponding reduction in loop gain, the phase detector gain factor Kd can be reduced. A large series resistor (R1) can be inserted between the output of the detector and the filter. Then the 50 µA current sources will saturate to the supplies and yield the following gain factor: Kd ≈ −5V 2πR 1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 0123456789 1 0 0.1 1 10 -10 Figure 6a. θ2 Unit Step Response Figure 6b. Second Order PLL Frequency Response ω n t. θ2 normalized to θ1 ω/ω n 20 log(θ2/θ1) ζ = 0.5 ζ = 0.6 ζ = 0.7 ζ = 0.8 ζ = 0.9 ζ = 1.0 ζ = 1.5 ζ = 2.0 ζ = 3.0 ζ = 10.0 ζ= 10.0 ζ= 0.5 ζ = 0.5 ζ = 10 CS5317 DS27F4 13

In some applications additional filtering may be useful to eliminate any jitter associated with the discrete current pulses from the phase detector. In this case a capacitor whose value is no more than 0.1 C can be placed across the RC filter net- work (C2 in Figure 5). Filter Design Example The following is a step by step example of how to derive the loop filter components. The CS5317 A/D sampling clock is to be derived from a 9600 Hz clock source. The application requires the sig- nal passband of the CS5317 to be 4 kHz. The on-chip digital filter of the CS5317 has a 3 dB passband of CLKOUT/488.65 (see Note 4 in the data sheet specifications tables). The 4 kHz pass- band requirement dictates that the sample clock (CLKOUT) of the CS5317 be a minimum of 4000 X 488.65 = 1.954 MHz. This requires the VCO to run at 3.908 MHz. The 3.908 MHz rate is 407 times greater than the 9600 Hz PLL input clock. Therefore the CS5317 must be set up in mode CLKG2 with N = 512. If the CLKG1 mode were used (N = 256), too narrow of a signal band- width through the A/D would result. Once the operating mode has been determined from the system requirements, a value for the damping factor must be chosen. Figure 6 illus- trates the dynamic aspects of the system with a given damping factor. Damping factor is gener- ally chosen to be between 0.5 and 2.0. The choice of 0.5 will result in an overshoot of 30 % to a step response whereas the choice of 2.0 will result in an overshoot of less than 5 %. For example pur- poses, let us use a damping factor of 1.0. So, let us begin with the following variables : Ko = - 10 Mradians/volt.sec Kd = - 8 µA/radian N = 512 ζ = 1.0 To calculate values for the resistor R and capaci- tor C of the filter, we must first derive a value for ω n. Using the general rule that the sample clock should be at least 20 times higher frequency than the 3dB bandwidth of the PLL control loop: CLKIN ≥ 20 ω 3dB where CLKIN = 9600 Hz = 2π 9600 radians/sec. So: ω 3dB = 2π 9600/20 = 3016 radians/sec. Knowing ω 3dB and the damping factor of 1.0, we can calculate the natural frequency, ω n , of the control loop: ω n = 1215 1 ⁄ sec Once the natural frequency, ω n , is determined, values for R and C for the loop filter can be cal- culated: R = 2ζω nN/KoKd R = 2(1)(1215 1/s) 512/(-10Mrad/v.s.)(-8 µA/rad) R = 15552 v/A = 15.55 kΩ . Use R = 15 kΩ . C = KoKd/N ω n2 C = (-10 Mrad/v.s)(- 8 µA/rad)/512 (1215 1/s)2 The above example assumed typical values for Ko and Kd. Your application may require a worst case analysis which includes the minimum or maximum values. Table 2 shows some other ex- ample situations and R and C values. CS5317

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range of 0 to 9.6 kHz (fs/2). sults, and counting the occurrences of each code. part easily achieves no missing codes. Figure 9. CS5317 DNL Plot Figure 8. CS5317 Intermodulation Distortion Call Applications Engineering. Call Applications Engineering.

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PIN DESCRIPTIONS (Pin numbers refer to the 18-pin DIP package) 18 pin DIP Pinout 20 pin SOIC pinout Power Supplies VD+ - Positive Digital Power, PIN 2. Positive digital supply voltage. Nominally 5 volts. VD- - Negative Digital Power, PIN 10. Negative digital supply voltage. Nominally -5 volts. DGND - Digital Ground, PIN 4. Digital ground reference. V A+ - Positive Analog Power, PIN 1. Positive analog supply voltage. Nominally 5 volts. V A- - Negative Analog Power, PIN 14. Negative analog supply voltage. Nominally -5 volts. AGND - Analog Ground, PIN 15. Analog ground reference. PLL/Clock Generator CLKIN - Clock Input, PIN 9. Clock input for both clock generation modes and the clock override mode (see MODE). 109 POSITIVE ANALOG POWER VA+ VCOIN VCO INPUT POSITIVE DIGITAL POWER VD+ PHDT PHASE DETECT DATA OUTPUT ENABLE DOE RST RESET DIGITAL GROUND DGND AGND ANALOG GROUND SERIAL CLOCK OUTPUT CLKOUT VA- NEGATIVE ANALOG POWER SERIAL DATA OUTPUT DATA NC NO CONNECT CLOCKING MODE SELECT MODE REFBUF POSITIVE REFERENCE BUFFER DATA OUTPUT READY DOUT AIN ANALOG INPUT CLOCK INPUT CLKIN VD- NEGATIVE DIGITAL POWER POSITIVE ANALOG POWER VA+ VCOIN VCO INPUT POSITIVE DIGITAL POWER VD+ PHDT PHASE DETECT DATA OUTPUT ENABLE DOE RST RESET DIGITAL GROUND DGND AGND ANALOG GROUND NO CONNECT NC NC NO CONNECT SERIAL CLOCK OUTPUT CLKOUT NC NO CONNECT SERIAL DATA OUTPUT DATA VA- NEGATIVE ANALOG POWER CLOCKING MODE SELECT MODE REFBUF POSITIVE REFERENCE BUFFER DATA OUTPUT READY DOUT AIN ANALOG INPUT CLOCK INPUT CLKIN VD- NEGATIVE DIGITAL POWER CS5317 DS27F4 17

MODE - Mode Set, PIN 7. Determines the internal clocking mode utilized by the CS5317. Connect to +5V to select CLKG1 mode. Connect to DGND to select CLKG2 mode. Connect to -5V to select CLKOR mode. This pin becomes equivalent to FSYNC in the CSZ5316 compatible mode. VCOIN - VCO Input, PIN 18. This pin is typically connected to PHDT. A capacitor and resistor in series connected between V A+ and this pin sets the filter response of the on-chip phase locked loop. PHDT - Phase Detect, PIN 17. This pin is typically connected to VCOIN. A capacitor and resistor in series connected between V A+ and this pin sets the filter response of the on-chip phase locked loop. Inputs AIN - Analog Input, PIN 11. DOE - Data Output Enable, PIN 3. Three-state control for serial output interface. When low, DA TA, DOUT, and CLKOUT are active. When high, they are in a high impedance state. RST - Sample Clock Reset, PIN 16. Sets phase of CLKOUT. Functions only in the clock override mode, CLKOR. Used to synchronize the output samples of multiple CS5317’s. Must be kept high in CLKG1 or CLKG2 modes. Also, tying this pin low, with MODE not tied to - 5V , will place the CS5317 into CSZ5316 compatible mode. Outputs DOUT - Data Output Flag, PIN 8. The falling edge indicates the start of serial data output on the DA TA pin. The rising edge indicates the end of serial data output. DATA - Data Output, PIN 6. Serial data output pin. Converted data is clocked out on this pin by the rising edge of CLKOUT. Data is sent MSB first in two’s complement format. CLKOUT - Data Output Clock, PIN 5. Serial data output clock. Data is clocked out on the rising edge of this pin. The falling edge should be used to latch data. Since CLKOUT is a free running clock, DOUT can be used to indicate valid data. REFBUF - Positive Voltage Reference Noise Buffer, PIN 12. Used to attenuate noise on the internal positive voltage reference. Must be connected to the analog ground through a 0.1µF ceramic capacitor. CS5317

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Resolution - The number of different output codes possible. Expressed as N, where 2N is the number of available output codes. Dynamic Range - The ratio of the largest allowable input signal to the noise floor. Total Harmonic Distortion - The ratio of the rms sum of all harmonics to the rms value of the largest allowable input signal. Units in dB’s. Signal to Intermodulation Distortion - The ratio of the rms sum of two input signals to the rms sum of all discernible intermodulation and harmonic distortion products. Linearity Error - The deviation of a code from a straight line passing through the endpoints of the transfer function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 1/2 LSB below the first code transition and "full-scale" is a point 1/2 LSB beyond the code transition to all ones. The deviation is measured from the middle of each particular code. Units in %FS. Differential Nonlinearity - The deviation of a code’s width from the ideal width. Units in LSB’s. Positive Full Scale Error - The deviation of the last code transition from the ideal, (VREF - 3/2 LSB). Units in mV . Positive Full Scale Drift - The drift in effective, positive, full-scale input voltage with temperature. Negative Full Scale Error - The deviation of the first code transition from the ideal, (-VREF + 1/2 LSB). Units in mV . Negative Full Scale Drift - The drift in effective, negative, full-scale input voltage with temperature. Bipolar Offset - The deviation of the mid-scale transition from the ideal. The ideal is defined as the middle transition lying on a straight line between actual positive full-scale and actual negative full-scale. Bipolar Offset Drift - The drift in the bipolar offset error with temperature. Absolute Group Delay - The delay through the filter section of the part. Passband Frequency - The upper -3 dB frequency of the CS5317. CS5317 DS27F4 19

Model Number Temperature Range Package CS5317-KP 0 to 70 °C 18 Pin Plastic DIP CS5317-KS 0 to 70 °C 20 Pin Plastic SOIC CS5317

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APPLICATIONS

Figure A1 shows one method of converting the serial output of the CS5317 into 16-bit, parallel words. The associated timing is also shown. A PA PB PC PD PE PF PG PH 74HCT299 QH PA PB PC PD PE PF PG PH D10 D11 D12 D13 D14 D15 74HCT299 CS5317 DATA DOUT CLKOUT CS Data Bus +5V OE2 +5V OE2 A OE1 OE1 INT INT Only needed for level sensitive interrupt driven systems. D Q Q SET 74HCT74 15 1314 02 1 INT Cleared when data read (CS goes low) (MSB) DATA INT CLKOUT DOUT Figure A1. CS5317-to-Parallel Data Bus Interface CS5317 DS27F4 21

Figure A2 shows the interconnection and timing details for connecting a CS5317 to a NEC µPD7730 DSP chip. Figure A3 shows the interconnection and timing details for connecting a CS5317 to a Motorola DSP 56000. Status Register (SR) Meaning External Clock 16 bit data MSB First Setting 1, 0 Bit 7, 6 Mnemonic SCI SDLI SIF µPD77230 SICK SI SIEN CS5317 DATA CLKOUT DOUT 15 1314DATA CLKOUT DOUT 02 1 (MSB) Figure A2. CS5317-to-NEC µPD77230 Serial Interface CS5317 DATA CLKOUT DOUT DSP56000 SCK, SC0 SRD SC2, SC1 SSI Control Reg. A CRA (X:FFEC) WL1 = 1 WL0 = 0 16 bits ASYNC SC0 SC1 SYNC SCK SC2 CLKOUT DOUT GCK SYN FSL SCKD SCD2 SCD1 SCD0 PINS SSI Control Reg. B CRB (X:FFED) 15 1314DATA CLKOUT DOUT 02 1 (MSB) Figure A3. CS5317-to-Motorola DSP56000 Serial Interface CS5317

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Figure A4 shows the interconnection and timing details for connecting a CS5317 to a WE DSP16 DSP chip. Figure A5 shows the interconnection and timing details for connecting a CS5317 with TMS32020 and TMS320C25 DSP chips. CS5317 DATA CLKOUT DOUT DSP16 ICK DI ILD QD DATA d Serial I/O Control Register (SIOC) Meaning MSB input first ILD is an input ICK is an input 16 bit input data Value Field MSB ILD ICK ILEN CLKOUT DOUT DATA d 15 1314 2 1 0 (MSB) Figure A4. CS5317-to-WE DSP16 Serial Interface TMS32020 TMS320C25 CLKR DR FSR CS5317 DATA CLKOUT DOUT TMS32020 Status Register (ST1): F0 = 0 (16 bit data) TMS320C25 Status Register (ST1): FSM = 1 (Frame Sync used) F0 = 0 (16 bit data) 15 1314DATA CLKOUT DOUT 02 1 (MSB) Figure A5. CS5317-to-TMS32020/TMS320C25 Serial Interface CS5317 DS27F4 23

• Notes •

Copyright  Cirrus Logic, Inc. 1998 (All Rights Reserved) Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com CDB5317 Evaluation Board for CS5317 /c108 Easy to Use Digital Interface Parallel 16 Bits With Clock Serial Output With Clock /c108 Multiple Operating Modes Including Two PLL Modes /c108 IDC Header used to access Parallel Data, Serial Data, and Clock Input and Output The CDB5317 Evaluation Board is designed to allow the user to quickly evaluate performance of the CS5317 Del- ta-Sigma Analog-to-Digital Converter. All that is required to use this board is an external power supply, a signal source, a clock source, and an ability to read either serial or parallel 16bitdata words. I CLKIN CS5317 CONVERTER SERIAL TO PARALLELCLKOUT DATA D0-D15 IDC HEADER AIN DACK +5V -5VGND CLKIN DRDY VL MAR ‘95 DS27DB3

CS5317 Delta-Sigma Analog-to-Digital Converter.

• The CDB5317 Evaluation Board.
• A power supply capable of supplying +5V and -5V .
• A clock source as the CLKIN signal of the CS5317.
• A spectrally pure sine wave generator such as the Krohn-Hite Model 4400A "Ultra-Low Distor- tion Oscillator".
• A PC equipped with a digital data acquisition board such as the Metrabyte Model PIO12 "24 Bit Parallel Digital I/O Interface".
• A software routine to collect the data and per- form a Fast Fourier Transform (FFT). The evaluation board includes filter components for the on-chip phase locked loop. The compo- nents are adequate for testing if the CLKIN signal has little or no phase-jitter. If the CDB5317 board is being tested as part of a system which generates a CLKIN which contains jitter, the PLL filter components may need to be optimized for your system (see the CS5317 data sheet). Set-up for evaluation is straightforward. First de- cide the operating mode and place the jumper on the board for the proper selection. Then decide whether the filter components for the phase locked loop are adequate or whether they should be changed for your evaluation. The PLL will lock on a steady clock input with the filter as it is. Connect the necessary 5 V (CMOS compatible) CLKIN signal for the application. Use the sine- wave generator to supply the analog signal to the CDB5317. Apply the analog input and CLKIN signals only when the evaluation board is pow- ered up. Converted data will then appear at the header on the CDB5317. The header should be connected to the digital data acquisition board in the PC through an IDC 40 pin connector and ca- ble. The software routine should collect the data from the CDB5317 and run a standard 1024 point Fast Fourier Transform (FFT). Such an analysis results in a plot similar to Figure 1. This plot re- sulted from using a 1kHz input signal and a Blackman-Harris window for the FFT. The signal to noise and signal to total harmonic distortion characteristics of the CS5317 may be easily measured in this way. The signal to total harmonic distortion value for a particular input is the ratio of the RMS value of the input signal and the sum of the RMS values of the harmonics shown in the diagram. The dynamic range of the CS5317 can be measured by reducing the input

Figure 1. FFT Plot Example

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6 U5 5

Figure 3. Buffers and Parallel Handshake Flip-Flop

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of the DOUT signal from the CS5317 is used to latch the data once it is input to the shift registers. The rising edge of DOUT is also used to toggle the DRDY flip flop (see Figure 3). The flip flop is used to signal a remote device whenever new data is latched into the output registers. The DRDY flip flop is reset whenever DACK occurs. A component layout of the CDB5317 board is il- lustrated in Figure 7. D10 D11 D12 D13 D14 D15 DATA CLKOUT QH QG QF QE QD QC QB QA GND LATCH CLK SHIFT CLK DIN 74HC595 RST CLKIN DACK DRDY QH QG QF QE QD QC QB QA GND 74HC595 TP4 TP5 10k VL 10 16 0.1 µF VL 10 16 0.1 µF CLKOUT2 (fig. 3) (fig. 2) CLKIN RST LATCH CLK SHIFT CLK DIN DOUT DATA1 (fig. 3) (fig. 2) DATA (fig. 3) (fig. 3) DOUT2 CLKOUT DRDY (fig. 3) (fig. 3) DACK OE Figure 6. CDB5317

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Figure 7. Bird’s Eye View