CS5101A-AP8

CS5101A CIRRUS | Alldatasheet

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Technical content

Features

lMonolithic CMOS A/D Converters - Inherent Sampling Architecture - 2-Channel Input Multiplexer - Flexible Serial Output Port lUltra-Low Distortion - S/(N+D): 92 dB - THD: 0.001% lConversion Time - CS5101A: 8 µs - CS5102A: 40 µs lLinearity Error: ±0.001% FS - Guaranteed No Missing Codes lSelf-Calibration Maintains Accuracy - Over Time and Temperature lLow Power Consumption - CS5101A: 320 mW - CS5102A: 44 mW - Power-down Mode: <1 mW lEvaluation Board Available

Description

The CS5101A and CS5102A are 16-bit monolithic CMOS analog-to-digital converters capable of 100 kHz (5101A) and 20 kHz (5102A) throughput. The CS5102A's low power consumption of 44 mW, coupled with a power down mode, makes it particularly suitable for battery powered operation. On-chip self-calibration circuitry achieves nonlinearity of ±0.001% of FS and guarantees 16-bit no missing codes over the entire specified temperature range. Superior lin- earity also leads to 92 dB S/(N+D) with harmonics below -100 dB. Offset and full-scale errors are minimized dur- ing the calibration cycle, eliminating the need for external trimming. The CS5101A and CS5102A each consist of a 2-chan- nel input multiplexer, DAC, conversion and calibration microcontroller, clock generator, comparator, and serial communications port. The inherent sampling architec- ture of the device eliminates the need for an external track and hold amplifier. The converters' 16-bit data is output in serial form with ei- ther binary or 2's complement coding. Three output timing modes are available for easy interfacing to micro- controllers and shift registers. Unipolar and bipolar input ranges are digitally selectable.

ORDERING INFORMATION

See page 36. I CLKIN REFBUF VREF AIN1 AGND HOLD SLEEP RST CODE BP/UP TRK1 TRK2 SSH/SDL SDATA SCLK TEST DGND VD- VD+VA-VA+ 12 28 2 5 16 17 8 9 11 15 25 23 7 1 6 Clock Generator Control Calibration Microcontroller Comparator 16-Bit Charge SRAM Redistribution DAC STBY CRS/FIN XOUT 4 AIN2 24 CH1/2 13 SCKMOD OUTMOD MAR ‘95 DS45F2

CS5101A -J,K CS5101A -A ,B Parame ter* Min Typ Ma x Min Typ Ma x U nits Specified Temperature Range 0 to +70 -40 to +85 °C Accu racy Linearity Error -J,A,S (Note 1) -K,B,T Drift (Note 2) 0.002 0.001 ± 1/4 0.003 0.002 0.002 0.001 ± 1/4 0.003 0.002 %FS %FS ΔLSB D ifferential Linearity (N otes 3, 4) 16 - - 16 - - Bits Full Scale Error -J,A,S (Note 1) -K,B,T Drift (Note 2) ± 1 ± 1 ± 1 ± 4 ± 3 ± 1 ± 1 ± 1 ± 4 ± 3 LSB LSB ΔLSB Unipolar Offset -J,A,S (Note 1) -K,B,T Drift (Note 2) ± 2 ± 2 ± 1 ± 5 ± 4 ± 2 ± 2 ± 1 ± 5 ± 4 LSB LSB ΔLSB Bipolar Offset -J,A,S (Note 1) -K,B,T Drift (Note 2) ± 2 ± 2 ± 1 ± 5 ± 3 ± 2 ± 2 ± 2 ± 5 ± 3 LSB LSB ΔLSB Bipolar Negative Full-Scale Error -J,A,S (Note 1) -K,B,T Drift (Note 2) ± 1 ± 1 ± 1 ± 4 ± 3 ± 1 ± 1 ± 1 ± 4 ± 3 LSB LSB ΔLSB Dyn amic Performance (Bipolar Mode) Peak Harmonic or Spurious Noise (Note 1) 1 kHz Input -J,A,S -K,B,T 12 kHz Input -J,A,S -K,B,T 100 102 100 102 dB dB dB dB Total Harmonic Distortion -J,A,S -K,B,T 0.002 0.001 0.002 0.001 Signal-to-Noise Ratio (Note 1) 0dB Input -J,A,S -K,B,T -60 dB Input -J,A,S -K,B,T dB dB dB dB Noise (Note 5) Unipolar Mode Bipolar Mode µV rms µVrms CS5101A ANALOG CHARACTERISTICS (TA = TMIN to TMAX ; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; Full-Scale Input Sinewave, 1 kHz; CLKIN = 4 MHz for -16, 8 MHz for -8; fs = 50 kHz for -16, 100 kHz for -8; Bipolar Mode; FRN Mode; AIN1 and AIN2 tied together, each channel tested separately; Analog Source Impedance = 50 Ω with 1000 pF to AGND unless otherwise specified) Notes: 1. Applies after calibration at any temperature within the specified temperature range. At temp 2. Total drift over specified temperature range after calibration at power-up at 25 °C. 3. Minimum resolution for which no missing codes is guaranteed over the specified temperature range. 4. Clock speeds of less than 1.0 MHz, at temperatures >100°C will degrade DNL performance. 5. Wideband noise aliased into the baseband. Referred to the input. *Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet). Specifications are subject to change without notice.

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Notes: 6. Applies only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF. 7. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback (FRN mode) with 8.0 MHz CLKIN. In PDT, RBT, and SSC modes, asynchronous delay between the falling edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will not exceed 1.5 master clock cycles + 10 ns. In PDT, RBT, and SSC modes, CLKIN can be increased as long as the HOLD sample rate is 100 kHz max. 8. The CS5101A requires 6 clock cycles of coarse charge, followed by a minimum of 1.125 µs of fine charge. FRN mode allows 9 clock cycles for fine charge which provides for the minimum 1.125 µs with an 8 MHz clock, however; in PDT, RBT, or SSC modes, at clock frequencies of 8 MHz or less, fine charge may be less than 9 clock cycles. This reflects the typ. specification (6 clock cycles + 1.125 µs). 9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition and conversion times, as described above. 10. All outputs unloaded. All inputs at VD+ or DGND. 11. Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low). 12. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the unipolar mode to 90 dB. Figure 23 shows a plot of typical power supply rejection versus frequency. ANALOG CHARACTERISTICS (continued) C S5101A -J,K C S5101A -A ,B Parame ter* Sym bol Min Typ Ma x Min Typ Ma x U nits Specified Tempe rature Range - 0 to +70 40 to +85 °C A nalog Input Aperture Time - - 25 - - 25 - ns Aperture Jitter - - 100 - - 100 - ps Input Capacitance (Note 6) Unipolar Mode Bipolar Mode 320 200 425 265 320 200 425 265 pF pF C onversion & Throughput Conversion Time (Note 7) -16 tc tc 8.12 16.25 8.12 16.25 µs µs Acquisition Time (Note 8) -16 t a ta 2.6 1.88 3.75 2.6 1.88 3.75 µs µs Throughput (Note 9) -16 f tp ftp 100 100 kHz kHz Pow er Supplies Power Supply Current (Note 10) Positive Analog Negative Analog (SLEEP High) Positive Digital Negative Digital IA+ IA- ID + ID - -21 -11 -28 -15 -21 -11 -28 -15 mA mA mA mA Power Consumption (Notes 10, 11) (SLEEP High) (SLEEP Low) P do Pds 320 430 320 430 mW mW Power Supply Rejection: (Note 12) Positive Supplies Negative Supplies PSR PSR dB dB DS45F2 3

Notes: 13. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 8.0 MHz in FRN mode (100 kHz sample rate). 14. With a 8 MHz crystal, two 10 pF loading capacitors and a 10 MΩ parallel resistor (see Figure 8). 15. These times are for FRN mode. 16. SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge occurs after HOLD rises to 64 tclk after HOLD has fallen. These times are for PDT and RBT modes. 17. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as narrow as 150 ns for all CLKIN frequencies if CLKIN falls 95 ns after HOLD falls. This ensures that the HOLD pulse will meet the minimum specification for thcf. SWITCHING CHARACTERISTICS (TA = TMIN to TMAX ; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) Parameter Symbol Min Typ Max Units CLKIN Period (Note 4) -16 tclk tclk 108 250 10,000 10,000 ns ns CLKIN Low Time t clkl 37.5 - - ns CLKIN High Time t clkh 37.5 - - ns Crystal Frequency (Note 13) -16 fxtal fxtal 2.0 2.0 9.216 4.0 MHz MHz SLEEP Rising to Oscillator Stable (Note 14) - - 2 - ms RST Pulse Width t rst 150 - - ns RST to STBY Falling t drrs - 100 - ns RST Rising to STBY Rising t cal - 11,528,160 - t clk CH1/2 Edge to TRK1, TRK2 Rising (Note 15) t drsh1 -8 0- n s CH1/2 Edge to TRK1, TRK2 Falling (Note 15) t dfsh4 - - 68t clk+260 ns HOLD to SSH Falling (Note 16) t dfsh2 -6 0 n s HOLD to TRK1, TRK2, Falling (Note 16) t dfsh1 66tclk - 68t clk+260 ns HOLD to TRK1, TRK2, SSH Rising (Note 16) t drsh - 120 - ns HOLD Pulse Width (Note 17) t hold 1tclk+20 - 63t clk ns HOLD to CH1/2 Edge (Note 16) t dhlri 15 - 64t clk ns HOLD Falling to CLKIN Falling (Note 17) t hcf 95 - 1tclk+10 ns

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ANALOG CHARACTERISTICS (TA = TMIN to TMAX ; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; Full-Scale Input Sinewave, 200 Hz; CLKIN = 1.6 MHz; fs = 20 kHz; Bipolar Mode; FRN Mode; AIN1 and AIN2 tied together, each channel tested separately; Analog Source Impedance = 50 Ω with 1000pF to AGND unless otherwise specified) CS5102A -J,K CS5102A -A ,B Parame ter* Min Typ Ma x Min Typ Ma x U nits Specified Temperature Range 0 to +70 -40 to +85 °C Accu racy Linearity Error -J,A,S (Note 1) -K,B,T Drift (Note 2) 0.002 0.001 ± 1/4 0.003 0.0015 0.002 0.001 ± 1/4 0.003 0.0015 %FS %FS ΔLSB D ifferential Linearity (N otes 3, 18) 16 - - 16 - - Bits Full Scale Error -J,A,S (Note 1) -K,B,T Drift (Note 2) ± 2 ± 2 ± 1 ± 4 ± 3 ± 2 ± 2 ± 1 ± 4 ± 3 LSB LSB ΔLSB Unipolar Offset -J,A,S (Note 1) -K,B,T Drift (Note 2) ± 1 ± 1 ± 1 ± 4 ± 3 ± 1 ± 1 ± 1 ± 4 ± 3 LSB LSB ΔLSB Bipolar Offset -J,A,S (Note 1) -K,B,T Drift (Note 2) ± 1 ± 1 ± 1 ± 4 ± 3 ± 1 ± 1 ± 2 ± 4 ± 3 LSB LSB ΔLSB Bipolar Negative -J,A,S (Note 1) Full-Scale Error -K,B,T Drift (Note 2) ± 2 ± 2 ± 1 ± 4 ± 3 ± 2 ± 2 ± 2 ± 4 ± 3 LSB LSB ΔLSB Dyn amic Performance (Bipolar Mode) Peak Harmonic or -J,A,S (Note 1) Spurious Noise -K,B,T 100 102 100 102 dB dB Total Harmonic Distortion -J,A,S -K,B,T 0.002 0.001 0.002 0.001 Signal-to-Noise Ratio (Note 1) 0dB Input -J,A,S -K,B,T -60 dB Input -J,A,S -K,B,T dB dB dB dB Noise (Note 5) Unipolar Mode Bipolar Mode µV rms µVrms Note: 18. Clock speeds of less than 1.6 MHz, at temperatures >100°C will degrade DNL performance. *Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet). Specifications are subject to change without notice. CS5102A DS45F2 5

Notes: 19. Conversion time scales directly to the master clock speed. The times shown are for synchronous, internal loopback (FRN mode). In PDT, RBT, and SSC modes, asynchronous delay between the falling edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will not exceed 1 master clock cycle + 140 ns. 20. The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µs of fine charge. FRN mode allows 9 clock cycles for fine charge which provides for the minimum 5.625 µs with an 1.6 MHz clock, however; in PDT, RBT, or SSC modes, at clock frequencies less than 1.6 MHz, fine charge may be less than 9 clock cycles. 21. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions affecting acquisition and conversion times, as described above. 23. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection improves by 6 dB in the unipolar mode to 90 dB. Figure 23 shows a plot of typical power supply rejection versus frequency. CS5102A ANALOG CHARACTERISTICS (continued) CS5102A -J,K CS5102A -A ,B Parame ter* Sym bol Min Typ Ma x Min Typ Ma x U nits Specified Tempe rature Range - 0 to +70 40 to +85 °C A nalog Input Aperture Time - - 30 - - 30 - ns Aperture Jitter - - 100 - - 100 - ps Input Capacitance (Note 6) Unipolar Mode Bipolar Mode 320 200 425 265 320 200 425 265 pF pF C onversion & Throughput Con version Tim e (N ote 19) tc - - 40.625 - - 40.625 µs Acquisition Tim e (N ote 20) ta - - 9.375 - - 9.375 µs Throughput (N ote 21) ftp 20 - - 20 - - kHz Pow er Supplies Power Supply Current (Note 22) Positive Analog Negative Analog (SLEEP High) Positive Digital Negative Digital I IA- ID + ID - 2.4 -2.4 2.5 -1.5 3.5 -3.5 3.5 -2.5 2.4 -2.4 2.5 -1.5 3.5 -3.5 3.5 -2.5 mA mA mA mA Power Consumption (Notes 11, 22) (SLEEP High) (SLEEP Low) P do Pds mW mW Power Supply Rejection: (Note 23) Positive Supplies Negative Supplies PSR PSR dB dB Typ. Power (mW) CLKIN (MHz) 34 0.8 37 1.0 39 1.2 41 1.4 44 1.6

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SWITCHING CHARACTERISTICS (TA = TMIN to TMAX ; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) Parameter Symbol Min Typ Max Units CLKIN Period (Note 18,24) t clk 0.5 - 10 µs CLKIN Low Time t clkl 200 - - ns CLKIN High Time t clkh 200 - - ns Crystal Frequency (Note 24, 25) f xtal 0.9 1.6 2.0 MHz SLEEP Rising to Oscillator Stable (Note 26) - - 20 - ms RST Pulse Width t rst 150 - - ns RST to STBY Falling t drrs - 100 - ns RST Rising to STBY Rising t cal - 2,882,040 - t clk CH1/2 Edge to TRK1, TRK2 Rising (Note 27) t drsh1 -8 0- n s CH1/2 Edge to TRK1, TRK2 Falling (Note 27) t dfsh4 - - 68t clk+260 ns HOLD to SSH Falling (Note 28) t dfsh2 -6 0 n s HOLD to TRK1, TRK2, Falling (Note 28) t dfsh1 66tclk - 68t clk+260 ns HOLD to TRK1, TRK2, SSH Rising (Note 28) t drsh - 120 - ns HOLD Pulse Width (Note 29) t hold 1tclk+20 - 63t clk ns HOLD to CH1/2 Edge (Note 28) t dhlri 15 - 64t clk ns HOLD Falling to CLKIN Falling (Note 29) t hcf 55 - 1tclk+10 ns Note: 24. Minimum CLKIN period is 0.625 µs in FRN mode (20 kHz sample rate). At temperatures >+85 °C, and with clock frequencies <1.6 MHz, analog performance may be degraded. 25. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 1.6 MHz in FRN mode (20 kHz sample rate). 26. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 MΩ parallel resistor (see Figure 8). 27. These times are for FRN mode. 28. SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge occurs after HOLD rises to 64 tclk after HOLD has fallen. These times are for PDT and RBT modes. 29. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as narrow as 150 ns for all CLKIN frequencies if CLKIN falls 55 ns after HOLD falls. This ensures that the HOLD pulse will meet the minimum specification for thcf. CS5102A DS45F2 7

SSH,TRK1,TRK2 dfsh2t drsht dfsh1t TRK1,TRK2 TRK1,TRK2 TRK1,TRK2 SSH/SDL Control Output Timing Reset and Calibration Timing Channel Selection Timing a. FRN Mode b. PDT, RBT Mode Start Conversion Timing CS5101A CS5102A

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SWITCHING CHARACTERISTICS (Continued) Parameter Symbol Min Typ Max Units PDT and RBT Modes SCLK Input Pulse Period t sclk 200 - - ns SCLK Input Pulse Width Low t sclkl 50 - - ns SCLK Input Pulse Width High t sclkh 50 - - ns SCLK Input Falling to SDATA Valid t dss - 100 150 ns HOLD Falling to SDATA Valid PDT Mode t dhs - 140 230 ns TRK1, TRK2 Falling to SDATA Valid (Note 30) t dts - 65 125 ns FRN and SSC Modes SCLK Output Pulse Width Low t slkl -2 t clk -t clk SCLK Output Pulse Width High t slkh -2 t clk -t clk SDATA Valid Before Rising SCLK t ss 2tclk-100 - - ns SDATA Valid After Rising SCLK t sh 2tclk-100 - - ns SDL Falling to 1st Rising SCLK t rsclk -2 t clk -n s Last Rising SCLK to SDL Rising CS5101A CS5102A trsdl trsdl 2tclk 2tclk 2tclk+165 2tclk+200 ns ns HOLD Falling to 1st Falling SCLK CS5101A CS5102A thfs thfs 6tclk 6tclk clk+165 8tclk+200 ns ns CH1/2 Edge to 1st Falling SCLK t chfs -7 t c l k- t clk Note: 30. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is valid tdss time after the next falling SCLK. DIGITAL CHARACTERISTICS (TA = Tmin to Tmax ; VA+, VD+ = 5V ± 10%; VA-, VD- = 5V ± 10%) Parameter Symbol Min Typ Max Units Calibration Memory Retention (Note 31) Power Supply Voltage VA+ and VD+ VMR 2.0 - - V High-Level Input Voltage V IH 2.0 - - V Low-Level Input Voltage V IL -- 0 . 8 V High-Level Output Voltage (Note 32) V OH (VD+)-1.0 - - V Low-Level Output Voltage I OUT = 1.6 mA V OL -- 0 . 4 V Input Leakage Current I in -- 1 0 µA Digital Output Pin Capacitance C out -9- p F Notes: 31. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be allowed to go positive. AIN1, AIN2 or VREF must not be greater than VA+ or VD+. This parameter is guaranteed by characterization. 32. I OUT = -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ Iout = -40 µA). CS5101A CS5102A DS45F2 9

TRK1, TRK2 sst MSB SCLK sht SDATA slkhtslklt dsst chfst CH1/2 HOLD hfst SSH/SDL rsclkt LSB rsdlt Data Transmission Timing a. SCLK input (RBT and PDT mode) b. SCLK output (SSC and FRN modes) a. Pipelined Data Transmission (PDT) b. Register Burst Transmission (RBT) Mode Serial Data Timing CS5101A CS5102A

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Notes: 35. In addition, VD+ must not be greater than (VA+) +0.3V 36. Transient currents of up to 100 mA will not cause SCR latch-up. *WARNING: Operation beyond these limits may result in permanent damage to the device. Notes: 33. All voltages with respect to ground. 34. The CS5101A and CS5102A can accept input voltages up to the analog supplies (VA+ and VA-). They will produce an output of all 1’s for inputs above VREF and all 0’s for inputs below AGND in unipolar mode and -VREF in bipolar mode, with binary coding (CODE = low). RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 33) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 VA+ -5.5 5.5 -5.5 V V V V Analog Reference Voltage VREF 2.5 4.5 (VA+)-0.5 V Analog Input Voltage: (Note 34) Unipolar Bipolar V AIN VAIN AGND -VREF VREF VREF V V ABSOLUTE MAXIMUM RATINGS* (AGND, DGND = 0V, all voltages with respect to ground) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital (Note 35) Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- -0.3 0.3 -0.3 0.3 6.0 -6.0 6.0 -6.0 V V V V Input Current, Any Pin Except Supplies (Note 36) I in -- ±10 mA Analog Input Voltage (AIN and VREF pins) V INA (VA-)-0.3 - (VA+)+0.3 V Digital Input Voltage V IND -0.3 - (VA+)+0.3 V Ambient Operating Temperature T A -55 - 125 °C Storage Temperature T stg -65 - 150 °C Ambient Operating Temperature T A -55 - 125 °C Storage Temperature T stg -65 - 150 °C CS5101A CS5102A DS45F2 11

tracking of high-slew signals. ing or converting, all capacitors are tied to AIN. and the signal at the analog input pin is ignored. hold capacitor in a sample/hold amplifier. Figure 1. Coarse Charge Input Buffers and Charge Redistribution DAC

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The ability of the CS5101A or the CS5102A to convert accurately to 16-bits clearly depends on the accuracy of its comparator and DAC. Each device utilizes an "auto-zeroing" scheme to null errors introduced by the comparator. All offsets are stored on the capacitor array while in the track mode and are effectively subtracted from the input signal when a conversion is initiated. Auto-zeroing enhances power supply rejection at frequencies well below the conversion rate. To achieve 16-bit accuracy from the DAC, the CS5101A and CS5102A use a novel self-calibra- tion scheme. Each bit capacitor shown in Figure 1 actually consists of several capacitors in parallel which can be manipulated to adjust the overall bit weight. An on-chip micro controller precisely adjusts each capacitor with a resolution of 18 bits. The CS5101A and CS5102A should be reset upon power-up, thus initiating a calibration cycle. The device then stores its calibration coefficients in on-chip SRAM. When the CS5101A and CS5102A are in power-down mode ( SLEEP low), they retain the calibration coefficients in memory, and need not be recalibrated when nor- mal operation is resumed. OPERATION OVERVIEW Monolithic design and inherent sampling archi- tecture make the CS5101A and CS5102A extremely easy to use. Initiating Conversions A falling transition on the HOLD pin places the input in the hold mode and initiates a conversion cycle. The charge is trapped on the capacitor ar- ray the instant HOLD goes low. The device will complete conversion of the sample within 66 master clock cycles, then automatically return to the track mode. After allowing a short time for acquisition, the device will be ready for another conversion. In contrast to systems with separate track-and- holds and A/D converters, a sampling clock can simply be connected to the HOLD input. The duty cycle of this clock is not critical. The HOLD input is latched internally by the master clock, so it need only remain low for 1/fclk + 20 ns, but no longer than the minimum conversion time minus two master clocks or an additional conversion cy- cle will be initiated with inadequate time for acquisition. In Free Run mode, SCKMOD = OUTMOD = 0, the device will convert at a rate of CLKIN/80, and the HOLD input is ignored. As with any high-resolution A-to-D system, it is recommended that sampling is synchronized to the master system clock in order to minimize the effects of clock feedthrough. However, the CS5101A and CS5102A may be operated entirely asynchronous to the master clock if necessary. Tracking the Input Upon completing a conversion cycle the CS5101A and CS5102A immediately return to the track mode. The CH1/ 2 pin directly controls the input switch, and therefore directly deter- mines which channel will be tracked. Ideally, the CH1/ 2 pin should be switched during the conver- sion cycle, thereby nullifying the input mux switching time, and guaranteeing a stable input at the start of acquisition. If, however, the CH1/2 control is changed during the acquisition phase, adequate coarse charge and fine charge time must be allowed before initiating conversion. When the CS5101A or the CS5102A enters track- ing mode, it uses an internal input buffer amplifier to provide the bulk of the charge on the capacitor array (coarse-charge), thereby reducing the current load on the external analog circuitry. Coarse-charge is internally initiated for 6 clock cycles at the end of every conversion. The buffer CS5101A CS5102A DS45F2 13

amplifier is then bypassed, and the capacitor ar- ray is directly connected to the input. This is referred to as fine-charge, during which the charge on the array is allowed to accurately settle to the input voltage (see Figure 10). With a full scale input step, the coarse-charge in- put buffer of the CS5101A will charge the capacitor array within 1% in 650 ns. The con- verter timing allows 6 clock cycles for coarse charge settling time. When the CS5101A switches to fine-charge mode, its slew rate is somewhat reduced. In fine-charge, the CS5101A can slew at 2 V/µs in unipolar mode. In bipolar mode, only half the capacitor array is connected to the analog input, so the CS5101A can slew at 4V/µs. With a full scale input step, the coarse-charge in- put buffer of the CS5102A will charge the capacitor array within 1% in 3.75 µs. The con- verter timing allows 6 clock cycles for coarse charge settling time. When in fine-charge mode, the CS5102A can slew at 0.4 V/µs in unipolar mode; and at 0.8 V/µs in bipolar mode. Acquisition of fast slewing signals can be has- tened if the voltage change occurs during or immediately following the conversion cycle. For instance, in multiple channel applications (using either the device’s internal channel selector or an external MUX), channel selection should occur while the CS5101A or the CS5102A is convert- ing. Multiplexer switching and settling time is thereby removed from the overall throughput equation. If the input signal changes drastically during the acquisition period (such as changing the signal source), the device should be in coarse-charge for an adequate period following the change. The CS5101A and CS5102A can be forced into coarse-charge by bringing CRS/FIN high. The buffer amplifier is engaged when CRS/FIN is high, and may be switched in any number of times during tracking. If CRS/FIN is held low, the CS5101A and CS5102A will only coarse- charge for the first 6 clock cycles following a conversion, and will stay in fine-charge until HOLD goes low. To get an accurate sample using the CS5101A, at least 750 ns of coarse-charge, followed by 1.125 µs of fine-charge is required before initiating a conversion. If coarse charge is not invoked, then up to 25 µs should be allowed after a step change input for proper acquisition. To get an accurate sample using the CS5102A, at least 3.75 µs of coarse-charge, followed by 5.625 µs of fine-charge is required before initiat- ing a conversion (see Figure 2). If coarse charge is not invoked, then up to 125 µs should be al- lowed after a step change input for proper acquisition. The CRS/ FIN pin must be low prior to HOLD becoming active and be held low dur- ing conversion. Master Clock The CS5101A and CS5102A can operate either from an externally-supplied master clock, or from their own crystal oscillator (with a crystal). To enable the internal crystal oscillator, simply tie a crystal across the XOUT and CLKIN pins and add 2 capacitors and a resistor, as shown on the system connection diagram in Figure 8. Calibration and conversion times directly scale to the master clock frequency. The CS5101A-8 can operate with clock or crystal frequencies up to 9.216 MHz (8.0 MHz in FRN mode). This allows maximum throughput of up to 50 kHz per chan- nel in dual-channel operation, or 100 kHz in a single channel configuration. The CS5101A-16 can accept a maximum clock speed of 4 MHz, with corresponding throughput of 50 kHz. The CS5102A can operate with clock or crystal frequen- cies up to 2.0 MHz (1.6 MHz in FRN mode). This allows maximum throughput of up to 10 kHz per channel in dual-channel operation, or 20 kHz in a single channel configuration. For 16 bit performance a 1.6 MHz clock is recommended. This 1.6 MHz CS5101A CS5102A

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a single channel configuration.

8 MHz CLKIN, with a 100 kHz HOLD signal, then

8.192 MHz) then sufficient fine charge time will

transition occurs 1.5 LSB’s below +VREF. ment format with a range of -32,768 to +32,767. Status Conv. Coarse Fine Chg. Coarse Fine Chg. Conv. Figure 2. Coarse-Charge/Fine-Charge Control Table 1. Output Coding

is updated on the falling edge of SCLK. Figure 3. Pipelined Data Transmission Mode (PDT) Table 2. Serial Output Modes

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Registered Burst Transmission (RBT) RBT mode is selected by tying SCKMOD high, and OUTMOD low. As in PDT mode, SCLK is an input, however data is available immediately following conversion, and may be clocked out the moment TRK1 or TRK2 falls. The falling edge of HOLD clears the output buffer, so any unread data will be lost. A new conversion may be initiated before all the data has been clocked out if the unread data bits are not important (Figure 4). Synchronous Self-Clocking (SSC) SSC mode is selected by tying SCKMOD low, and OUTMOD high. In SSC mode, SCLK is an output, and will clock out each bit of the data as it’s being converted. SCLK will remain high be- tween conversions, and run at a rate of 1/4 the master clock speed for 16 low pulses during con- version (Figure 5). The SSH/SDL goes low coincident with the first falling edge of SCLK, and returns high 2 CLKIN cycles after the last rising edge of SCLK. This signal frames the 16 data bits and is useful for interfacing to shift registers (e.g. 74HC595) or to DSP serial ports. Free Run (FRN) Free Run is the internal, synchronous loopback mode. FRN mode is selected by tying SCKMOD and OUTMOD low. SCLK is an output, and op- erates exactly the same as in the SSC mode. In Free Run mode, the converter initiates a new conversion every 80 master clock cycles, and al- ternates between channel 1 and channel 2. HOLD is disabled, and should be tied to either VD+ or DGND. CH1/ 2 is an output, and will change at the start of each new conversion cycle, indicating which channel will be tracked after the current conversion is finished (Figure 6). The SSH/SDL goes low coincident with the first falling edge of SCLK, and returns high 2 CLKIN cycles after the last rising edge of SCLK. This signal frames the 16 data bits and is useful for interfacing to shift registers (e.g. 74HC595) or to DSP serial ports. SYSTEM DESIGN WITH THE CS5101A AND CS5102A Figure 7 shows a general system connection dia- gram for the CS5101A and CS5102A. Digital Circuit Connections When TTL loads are utilized the potential for crosstalk between digital and analog sections of the system is increased. This crosstalk is due to high digital supply and signal currents arising from the TTL drive current required of each digi- tal output. Connecting CMOS logic to the digital outputs is recommended. Suitable logic families include 4000B, 74HC, 74AC, 74ACT, and 74HCT. System Initialization Upon power up, the CS5101A and CS5102A must be reset to guarantee a consistent starting condition and initially calibrate the device. Due to each device’s low power dissipation and low temperature drift, no warm-up time is required before reset to accommodate any self-heating ef- fects. However, the voltage reference input should have stabilized to within 0.25% of its final value before RST rises to guarantee an accurate calibration. Later, the CS5101A and CS5102A may be reset at any time to initiate a single full calibration. When RST is brought low all internal logic clears. When RST returns high on the CS5101A, a calibration cycle begins which takes 11,528,160 master clock cycles to complete (approximately 1.4 seconds with an 8 MHz master clock). The CS5101A CS5102A

18 DS45F2

be established prior RST rising.

8.0 MHz

8.192 MHz

1.6 MHz

2.0 MHz

Figure 7. CS5101A/CS5102A System Connection Diagram

as well as grounding and decoupling schemes. it offers several built-and-tested reference circuits. any errors due to offsets and/or noise in the buffer. the array after coarse-charging from the buffer. without changing its output voltage significantly. sequence of the internal capacitor array changes. exhibit extremely low output impedance at dc. Figure 8. Power-up Reset Circuit

20 DS45F2

ramic capacitor is recommended. occur because of capacitive loading at its output. before the resistor is added. erence voltages up to the positive analog supply. REFBUF, and the negative analog supply, V A-. CS501X Series of A/D Converters". accurate unbuffered version. Figure 9. Reference Connections

8 MHz Clock

2.0 MHz Clock

Figure 10. Charge Settling Time

Fine-charge settling is specified as a maximum of 1.125 µs (CS5101A) or 5.625 µs (CS5102A) for an analog source impedance of less than 50 Ω . In addition, the comparator requires a source imped- ance of less than 400 Ω around 2 MHz for stability. The source impedance can be effectively reduced at high frequencies by adding capaci- tance from AIN to ground (typically 200 pF). However, high dc source resistances will increase the input’s RC time constant and extend the nec- essary acquisition time. For more information on input amplifiers, consult the application note: Buffer Amplifiers for the CS501X Series of A/D Converters. SLEEP Mode Operation The CS5101A and CS5102A include a SLEEP pin. When SLEEP is active (low) each device will dissipate very low power to retain its calibra- tion memory when the device is not sampling. It does not require calibration after SLEEP is made inactive (high). When coming out of SLEEP, sampling can begin as soon as the oscillator starts (time will depend on the particular oscillator components) and the REFBUF capacitor is charged (which takes about 3 ms for the CS5101A, 50 ms for the CS5102A). To achieve minimum start-up time, use an external clock and leave the voltage reference powered-up. Connect a resistor (2 kΩ ) between pins 20 and 21 to keep the REFBUF capacitor charged. Conversion can then begin as soon as the A/D circuitry has stabi- lized and performed a track cycle. To retain calibration memory while SLEEP is ac- tive (low) V A+ and VD+ must be maintained at greater than 2.0V . V A- and VD- can be allowed to go to 0 volts. The voltages into V A- and VD- cannot just be "shut-off" as these pins cannot be allowed to float to potentials greater than AGND/DGND. If the supply voltages to V A- and VD- are removed, use a transistor switch to short these to the power supply ground while in SLEEP mode. Grounding and Power Supply Decoupling The CS5101A and CS5102A use the analog ground connection, AGND, only as a reference voltage. No dc power currents flow through the AGND connection, and it is completely inde- pendent of DGND. However, any noise riding on the AGND input relative to the system’s analog ground will induce conversion errors. Therefore, both the analog input and reference voltage should be referred to the AGND pin, which should be used as the entire system’s analog ground reference. The digital and analog supplies are isolated within the CS5101A and CS5102A and are pinned out separately to minimize coupling be- tween the analog and digital sections of the chip. All four supplies should be decoupled to their re- spective grounds using 0.1 µF ceramic capacitors. If significant low-frequency noise is present on the supplies, tantalum capacitors are recom- mended in parallel with the 0.1 µF capacitors. The positive digital power supply of the CS5101A and CS5102A must never exceed the positive analog supply by more than a diode drop or the CS5101A and CS5102A could experience permanent damage. If the two supplies are de- rived from separate sources, care must be taken that the analog supply comes up first at power- up. The system connection diagram (Figure 7) shows a decoupling scheme which allows the CS5101A and CS5102A to be powered from a single set of ± 5V rails. The positive digital sup- ply is derived from the analog supply through a 10 Ω resistor to avoid the analog supply dropping below the digital supply. If this scheme is util- ized, care must be taken to insure that any digital load currents (which flow through the 10 Ω resis- tors) do not cause the magnitude of digital supplies to drop below the analog supplies by more than 0.5 volts. Digital supplies must always remain above the minimum specification. CS5101A CS5102A

22 DS45F2

As with any high-precision A/D converter, the CS5101A and CS5102A require careful attention to grounding and layout arrangements. However, no unique layout issues must be addressed to properly apply the devices. The CDB5101A evaluation board is available for the CS5101A, and the CDB5102A evaluation board is available for the CS5102A. The availability of these boards avoids the need to design, build, and debug a high-precision PC board to initially characterize the part. Each board comes with a socketed CS5101A or CS5102A, and can be reconfigured to simulate any combination of sampling, calibra- tion, master clock, and analog input range conditions. CS5101A AND CS5102A PERFORMANCE Differential Nonlinearity The self-calibration scheme utilized in the CS5101A and CS5102A features a calibration resolution of 1/4 LSB, or 18-bits. This ideally yields DNL of ±1/4 LSB, with code widths rang- ing from 3/4 to 5/4 LSB’s. Traditional laser trimmed ADC’s have significant differential nonlinearities. Appearing as wide and narrow codes, DNL often causes entire sections of the transfer function to be missing. Although their affect is minor on S/(N+D) with high ampli- tude signals, DNL errors dominate performance with low-level signals. For instance, a signal 80 dB below full-scale will slew past only 6 or 7 codes. Half of those codes could be missing with a conventional 16-bit ADC which achieves only 14-bit DNL. The most common source of DNL errors in con- ventional ADC’s is bit weight errors. These can arise due to accuracy limitations in factory trim stations, thermal or physical stresses after calibra- tion, and/or drifts due to aging or temperature variations in the field. Bit-weight errors have a drastic effect on a converter’s ac performance. They can be analyzed as step functions superim- posed on the input signal. Since bits (and their errors) switch in and out throughout the transfer curve, their effect is signal dependent. That is, harmonic and intermodulation distortion, as well as noise, can vary with different input conditions. Differential nonlinearities in successive-approxi- mation ADC’s also arise due to dynamic errors in the comparator. Such errors can dominate if the converter’s throughput/sampling rate is too high. The comparator will not be allowed sufficient time to settle during each bit decision in the suc- cessive-approximation algorithm. The worst-case codes for dynamic errors are the major transitions (1/2 FS; 1/4, 3/4 FS; etc.). Since DNL effects are most critical with low-level signals, the codes around mid-scale (1/2 FS) are most important. Yet those codes are worst-case for dynamic DNL errors! With all linearity calibration performed on-chip to 18-bits, the CS5101A and CS5102A maintain accurate bit weights. DNL errors are dominated by residual calibration errors of ±1/4 LSB rather than dynamic errors in the comparator. Further- more, all DNL effects on S/(N+D) are buried by white broadband noise. (See Figures 17 and 19). Figure 11 illustrates the DNL histogram plot of a typical CS5101A at 25°C. Figure 12 illustrates the DNL of the CS5101A at 138°C ambient after calibration at 25°C ambient. Figures 13 and 14 illustrate the DNL of the CS5102A at 25°C and 138°C ambient, respectively. A histogram test is a statistical method of deriving an A/D converter’s differential nonlinearity. A ramp is input to the A/D and a large number of samples are taken to insure a high confidence level in the test’s result. The number of occurrences for each code is monitored and stored. A perfect A/D converter would have all codes of equal size and therefore equal numbers of occurrences. In the histogram test a code with the average number of occur- rences will be considered ideal (DNL = 0). A CS5101A CS5102A DS45F2 23

Figure 14. CS5102A DNL Plot; Ambient Temperature at 138°C Figure 13. CS5102A DNL Plot; Ambient Temperature at 25°C Figure 12. CS5101A DNL Plot; Ambient Temperature at 138°C Figure 11. CS5101A DNL Plot; Ambient Temperature at 25°C

24 DS45F2

captured and processed. The FFT algorithm ana- lyzes the spectral content of the digital waveform and distributes its energy among 512 "frequency bins." Assuming an ideal sinewave, distribution of energy in bins outside of the fundamental and dc can only be due to quantization effects and errors in the CS5101A and CS5102A. If sampling is not synchronized to the input sine- wave, it is highly unlikely that the time record will contain an integer number of periods of the input signal. However, the FFT assumes that the signal is periodic, and will calculate the spectrum of a signal that appears to have large discontinui- ties, thereby yielding a severely distorted spectrum. To avoid this problem, the time record is multiplied by a window function prior to per- forming the FFT. The window function smoothly forces the endpoints of the time record to zero, thereby removing the discontinuities. The effect of the window in the frequency-domain is to con- volute the spectrum of the window with that of the actual input. The quality of the window used for harmonic analysis is typically judged by its highest side- lobe level. A five term window is used in FFT testing of the CS5101A and CS5102A. This win- dowing algorithm attenuates the side-lobes to below the noise floor. Artifacts of windowing are discarded from the signal-to-noise calculation us- ing the assumption that quantization noise is white. Averaging the FFT results from ten time records filters the spectral variability that can arise from capturing finite time records without disturbing the total energy outside the fundamen- tal. All harmonics are visible in the plots. For more information on FFT’s and windowing refer to: F.J. HARRIS, "On the use of windows for harmonic analysis with the Discrete Fourier Transform", Proc. IEEE, V ol. 66, No. 1, Jan 1978, pp.51-83. This is available on request from Crystal Semiconductor. As illustrated in Figure 17, the CS5101A typi- cally provides about 92 dB S/(N+D) and 0.001% THD at 25°C. Figure 18 illustrates only minor degradation in performance when the am- bient temperature is raised to 138°C. Figure 19 and 20 illustrate that the CS5102A typically yields >92 dB S/(N+D) and 0.001% THD even with a large change in ambient temperature. Un- like conventional successive-approximation ADC’s, the signal-to-noise and dynamic range of the CS5101A and CS5102A are not limited by differential nonlinearities (DNL) caused by cali- bration errors. Rather, the dominant noise source is broadband thermal noise which aliases into the baseband. This white broadband noise also ap- pears as an idle channel noise of 1/2 LSB (rms). Sampling Distortion Like most discrete sample/hold amplifier designs, the inherent sample/hold of the CS5101A and CS5102A exhibits a frequency-dependent distor- tion due to nonideal sampling of the analog input voltage. The calibrated capacitor array used dur- ing conversions is also used to track and hold the analog input signal. The conversion is not per- formed on the analog input voltage per se, but is actually performed on the charge trapped on the capacitor array at the moment the HOLD com- mand is given. The charge on the array ideally assumes a linear relationship to the analog input voltage. Any deviation from this linear relation- ship will result in conversion errors even if the conversion process proceeds flawlessly. At dc, the DAC capacitor array’s voltage coeffi- cient dictates the converter’s linearity. This variation in capacitance with respect to applied signal voltage yields a nonlinear relationship be- tween the charge on the array and the analog input voltage and places a bow or wave in the transfer function. This is the dominant source of distortion at low input frequencies (Fig- ures 17,18,19, and 20). The ideal relationship between the charge on the array and the input voltage can also be distorted CS5101A CS5102A

26 DS45F2

voltage dependent variation in the aperture delay. Figure 21. 5101A Histogram Plot of 8192 Conversion Figure 22. 5102A Histogram Plot of 8192 Conversion

28 DS45F2

errors due to aperture jitter. chip self-calibration and an "auto-zero" process. amplifiers is augmented by an auto-zero process. rejection improves by 6 dB in the unipolar mode. (74HC595) and to DSP serial ports. Table 3 summarizes all the improvements. Figure 23. Power Supply Rejection

Interface signal (SSH/SDL). latch (SDL) signal. Table 3. CS5101A/CS5102A Improvements over CS5101/CS5102 Call Applications Engineering. Call Applications Engineering.

30 DS45F2

NEGATIVE DIGITAL POWER VD- SLEEP SLEEP (LOW POWER) MODE RESET & INITIATE CALIBRATION RST SCKMOD SERIAL CLOCK MODE SELECT MASTER CLOCK INPUT CLKIN TEST TEST CRYSTAL OUTPUT XOUT VA+ POSITIVE ANALOG POWER STANDBY (CALIBRATING) STBY AIN2 CHANNEL 2 ANALOG INPUT DIGITAL GROUND DGND VA- NEGATIVE ANALOG POWER POSITIVE DIGITAL POWER VD+ AGND ANALOG GROUND TRACKING CHANNEL 1 TRK1 REFBUF REFERENCE BUFFER TRACKING CHANNEL 2 TRK2 VREF VOLTAGE REFERENCE COARSE/FINE CHARGE CONTROL CRS /FIN AIN1 CHANNEL 1 ANALOG INPUT SIMULTANEOUS S/H / SERIAL DATA LATCH SSH/SDL OUTMOD OUTPUT MODE SELECT HOLD & CONVERT HOLD BP /UP BIPOLAR/UNIPOLAR SELECT INPUT CHANNEL SELECT CH1 /2C O D E BINARY/2’s COMPLEMENT SELECT SERIAL DATA CLOCK SCLK SDATA SERIAL DATA OUTPUT CS5102A CS5101A or VD- RST SLEEP CLKIN SCKMOD XOUT TEST STBY VA+ DGND AIN2 VD+ VA- TRK1 AGND TRK2 REFBUF CRS/ FIN VREF SSH/SDL AIN1 HOLD OUTMOD CH1 /2 BP/ UP SCLK CODE SDATA top view 2532 7242 6 281 12 14 16 1813 15 17 CS5102A or CS5101A CS5101A CS5102A DS45F2 31

VD+ - Positive Digital Power, PIN 7. Positive digital power supply. Nominally +5 volts. VD- - Negative Digital Power, PIN 1. Negative digital power supply. Nominally -5 volts. DGND - Digital Ground, PIN 6. Digital ground [reference]. V A+ - Positive Analog Power, PIN 25. Positive analog power supply. Nominally +5 volts. V A- - Negative Analog Power, PIN 23. Negative analog power supply. Nominally -5 volts. AGND - Analog Ground, PIN 22. Analog ground reference. Oscillator CLKIN - Clock Input, PIN 3. All conversions and calibrations are timed from a master clock which can be externally supplied by driving CLKIN [this input TTL-compatible, CMOS recommended]. XOUT - Crystal Output, PIN 4. The master clock can be generated by tying a crystal across the CLKIN and XOUT pins. If an external clock is used, XOUT must be left floating. Digital Inputs HOLD - Hold, PIN 12. A falling transition on this pin sets the CS5101A or CS5102A to the hold state and initiates a conversion. This input must remain low for at least 1/tclk + 20 ns. When operating in Free Run Mode, HOLD is disabled, and should be tied to DGND or VD+. CRS/ FIN - Coarse Charge/Fine Charge Control, PIN 10. When brought high during acquisition time, CRS/FIN forces the CS5101A or CS5102A into coarse charge state. This engages the internal buffer amplifier to track the analog input and charges the capacitor array much faster, thereby allowing the CS5101A or CS5102A to track high slewing signals. In order to get an accurate sample, the last coarse charge period before initiating a conversion (bringing HOLD low) must be longer than 0.75 µs (CS5101A) or 3.75 µs (CS5102A). Similarly, the fine charge period immediately prior to conversion must be at least 1.125 µs (CS5101A) or 5.625 µs (CS5102A). The CRS/FIN pin must be low during conversion time. For normal operation, CRS/FIN should be tied low, in which case the CS5101A or CS5102A will automatically enter coarse charge for 6 clock cycles immediately after the end of conversion. CS5101A CS5102A

32 DS45F2

CH1/ 2 - Left/Right Input Channel Select, PIN 13. Status at the end of a conversion cycle determines which analog input channel will be acquired for the next conversion cycle. When in Free Run Mode, CH1/2 is an output, and will indicate which channel is being sampled during the current acquisition phase. SLEEP - Sleep, PIN 28. When brought low causes the CS5101A or CS5102A to enter a power-down state. All calibration coefficients are retained in memory, so no recalibration is needed after returning to the normal operating mode. If using the internal crystal oscillator, time must be allowed after SLEEP returns high for the crystal oscillator to stabilize. SLEEP should be tied high for normal operation. CODE - 2’s Complement/Binary Coding Select, PIN 16. Determines whether output data appears in 2’s complement or binary format. If high, 2’s complement; if low, binary. BP/UP - Bipolar/Unipolar Input Range Select, PIN 17. When low, the CS5101A or CS5102A accepts a unipolar input range from AGND to VREF. When high, the CS5101A or CS5102A accepts bipolar inputs from -VREF to +VREF. SCKMOD - Serial Clock Mode Select, PIN 27. When high, the SCLK pin is an input; when low, it is an output. Used in conjunction with OUTMOD to select one of 4 output modes described in Table 2. OUTMOD - Output Mode Select, PIN 18. The status of SCKMOD and OUTMOD determine which of four output modes is utilized. The four modes are described in Table 2. SCLK - Serial Clock, PIN 14. Serial data changes status on a falling edge of this input, and is valid on a rising edge. When SCKMOD is high SCLK acts as an input. When SCKMOD is low the CS5101A or CS5102A generates its own serial clock at one-fourth the master clock frequency and SCLK is an output. RST - Reset, PIN 2. When taken low, all internal digital logic is reset. Upon returning high, a full calibration sequence is initiated which takes 11,528,160 CLKIN cycles (CS5101A) or 2,882,040 CLKIN cycles (CS5102A) to complete. During calibration, the HOLD input will be ignored. The CS5101A or CS5102A must be reset at power-up for calibration, however; calibration is maintained during SLEEP mode, and need not be repeated when resuming normal operation. Analog Inputs AIN1, AIN2 - Channel 1 and 2 Analog Inputs, PINS 19 and 24. Analog input connections for the left and right input channels. VREF - Voltage Reference, PIN 20. The analog reference voltage which sets the analog input range. In unipolar mode VREF sets full-scale; in bipolar mode its magnitude sets both positive and negative full-scale. CS5101A CS5102A DS45F2 33

STBY - Standby (Calibrating), PIN 5. Indicates calibration status after reset. Remains low throughout the calibration sequence and returns high upon completion. SDATA - Serial Output, PIN 15. Presents each output data bit on a falling edge of SCLK. Data is valid to be latched on the rising edge of SCLK. SSH/SDL - Simultaneous Sample/Hold / Serial Data Latch, PIN 11. Used to control an external sample/hold amplifier to achieve simultaneous sampling between channels. In FRN and SSC modes (SCLK is an output), this signal provides a convenient latch signal which forms the 16 data bits. This can be used to control external serial to parallel latches, or to control the serial port in a DSP . TRK1, TRK2 - Tracking Channel 1, Tracking Channel 2, PINS 8 and 9. Falls low at the end of a conversion cycle, indicating the acquisition phase for the corresponding channel. The TRK1 or TRK2 pin will return high at the beginning of conversion for that channel. Analog Outputs REFBUF - Reference Buffer Output, PIN 21. Reference buffer output. A 0.1 µF ceramic capacitor must be tied between this pin and V A-. Miscellaneous TEST - Test, PIN 26. Allows access to the CS5101A’s and the CS5102A ’s test functions which are reserved for factory use. Must be tied to VD+. CS5101A CS5102A

34 DS45F2

The deviation of a code from a straight line passing through the endpoints of the transfer function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 1/2 LSB below the first code transition and "full-scale" is a point 1/2 LSB beyond the code transition to all ones. The deviation is measured from the middle of each particular code. Units in % Full-Scale. Differential Linearity Minimum resolution for which no missing codes is guaranteed. Units in bits. Full Scale Error The deviation of the last code transition from the ideal (VREF-3/2 LSB’s). Units in LSB’s. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above AGND) when in unipolar mode (BP/UP low). Units in LSB’s. Bipolar Offset AGND) when in bipolar mode (BP/UP high). Units in LSB’s. Bipolar Negative Full-Scale Error The deviation of the first code transition from the ideal when in bipolar mode (BP/UP high). The ideal is defined as lying on a straight line which passes through the final and mid-scale code transitions. Units in LSB’s. Signal to Peak Harmonic or Noise The ratio of the rms value of the signal to the rms value of the next largest spectral component below the Nyquist rate (excepting dc). This component is often an aliased harmonic when the signal frequency is a significant proportion of the sampling rate. Expressed in decibels. Total Harmonic Distortion The ratio of the rms sum of all harmonics to the rms value of the signal. Units in percent. Signal-to-(Noise + Distortion) The ratio of the rms value of the signal to the rms sum of all other spectral components below the Nyquist rate (excepting dc), including distortion components. Expressed in decibels. Aperture Time The time required after the hold command for the sampling switch to open fully. Effectively a sampling delay which can be nulled by advancing the sampling signal. Units in nanoseconds. Aperture Jitter The range of variation in the aperture time. Effectively the "sampling window" which ultimately dic- tates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds. CS5101A CS5102A DS45F2 35

Model Conversion Time Throughput Linearity Temperature Package CS5101A-JP8 8.13 µs 100 kHz 0.003% 0 to 70 °C 28-Pin Plastic DIP CS5101A-KP8 8.13 µs 100 kHz 0.002% 0 to 70 °C 28-Pin Plastic DIP CS5101A-JP16 16.25 µs 50 kHz 0.003% 0 to 70 °C 28-Pin Plastic DIP CS5101A-JL8 8.13 µs 100 kHz 0.003% 0 to 70 °C 28-Pin PLCC CS5101A-KL8 8.13 µs 100 kHz 0.002% 0 to 70 °C 28-Pin PLCC CS5101A-JL16 16.25 µs 50 kHz 0.003% 0 to 70 °C 28-Pin PLCC CS5101A-AP8 8.13 µs 100 kHz 0.003% -40 to 85 °C 28-Pin Plastic DIP CS5101A-BP8 8.13 µs 100 kHz 0.002% -40 to 85 °C 28-Pin Plastic DIP CS5101A-AL8 8.13 µs 100 kHz 0.003% -40 to 85 °C 28-Pin PLCC CS5101A-BL8 8.13 µs 100 kHz 0.002% -40 to 85 °C 28-Pin PLCC Model Conversion Time Throughput Linearity Temperature Package CS5102A-JP 40 µs 20 kHz 0.003% 0 to 70 °C 28-Pin Plastic DIP CS5102A-KP 40 µs 20 kHz 0.0015% 0 to 70 °C 28-Pin Plastic DIP CS5102A-JL 40 µs 20 kHz 0.003% 0 to 70 °C 28-Pin PLCC CS5102A-KL 40 µs 20 kHz 0.0015% 0 to 70 °C 28-Pin PLCC CS5102A-AP 40 µs 20 kHz 0.003% -40 to 85 °C 28-Pin Plastic DIP CS5102A-BP 40 µs 20 kHz 0.0015% -40 to 85 °C 28-Pin Plastic DIP CS5102A-AL 40 µs 20 kHz 0.003% -40 to 85 °C 28-Pin PLCC CS5102A-BL 40 µs 20 kHz 0.0015% -40 to 85 °C 28-Pin PLCC CS5101A CS5102A

36 DS45F2

Apr ’00 : 28 PIN PLASTIC (PDIP) (600 MIL) PACKAGE DRAWING INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX JEDEC # : MS-020 Controling Dimension is Inches

28 PIN PLASTIC (PDIP) (600 MIL) PACKAGE DRAWING

D SEATING PLANE e b A LA1 TOP VIEW BOTTOM VIEW SIDE VIEW eA c E eC eB PKPD028A01

Apr ’00 : 28L PLCC PACKAGE DRAWING INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX JEDEC # : MS-047 AA-AF Controlling Dimension is Inches 28L PLCC PACKAGE DRAWING D E1 E D2/E2 B e A PKPL028A01

Apr ’00 : 28 PIN LCC PACKAGE DRAWING PRELIMINARY DRAFT WAITING ON VERIFICATION INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX Controlling Dimension is Inches

28 PIN LCC PACKAGE DRAWING

L b e TERMINAL 1 BOTTOM VIEW A E D TOP VIEW PRELIMINARY DRAFT WAITING ON VERIFICATION PKLC028A01