CS5014

CS5016 CIRRUS | Alldatasheet

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Technical content

Features

• • Monolithic CMOS A/D Converters Microprocessor Compatible Parallel and Serial Output Inherent Track/Hold Input
• • True 12, 14 and 16-Bit Precision
• • Conversion Times: CS5016 16.25 µs CS5014 14.25 µs CS5012A 7.20 µs
• • Self Calibration Maintains Accuracy Over Time and Temperature
• • Low Power Dissipation: 150 mW
• • Low Distortion General Description The CS5012A/14/16 are 12, 14 and 16-bit monolithic analog to digital converters with conversion times of 7.2µs, 14.25µs and 16.25µs. Unique self-calibration cir- cuitry insures excellent linearity and differential non- linearity, with no missing codes. Offset and full scale errors are kept within 1/2 LSB (CS5012A/14) and 1 LSB (CS5016), eliminating the need for calibration. Unipolar and bipolar input ranges are digitally select- able. The pin compatible CS5012A/14/16 consist of a DAC, conversion and calibration microcontroller, oscillator, comparator, microprocessor compatible 3-state I/O, and calibration circuitry. The input track-and-hold, in- herent to the devices’ sampling architecture, acquires the input signal after each conversion using a fast slewing on-chip buffer amplifier. This allows throughput rates up to 100 kHz (CS5012A), 56 kHz (CS5014) and 50 kHz (CS5016). An evaluation board (CDB5012/14/16) is available which allows fast evaluation of ADC performance. ORDERING INFORMATION: Pages 2-45, 2-46, & 2-47 MAR ’95 DS14F6 2-7 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445 7222 FAX: (512) 445 7581 16, 14 & 12-Bit, Self-Calibrating A/D Converters Semiconductor Corporation CS5016 CS5014 CS5012A D10 D11 D12 D13 D14 D15 (MSB) D4 (LSB) CS5012A6 D2 (LSB) CS5014 D0 (LSB) CS5016 SCLKEOT EOC SDATA 37 38 39 40 CLKIN CLOCK GENERATOR INTRLV RST 3221 RD HOLD BW 3324 CAL CS BP/UP REFBUF AGND VREF 28 AIN 26 CHARGE REDISTRIBUTION DAC COMPARATOR VA+ VA- VD+ VD- DGND TST 25 30 11 36 10 31 CONTROL CALIBRATION MEMORY MICROCONTROLLER STATUS REGISTER Copyright  Crystal Semiconductor Corporation 1995 (All Rights Reserved)

CS5012A ANALOG CHARACTERISTICS (TA = TMIN to TMAX ; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 2.5V to 4.5V; fclk = 6.4 MHz for -7, 4 MHz for -12; Analog Source Impedance = 200Ω ) CS5012A-K CS5012A-B CS5012-T Parameter* Min Typ Max Min Typ Max Min Typ Max Units Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C Accuracy Linearity Error (Note 1) Drift (Note 2) ±1/4 ±1/8 ±1/2 ±1/4 ±1/8 ±1/2 ±1/4 ±1/8 ±1/2 LSB 12 ΔLSB 12 Differential Linearity (Note 1) Drift (Note 2) ±1/4 ±1/32 ±1/2 ±1/4 ±1/32 ±1/2 ±1/4 ±1/32 ±1/2 LSB 12 ΔLSB 12 Full Scale Error (Note 1) Drift (Note 2) ±1/4 ±1/16 ±1/2 ±1/4 ±1/16 ±1/2 ±1/4 ±1/8 ±1/2 LSB 12 ΔLSB 12 Unipolar Offset (Note 1) Drift (Note 2) ±1/4 ±1/16 ±1/2 ±1/4 ±1/16 ±1/2 ±1/4 ±1/16 ±1/2 LSB 12 ΔLSB 12 Bipolar Offset (Note 1) Drift (Note 2) ±1/4 ±1/16 ±1/2 ±1/4 ±1/16 ±1/2 ±1/4 ±1/16 ±1/2 LSB 12 ΔLSB 12 Bipolar Negative Full-Scale Error(Note 1) Drift (Note 2) ±1/4 ±1/16 ±1/2 ±1/4 ±1/16 ±1/2 ±1/4 ±1/16 ±1/2 LSB 12 ΔLSB 12 Total Unadjusted Error (Note 1) Drift (Note 2) ±1/4 ±1/4 ±1/4 ±1/4 ±1/4 ±1/4 LSB 12 ΔLSB 12 Dynamic Performance (Bipolar Mode) Peak Harmonic or (Note 1) Spurious Noise Full Scale, 1 kHz Input Full Scale, 12 kHz Input dB dB Total Harmonic Distortion 0.008 0.008 0.008 % Signal-to-Noise Ratio (Note 1) 1 kHz, 0 dB Input 1 kHz, -60 dB Input 72 73 72 73 72 73 dB dB Noise (Note 3) Unipolar Mode Bipolar Mode µV rms µVrms Notes: 1. Applies after calibration at any temperature within the specified temperature range. 2. Total drift over specified temperature range since calibration at power-up at 25 °C 3. Wideband noise aliased into the baseband. Referred to the input. * Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet). Specifications are subject to change without notice. 2-8 DS14F6

CS5012A ANALOG CHARACTERISTICS (continued) CS5012A-K CS5012A-B CS5012-T Parameter* Min Typ Max Min Typ Max Min Typ Max Units Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C Analog Input Aperture Time 25 25 25 ns Aperture Jitter 100 100 100 ps Input Capacitance (Note 4) Unipolar Mode CS5012 CS5012A Bipolar Mode CS5012 CS5012A 275 103 165 375 137 220 275 103 165 375 137 220 275 103 165 375 137 220 pF pF pF pF Conversion & Throughput Conversion Time -7 (Notes 5 and 6) -12 7.2 12.25 7.2 12.25 12.25 µs µs Acquisition Time -7 (Note 6) -12 2.5 3.0 2.8 3.75 2.5 3.0 2.8 3.75 3.0 3.75 µs µs Throughput -7 (Note 6) -12 100 62.5 100 62.5 62.5 kHz kHz Power Supplies DC Power Supply Currents (Note 7) IA+ IA- (CS5012) I D + (CS5012A) I D + ID - -12 -19 7.5 -12 -19 7.5 -12 -19 mA mA mA mA mA Power Dissipation (Note 7) 150 250 150 250 150 250 mW Power Supply Rejection (Note 8) Positive Supplies Negative Supplies dB dB Notes: 4. Applies only in track mode. When converting or calibrating, input capacitance will not exceed 15 pF. 5. Measured from falling transition on HOLD to falling transition on EOC. 6. Conversion, acquisition, and throughput times depend on CLKIN, sampling, and calibration conditions. The numbers shown assume sampling and conversion is synchronized with the CS5012A/14/16 ’s conversion clock, interleave calibrate is disabled, and operation is from the full-rated, external clock. Refer to the section Conversion Time/Throughput for a detailed discussion of conversion timing. 7. All outputs unloaded. All inputs CMOS levels. 8. With 300 mV p-p, 1 kHz ripple applied to each analog supply separately in bipolar mode. Rejection improves by 6 dB in the unipolar mode to 90 dB. Figure 13 shows a plot of typical power supply rejection versus frequency. CS5012A DS14F6 2-9

CS5014 ANALOG CHARACTERISTICS (TA = TMIN to TMAX ; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; CLKIN = 4 MHz for -14, 2 MHz for -28; Analog Source Impedance = 200Ω ) CS5014-K CS5014-B CS5014-S, T Parameter* Min Typ Max Min Typ Max Min Typ Max Units Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C Accuracy Linearity Error K, B, T (Note 1) S Drift (Note 2) ±1/4 ±1/8 ±1/2 ±1/4 ±1/8 ±1/2 ±1/4 ±1/2 ±1/8 ±1/2 ±1.5 LSB 14 LSB 14 ΔLSB 14 Differential Linearity (Note 1) Drift (Note 2) ±1/4 ±1/32 ±1/2 ±1/4 ±1/32 ±1/2 ±1/4 ±1/32 ±1/2 LSB 14 ΔLSB 14 Full Scale Error (Note 1) Drift (Note 2) ±1/2 ±1/4 ±1 ±1/2 ±1/4 ±1 ±1/2 ±1/2 ±1 LSB 14 ΔLSB 14 Unipolar Offset K, B, T (Note 1) S Drift (Note 2) ±1/4 ±1/4 ±3/4 ±1/4 ±1/4 ±3/4 ±1/4 ±1/2 ±3/4 LSB 14 LSB 14 ΔLSB 14 Bipolar Offset K, B, T (Note 1) S Drift (Note 2) ±1/4 ±1/4 ±3/4 ±1/4 ±1/2 ±3/4 ±1/4 ±1/2 ±3/4 LSB 14 LSB 14 ΔLSB 14 Bipolar Negative Full-Scale Error(Note 1) K, B, T S Drift (Note 2) ±1/2 ±1/4 ±1 ±1/2 ±1/4 ±1 ±1/2 ±1/2 ±1.5 LSB LSB 14 ΔLSB 14 Total Unadjusted Error (Note 1) Drift (Note 2) ±1/2 LSB 14 ΔLSB 14 Dynamic Performance (Bipolar Mode) Peak Harmonic or (Note 1) Spurious Noise Full Scale, 1 kHz Input K, B, T S Full Scale, 12 kHz Input K, B, T S dB dB dB dB Total Harmonic Distortion 0.003 0.003 0.003 % Signal-to-Noise Ratio (Notes 1 and 9) 1 kHz, 0 dB Input K, B, T S 1 kHz, -60 dB Input 82 84 82 84 dB dB dB Noise (Note 3) Unipolar Mode Bipolar Mode µV rms µVrms Notes: 9. A detailed plot of S/(N+D) vs. input amplitude appears in Figure 26 for the CS5014 and Figure 28 for the CS5016. * Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet). Specifications are subject to change without notice. CS5014 2-10 DS14F6

CS5014 ANALOG CHARACTERISTICS (continued) CS5014-K CS5014-B CS5014-S, T Parameter* Min Typ Max Min Typ Max Min Typ Max Units Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C Analog Input Aperture Time 25 25 25 ns Aperture Jitter 100 100 100 ps Input Capacitance (Note 4) Unipolar Mode Bipolar Mode 275 165 375 220 275 165 375 220 275 165 375 220 pF pF Conversion & Throughput Conversion Time -14 (Notes 5 and 6) -28 14.25 28.5 14.25 28.5 14.25 28.5 µs µs Acquisition Time -14 (Note 6) -28 3.0 4.5 3.75 5.25 3.0 4.5 3.75 5.25 3.0 4.5 3.75 5.25 µs µs Throughput -14 (Note 6) -28 55.6 27.7 55.6 27.7 55.6 27.7 kHz kHz Power Supplies DC Power Supply Currents (Note 7) IA+ IA- ID + ID - -19 -19 -19 mA mA mA mA Power Dissipation (Note 7) 120 250 120 250 120 250 mW Power Supply Rejection (Note 8) Positive Supplies Negative Supplies dB dB DS14F6 2-11

CS5016 ANALOG CHARACTERISTICS (TA = TMIN to TMAX ; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; CLKIN = 4 MHz for -16, 2 MHz for -32; Analog Source Impedance = 200Ω ; Synchronous Sampling.) CS5016-J, K CS5016-A, B CS5016-S, T Parameter* Min Typ Max Min Typ Max Min Typ Max Units Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C Accuracy Linearity Error J, A, S (Note 1) K, B, T Drift (Note 2) 0.002 0.001 ±1/4 0.003 0.0015 0.002 0.001 ±1/4 0.003 0.0015 0.002 0.001 ±1/4 0.0076 0.0015 %FS %FS ΔLSB 16 Differential Linearity (Note 10) 16 16 16 Bits Full Scale Error J, A, S (Note 1) K, B, T Drift (Note 2) LSB 16 LSB 16 ΔLSB 16 Unipolar Offset J, A, S (Note 1) K, B, T Drift (Note 2) ±3/2 LSB 16 LSB 16 ΔLSB 16 Bipolar Offset J, A, S (Note 1) K, B, T Drift (Note 2) ±3/2 LSB 16 LSB 16 ΔLSB 16 Bipolar Negative Full-Scale Error(Note 1) J, A, S K, B, T Drift (Note 2) LSB LSB 16 ΔLSB 16 Dynamic Performance (Bipolar Mode) Peak Harmonic or (Note 1) Spurious Noise Full Scale, 1 kHz Input J, A, S K, B, T Full Scale, 12 kHz Input J, A, S K, B, T 100 100 104 100 100 104 100 100 104 dB dB dB dB Total Harmonic Distortion J, A, S Full Scale, 1 kHz Input K, B, T 0.002 0.001 0.002 0.001 0.002 0.001 Signal-to-Noise Ratio (Notes 1 and 9) 1 kHz, 0 dB Input J, A, S K, B, T 1 kHz, -60 dB Input J, A, S K, B, T dB dB dB dB Noise (Note 3) Unipolar Mode Bipolar Mode µV rms µVrms Notes: 10. Minimum resolution for which no missing codes is guaranteed * Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet). Specifications are subject to change without notice. 2-12 DS14F6

CS5016 ANALOG CHARACTERISTICS (continued) CS5016-J, K CS5016-A, B CS5016-S, T Parameter* Min Typ Max Min Typ Max Min Typ Max Units Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C Analog Input Aperture Time 25 25 25 ns Aperture Jitter 100 100 100 ps Input Capacitance (Note 4) Unipolar Mode Bipolar Mode 275 165 375 220 275 165 375 220 275 165 375 220 pF pF Conversion & Throughput Conversion Time -16 (Notes 5 and 6) -32 16.25 32.5 16.25 32.5 16.25 32.5 µs µs Acquisition Time -16 (Note 6) -32 3.0 4.5 3.75 5.25 3.0 4.5 3.75 5.25 3.0 4.5 3.75 5.25 µs µs Throughput -16 (Note 6) -32 26.5 26.5 26.5 kHz kHz Power Supplies DC Power Supply Currents (Note 7) IA+ IA- ID + ID - -19 -19 -19 mA mA mA mA Power Dissipation (Note 7) 120 250 120 250 120 250 mW Power Supply Rejection (Note 8) Positive Supplies Negative Supplies dB dB DS14F6 2-13

SWITCHING CHARACTERISTICS (TA = TMIN to TMAX ; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF, BW = VD+) Parameter Symbol Min Typ Max Units CS5012A CLKIN Frequency: Internally Generated: Externally Supplied: -7 -12 f CLK 1.75 100 kHz 100 kHz 6.4 4.0 MHz MHz MHz CS5014/5016 CLKIN Frequency: Internally Generated: -14, -16 -28, -32 Externally Supplied: -14, -16 -28, -32 f CLK 1.75 100 kHz 100 kHz MHz MHz MHz MHz CLKIN Duty Cycle 40 - 60 % Rise Times: Any Digital Input Any Digital Output trise - 1.0 µs ns Fall Times: Any Digital Input Any Digital Output tfall - 1.0 µs ns HOLD Pulse Width t hpw 1/fCLK +50 - t c ns Conversion Time: CS5012A CS5014 CS5016 t c 49/fCLK +50 57/fCLK 65/fCLK 53/f CLK +235 61/fCLK +235 69/fCLK +235 ns ns ns Data Delay Time t dd - 40 100 ns EOC Pulse Width (Note 11) t epw 4/fCLK -20 - - ns Set Up Times: CAL, INTRLV to CS Low A0 to CS and RD Low tcs tas ns ns Hold Times: CS or RD High to A0 Invalid CS High to CAL, INTRLV Invalid tah tch ns ns Access Times: CS Low to Data Valid A, B, J, K S, T RD Low to Data Valid A, B, J, K S, T tca tra 115 120 150 120 150 ns ns ns ns Output Float Delay: K, B CS or RD High to Output Hi-Z T tfd - 110 140 ns ns Serial Clock Pulse Width Low Pulse Width High tpwl tpwh 2/fCLK 2/fCLK ns ns Set Up Times: SDATA to SCLK Rising t ss 2/fCLK -50 2/f CLK -n s Hold Times: SCLK Rising to SDATA t sh 2/fCLK -100 2/f CLK -n s Notes: 11.EOC remains low 4 CLKIN cycles if CS and RD are held low. Otherwise, it returns high within 4 CLKIN cycles from the start of a data read operation or a conversion cycle. CS5012A, CS5014, CS5016 2-14 DS14F6

90% 10% tfallriset 90% 10% Hi-Z Hi-Z chttcs tah tfd tas tra tca HOLD EOC Output Data thpw tc LAST CONVERSION DATA VALID tdd NEW DATA VALID tepw D0-D15 CS RD CAL, INTRLV SDATA tss tsh SCLK tpwl tpwh Rise and Fall Times Conversion Timing Serial Output Timing Read and Calibration Control Timing CS5012A, CS5014, CS5016 DS14F6 2-15

CS5012A, CS5014, CS5016 DIGITAL CHARACTERISTICS (TA = TMIN to TMAX ; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%) Parameter Symbol Min Typ Max Units High-Level Input Voltage V IH 2.0 - - V Low-Level Input Voltage V IL -- 0 . 8 V High-Level Output Voltage (Note 12) V OH (VD+) - 1.0V - - V Low-Level Output Voltage I out = 1.6mA V OL -- 0 . 4 V Input Leakage Current I in -- 1 0 µA 3-State Leakage Current I OZ -- ±10 µA Digital Output Pin Capacitance C out -9- p F Notes: 12. Iout = -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ Iout = -40 µA). RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 13) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 VA+ -5.5 5.5 -5.5 V V V V Analog Reference Voltage VREF 2.5 4.5 (VA+) - 0.5 V Analog Input Voltage: (Note 14) Unipolar Bipolar V AIN VAIN AGND -VREF VREF VREF V V Notes: 13. All voltages with respect to ground. 14. The CS5012A/14/16 can accept input voltages up to the analog supplies (VA+ and VA-). It will output all 1’s for inputs above VREF and all 0’s for inputs below AGND in unipolar mode and -VREF in bipolar mode. ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with repect to ground.) WARNING: Operation at or beyond these limits may reult in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Min Max Units DC Power Supplies: Positive Digital (Note 15) Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- -0.3 0.3 -0.3 0.3 6.0 -6.0 6.0 -6.0 V V V V Input Current, Any Pin Except Supplies (Note 16) I in - ±10 mA Analog Input Voltage (AIN and VREF pins) V INA (VA-) - 0.3 (VA+) + 0.3 V Digital Input Voltage V IND -0.3 (VA+) + 0.3 V Ambient Operating Temperature T A -55 125 °C Storage Temperature T stg -65 150 °C Notes: 15. In addition, VD+ should not be greater than (VA+) + 0.3V. 16. Transient currents of up to 100 mA will not cause SCR latch-up. 2-16 DS14F6

15 CLKIN cycles after EOC indicating the ana-

Table 1. Conversion and Throughput Times (tclk = Master Clock Period)

The reset calibration always works perfectly, and should be used instead of burst mode. The CS5012’s and CS5012A/14/16’s very low drift over temperature means that, under most circum- stances, calibration will only need to be performed at power-up, using reset. The CS5012A/14/16 feature a background cali- bration mode called "interleave." Interleave appends a single calibration experiment to each conversion cycle and thus requires no dead time for calibration. The CS5012A/14/16 gathers data between conversions and will adjust its transfer function once it completes the entire sequence of experiments (one calibration cycle per 2,014 con- versions in the CS5012A and one calibration per 72,051 conversions in the CS5012, CS5014 and CS5016). Initiated by bringing both the INTRLV input and CS low (or hard-wiring INTRLV low), interleave extends the CS5012A/14/16’s effective conversion time by 20 CLKIN cycles. Other than reduced throughput, interleave is totally transpar- ent to the user. Interleave calibration should not be used intermittently. The fact that the CS5012A/14/16 offer several calibration modes is not to imply that the devices need to be recalibrated often. The devices are very stable in the presence of large temperature changes. Tests have indicated that after using a single reset calibration at 25 °C most devices ex- hibit very little change in offset or gain when exposed to temperatures from -55 to +125 °C. The data indicated 30 ppm as the typical worst case total change in offset or gain over this tem- perature range. Differential linearity remained virtually unchanged. System error sources outside of the A/D converter, whether due to changes in temperature or to long-term aging, will generally dominate total system error. Microprocessor Interface The CS5012A/14/16 feature an intelligent micro- processor interface which offers detailed status information and allows software control of the self-calibration functions. Output data is available in either 8-bit or 16-bit formats for easy interfac- ing to industry-standard microprocessors. Strobing both CS and RD low enables the CS5012A/14/16’s 3-state output buffers with either output data or status information depending on the status of A0. An address bit can be con- nected to A0 as shown in Figure 4b thereby memory mapping the status register and output data. Conversion status can be polled in software by reading the status register ( CS and RD strobed low with A0 low), and masking status bits S0-S5 and S7 (by logically AND’ing the status word with 01000000) to determine the value of S6. Similarly, the software routine can determine calibration status using other status bits (see Ta- ble 2). Care must be taken not to read the status register (A0 low) while HOLD is low, or a soft- ware reset will result (see Reset above). Alternatively, the End-of-Convert (EOC) output can be used to generate an interrupt or drive a DMA controller to dump the output directly into memory after each conversion. The EOC pin falls as each conversion cycle is completed and data is valid at the output. It returns high within four CLKIN cycles of the first subsequent data read operation or after the start of a new conversion cycle. CS5012A, CS5014, CS5016 2-22 DS14F6

byte will appear on the next data read operation. converting will not introduce conversion errors. and returns high on the first subsequent read. D1 S1 RESERVED Reserved for factory use. indicates which byte will appear at the output next. the devices specified accuracy. D4 S4 RESERVED Reserved for factory use. D5 S5 TRACKING High when the device is tracking the input. D6 S6 CONVERTING High when the device is converting the held input. D7 S7 CALIBRATING High when the device is calibrating. Table 2. Status Pin Definitions Figure 7. CS5012A/14/16 Data Format

the data from the CS5012A/14/16 (See Figure 9). ease the demands placed on external circuitry. Figure 8. Microprocessor-Independent Connections

signal frequencies or their harmonics. exhibit extremely low output impedance at dc. ramic capacitor is recommended. Figure 9. Serial Output Timing

1. Timing delay td (relative to CLKIN) can vary between 135 ns to 235 ns over the military temperature range

is recognized on a rising edge of CLKIN/4.

(6 clock cycles) and 2.25 µs for fine-charging. to decrease source impedance at high frequencies. in unipolar mode and 0.5V/µs in bipolar mode. Figure 12. Pipelined MUX Input Channels

Analog Input Range/Coding Format The reference voltage directly defines the input voltage range in both the unipolar and bipolar configurations. In the unipolar configuration (BP/ UP low), the first code transition occurs

0.5 LSB above AGND, and the final code transi-

tion occurs 1.5 LSB’s below VREF. Coding is in straight binary format. In the bipolar configura- tion (BP/ UP high), the first code transition occurs

0.5 LSB above -VREF and the last transition oc-

curs 1.5 LSB’s below +VREF. Coding is in an offset-binary format. Positive full scale gives a digital output of all ones, and negative full scale gives a digital output of all zeros. The BP/ UP mode pin may be switched after cali- bration without having to recalibrate the converter. However, the BP/ UP mode should be changed during the previous conversion cycle, that is, between HOLD falling and EOC falling. If BP/UP is changed at any other time, one dummy conversion cycle must be allowed for proper acquisition of the input. Grounding and Power Supply Decoupling The CS5012A/14/16 use the analog ground con- nection, AGND, only as a reference voltage. No dc power currents flow through the AGND con- nection, and it is completely independent of DGND. However, any noise riding on the AGND input relative to the system’s analog ground will induce conversion errors. Therefore, both the ana- log input and reference voltage should be referred to the AGND pin, which should be used as the entire system’s analog ground reference point. The digital and analog supplies to the CS5012A/14/16 are pinned out separately to minimize coupling between the analog and digital sections of the chip. All four supplies should be decoupled to their respective grounds using 0.1 µF ceramic capacitors. If significant low-fre- quency noise is present on the supplies, 1 µF tantalum capacitors are recommended in parallel with the 0.1 µF capacitors. The positive digital power supply of the CS5012A/14/16 must never exceed the positive analog supply by more than a diode drop or the device could experience permanent damage. If the two supplies are derived from separate sources, care must be taken that the analog sup- ply comes up first at power-up. The system connection diagram in Figure 36 shows a decou- pling scheme which allows the CS5012A/14/16 to be powered from a single set of ± 5V rails. As with any high-precision A/D converter, the CS5012A/14/16 require careful attention to grounding and layout arrangements. However, no unique layout issues must be addressed to prop- erly apply the device. The CDB5012/14/16 evaluation board is available for the CS5012A/14/16, which avoids the need to de- sign, build, and debug a high-precision PC board to initially characterize the part. The board comes with a socketed CS5012A/14/16, and can be quickly reconfigured to simulate any combination of sampling, calibration, CLKIN, and analog in- put range conditions. CS5012A, CS5014, CS5016 2-28 DS14F6

grates to 35 µV rms in unipolar mode. digitally filtering to the desired signal bandwidth. if the conversion process proceeds flawlessly. tion at low input frequencies (Figures 22 and 24). overall S/(N+D) performance (Figures 31-34). time the entire conversion cycle finishes. Figure 30. Histogram Plot of 5000 Conversion

sampling rate, a tone will appear as the clock fre- quency aliases into the baseband. The tone frequency can be calculated using the equation below and could be selectively filtered in soft- ware using DSP techniques. ftone = (N fs - fclk) where N = fclk/fs rounded to the nearest integer The magnitude of clock feedthrough depends on the master clock conditions and the source im- pedance applied to the analog input. When operating with the CS5014/16’s internally gener- ated clock, the CLKIN input is grounded and the dominant source of coupling is through the de- vice’s substrate. As shown in Figure 35, a typical CS5014/16 operating with their internal oscillator at 2 MHz and 50 Ω of analog input source im- pedance will exhibit only 15 µV rms of clock feedthrough. However, if a 2 MHz external clock is applied to CLKIN under the same conditions, feedthrough increases to 25 µV rms. Feedthrough also increases with clock frequency; a 4 MHz clock yields 40 µV rms. Clock feedthrough can be reduced by limiting the source impedance applied at the analog input. As shown in Figure 35, reducing source impedance from 50 Ω to 25 Ω yields a 15 µV rms reduction in feedthrough. Therefore, when operating the CS5014/16 with high-frequency external master clocks, it is important to minimize source imped- ance applied to the CS5014/16’s input. Also, the overall effect of clock feedthrough can be minimized by maximizing the input range and LSB size. The reference voltage applied to VREF can be maximized, and the CS5014/16 can be op- erated in bipolar mode which inherently doubles the LSB size over the unipolar mode. Differences between the CS5012A and the CS5012 The differences between the CS5012A and the CS5012 are tabulated in Table 3. The CS5012 is a short-cycled version of the CS5016 A/D con- verter and includes the same 18-bit calibration circuitry. This calibration circuitry sets the cali- bration resolution of the CS5012 at 1/64th of an LSB and achieves the near perfect differential linearity performance illustrated by the CS5012 DNL plot in Figure 15. The CS5012A calibration circuitry was modified to provide calibration to 15-bit resolution therefore achieving calibration to 1/8 of an LSB. This reduction in calibration resolution for the CS5012A reduces the time re- quired to calibrate the device (see Table 3) and reduces the size of the total array capacitance. The reduced array capacitance improves the high frequency performance by allowing higher slew rate in the input circuitry. Table 3 documents some other improvements in- cluded in the CS5012A. The burst mode calibration was made functional, although it should not be used. The device was also modified so the EOC signal goes low at the end of a reset calibration in either microprocessor or microproc- essor-independent mode. The CS5012A was modified to maintain a throughput rate of 64 CLKIN cycles in loopback mode for all frequen- cies of CLKIN. Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. Call: (512) 445-7222 CS5012A, CS5014, CS5016 DS14F6 2-37

cycles after completion of a RESET calibration. CLKIN frequencies when in loopback. Table 3. Differences Between the CS5012A and CS5012

Figure 36. CS5012A/14/16 System Connection Diagram be connected to VD+ or DGND. Table 4. CS5012A/14/16 Truth Table CS and HOLD low, or a software reset will result.

HOLD HOLD SDATA SERIAL OUTPUT CS5016 (LSB) DATA BUS BIT 0 D0 SCLK SERIAL CLOCK DATA BUS BIT 1 D1 EOC END OF CONVERSION CS5014 (LSB) DATA BUS BIT 2 D2 EOT END OF TRACK DATA BUS BIT 3 D3 VD- NEGATIVE DIGITAL POWER CS5012 (LSB) DATA BUS BIT 4 D4 CAL CALIBRATE DATA BUS BIT 5 D5 INTRLV INTERLEAVE DATA BUS BIT 6 D6 BW BUS WIDTH SELECT DATA BUS BIT 7 D7 RST RESET DIGITAL GROUND DGND TST TEST POSITIVE DIGITAL POWER VD+ VA- NEGATIVE ANALOG POWER DATA BUS BIT 8 D8 REFBUF REFERENCE BUFFER OUTPUT DATA BUS BIT 9 D9 VREF VOLTAGE REFERENCE DATA BUS BIT 10 D10 AGND ANALOG GROUND DATA BUS BIT 11 D11 AIN ANALOG INPUT DATA BUS BIT 12 D12 VA+ POSITIVE ANALOG POWER DATA BUS BIT 13 D13 BP /UP BIPOLAR/UNIPOLAR SELECT DATA BUS BIT 14 D14 A0 READ ADDRESS (MSB) DATA BUS BIT 15 D15 RD READ CLOCK INPUT CLKIN CS CHIP SELECT HOLD D0 SDATA D1 SCLK D2 EOC D3 EOT D4 VD- D5 CAL D6 INTRLV NC BW D7 RST DGND TST VD+ VA- NC NC D8 REFBUF NC VREF D9 AGND D10 AIN D11 VA+ D12 BP/ UP D13 A0 D14 RD D15 CS CLKIN CS5012A CS5012 CS5014 CS5016 top view 18 20 22 24 26 28 12464 0 4244 17 29 CS5012A CS5012 CS5014 CS5016 NOTE: All pin references in this data sheet refer to the 40-pin DIP package numbering. Use this figure to determine pin numbers for 44-pin package. CS5012A, CS5014, CS5016 2-40 DS14F6

VD+ – Positive Digital Power, PIN 11. Positive digital power supply. Nominally +5 volts. VD- – Negative Digital Power, PIN 36. Negative digital power supply. Nominally -5 volts. DGND – Digital Ground, PIN 10. Digital ground. V A+ – Positive Analog Power, PIN 25. Positive analog power supply. Nominally +5 volts. V A- – Negative Analog Power, PIN 30. Negative analog power supply. Nominally -5 volts. AGND – Analog Ground, PIN 27. Analog ground. Oscillator CLKIN – Clock Input, PIN 20. All conversions and calibrations are timed from a master clock which can either be supplied by driving this pin with an external clock signal, or can be internally generated by tying this pin to DGND. Digital Inputs HOLD – Hold, PIN 1. A falling transition on this pin sets the CS5012A/14/16 to the hold state and initiates a conversion. This input must remain low at least one CLKIN cycle plus 50 ns. CS – Chip Select, PIN 21. When high, the data bus outputs are held in a high impedance state and the input to CAL and INTRLV are ignored. A falling transition initiates or terminates burst or interleave calibration (depending on the status of CAL and INTRLV) and a rising transition latches both the CAL and INTRLV inputs. If RD is low, the data bus is driven as indicated by BW and A0. RD – Read, PIN 22. When RD and CS are both low, data is driven onto the data bus. If either signal is high, the data bus outputs are held in a high impedance state. The data driven onto the bus is determined by BW and A0. CS5012A, CS5014, CS5016 DS14F6 2-41

A0 – Read Address, PIN 23. Determines whether data or status information is placed onto the data bus. When high during the read operation, converted data is placed onto the data bus; when low, the status register is driven onto the bus. BP/UP – Bipolar/Unipolar Input Select, PIN 24. When high, the device is configured with a bipolar transfer function ranging from -VREF to +VREF. Encoding is in an offset binary format, with the mid-scale code 100...0000 centered at AGND. When low, the device is configured for a unipolar transfer function from AGND to VREF. Unipolar encoding is in straight binary format. Once calibration has been performed, either bipolar or unipolar mode may be selected without the need to recalibrate. RST – Reset, PIN 32. When taken high for at least 100 ns, all internal digital logic is reset. Upon being taken low, a full calibration sequence is initiated. BW – Bus Width Select, PIN 33. When hard-wired high, all 12 data bits are driven onto the bus simultaneously during a data read cycle. When low, the bus is in a byte wide format. On the first read following a conversion, the eight MSB’s are driven onto D0-D7. A second read cycle places the four LSB’s with four trailing zeros on D0-D7. Subsequent reads will toggle the higher/lower order byte. Regardless of BW’s status, a read cycle with A0 low yields the status information on D0-D7. INTRLV – Interleave, PIN 34. When latched low using CS, the device goes into interleave calibration mode. A full calibration will complete every 2,014 conversions in the CS5012A, and every 72,051 conversions in the CS5014/16. The effective conversion time extends by 20 clock cycles. CAL – Calibrate, PIN 35. (See Addendum appending this data sheet)) When latched high using CS, burst calibration results. The device cannot perform conversions during the calibration period which will terminate only once CAL is latched low again. Calibration picks up where the previous calibration left off, and calibration cycles complete every 58,280 CLKIN cycles in the CS5012A, and every 1,441,020 CLKIN cycles in the CS5014/16 . If the device is converting when a calibration is signaled, it will wait until that conversion completes before beginning. Analog Inputs AIN – Analog Input, PIN 26. Input range in the unipolar mode is zero volts to VREF. Input range in bipolar mode is -VREF to +VREF. The output impedance of buffer driving this input should be less than or equal to 200 Ω . CS5012A, CS5014, CS5016 2-42 DS14F6

VREF – V oltage Reference, PIN 28. The analog reference voltage which sets the analog input range. It represents positive full scale for both bipolar and unipolar operation, and its magnitude sets negative full scale in bipolar mode. Digital Outputs D0 through D15 – Data Bus Outputs, PINS 2 thru 9, 12 thru 19. 3-state output pins. Enabled by CS and RD, they offer the converter’s output in a format consistent with the state of BW if A0 is high. If A0 is low, bits D0-D7 offer status register data. EOT – End Of Track, PIN 37. If low, indicates that enough time has elapsed since the last conversion for the device to acquire the analog input signal. EOC – End Of Conversion, PIN 38. This output indicates the end of a conversion or calibration cycle. It is high during a conversion and will fall to a low state upon completion of the conversion cycle indicating valid data is available at the output. Returns high on the first subsequent read or the start of a new conversion cycle. SDATA – Serial Output, PIN 40. Presents each output data bit after it is determined by the successive approximation algorithm. V alid on the rising edge of SCLK, data appears MSB first, LSB last, and each bit remains valid until the next bit appears. SCLK – Serial Clock Output, PIN 39. Used to clock converted output data serially from the CS5012A/14/16. Serial data is stable on the rising edge of SCLK. Analog Outputs REFBUF – Reference Buffer Output, PIN 29. Reference buffer output. A 0.1 µF ceramic capacitor must be tied between this pin and V A-. Miscellaneous TST – Test, PIN 31. Allows access to the CS5012A/14/16’s test functions which are reserved for factory use. Must be tied to DGND. CS5012A, CS5014, CS5016 DS14F6 2-43

The deviation of a code from a straight line passing through the endpoints of the transfer function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 1/2 LSB below the first code transition and "full-scale" is a point 1/2 LSB beyond the code transition to all ones. The deviation is measured from the middle of each particular code. Units in % Full-Scale. Differential Linearity Minimum resolution for which no missing codes is guaranteed. Units in bits. Full Scale Error The deviation of the last code transition from the ideal (VREF-3/2 LSB’s). Units in LSB’s. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above AGND) when in unipolar mode (BP/UP low). Units in LSB’s. Bipolar Offset AGND) when in bipolar mode (BP/ UP high). Units in LSB’s. Bipolar Negative Full-Scale Error The deviation of the first code transition from the ideal when in bipolar mode (BP/UP high). The ideal is defined as lying on a straight line which passes through the final and mid-scale code transitions. Units in LSB’s. Peak Harmonic or Spurious Noise (More accurately, Signal to Peak Harmonic or Spurious Noise) The ratio of the rms value of the signal to the rms value of the next largest spectral component below the Nyquist rate (excepting dc). This component is often an aliased harmonic when the signal frequency is a significant proportion of the sampling rate. Expressed in decibels. Total Harmonic Distortion The ratio of the rms sum of all harmonics to the rms value of the signal. Units in percent. Signal-to-Noise Ratio The ratio of the rms value of the signal to the rms sum of all other spectral components below the Nyquist rate (excepting dc), including distortion components. Expressed in decibels. Aperture Time The time required after the hold command for the sampling switch to open fully. Effectively a sampling delay which can be nulled by advancing the sampling signal. Units in nanoseconds. Aperture Jitter The range of variation in the aperture time. Effectively the "sampling window" which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds. NOTE: Temperatures specified define ambient conditions in free-air during test and do not refer to the junction temperature of the device. CS5012A, CS5014, CS5016 2-44 DS14F6

Model Throughput Conversion Time Maximum DNL Temp. Range Package CS5012A-KP12 63 kHz 12.25 µs ±1/2 LSB 0 to 70 °C 40-Pin Plastic DIP CS5012A-KP7 100 kHz 7.20 µs ±1/2 LSB 0 to 70 °C 40-Pin Plastic DIP CS5012A-KL12 63 kHz 12.25 µs ±1/2 LSB 0 to 70 °C 44-Pin PLCC CS5012A-KL7 100 kHz 7.20 µs ±1/2 LSB 0 to 70 °C 44-Pin PLCC CS5012A-BP12 63 kHz 12.25 µs ±1/2 LSB -40 to +85 °C 40-Pin Plastic DIP CS5012A-BP7 100 kHz 7.20 µs ±1/2 LSB -40 to +85 °C 40-Pin Plastic DIP CS5012A-BL12 63 kHz 12.25 µs ±1/2 LSB -40 to +85 °C 44-Pin PLCC CS5012A-BL7 100 kHz 7.20 µs ±1/2 LSB -40 to +85 °C 44-Pin PLCC 5962-8967901QA 63 kHz 12.25 µs ±1/2 LSB -55 to +125 °C 40-Pin CerDIP 5962-8967901XA 63 kHz 12.25 µs ±1/2 LSB -55 to +125 °C 44-Pin Ceramic LCC The CS5012A is recommended for new designs. The following is a list of upgraded part numbers. Discontinued Equivalent Part Number Recommended Device. CS5012-KP24 CS5012A-KP12 CS5012-KP12 CS5012A-KP12 CS5012-KP7 CS5012A-KP7 CS5012-KL24 CS5012A-KL12 CS5012-KL12 CS5012A-KL12 CS5012-KL7 CS5012A-KL7 CS5012-BD24 CS5012A-BP12 CS5012-BD12 CS5012A-BP12 CS5012-BD7 CS5012A-BP7 CS5012-BL24 CS5012A-BL12 CS5012-BL12 CS5012A-BL12 CS5012-BL7 CS5012A-BL7 CS5012-TD24B 5962-897901QA CS5012-TD12B 5962-897901QA CS5012-TE24B 5962-897901XA CS5012-TE12B 5962-897901XA CS5012A, CS5014, CS5016 DS14F6 2-45

Model Throughput Conversion Time Linearity Temp. Range Package CS5014-KP28 28 kHz 28.50 µs ±0.5 LSB 0 to 70 °C 40-Pin Plastic DIP CS5014-KP14 56 kHz 14.25 µs ±0.5 LSB 0 to 70 °C 40-Pin Plastic DIP CS5014-KL28 28 kHz 28.50 µs ±0.5 LSB 0 to 70 °C 44-Pin PLCC CS5014-KL14 56 kHz 14.25 µs ±0.5 LSB 0 to 70 °C 44-Pin PLCC CS5014-BP28 28 kHz 28.50 µs ±0.5 LSB -40 to +85 °C 40-Pin Plastic DIP CS5014-BP14 56 kHz 14.25 µs ±0.5 LSB -40 to +85 °C 40-Pin Plastic DIP CS5014-BL28 28 kHz 28.50 µs ±0.5 LSB -40 to +85 °C 44-Pin PLCC CS5014-BL14 56 kHz 14.25 µs ±0.5 LSB -40 to +85 °C 44-Pin PLCC CS5014-SD14 56 kHz 14.25 µs ±1.5 LSB -55 to +125 °C 40-Pin CerDIP CS5014-TD14 56 kHz 14.25 µs ±0.5 LSB -55 to +125 °C 40-Pin CerDIP CS5014-SE14 56 kHz 14.25 µs ±1.5 LSB -55 to +125 °C 44-Pin Ceramic LCC CS5014-TE14 56 kHz 14.25 µs ±0.5 LSB -55 to +125 °C 44-Pin Ceramic LCC 5962-8967401QA 56 kHz 14.25 µs ±1.5 LSB -55 to +125 °C 40-Pin CerDIP 5962-8967402QA 56 kHz 14.25 µs ±0.5 LSB -55 to +125 °C 40-Pin CerDIP 5962-8967401XA 56 kHz 14.25 µs ±1.5 LSB -55 to +125 °C 44-Pin Ceramic LCC 5962-8967402XA 56 kHz 14.25 µs ±0.5 LSB -55 to +125 °C 44-Pin Ceramic LCC The following is a list of upgraded part numbers. Discontinued Equivalent Part Number Recommended Device CS5014-SD14B 5962-8967401QA CS5014-TD14B 5962-8967402QA CS5014-SE14B 5962-8967401XA CS5014-TE14B 5962-8967402XA CS5012A, CS5014, CS5016 2-46 DS14F6

Model Linearity Noise Ratio Conversion Time Temp. Range Package CS5016-JP32 .0030% 87 dB 32.50 µs 0 to 70 °C 40-Pin Plastic DIP CS5016-JP16 .0030% 87 dB 16.25 µs 0 to 70 °C 40-Pin Plastic DIP CS5016-KP32 .0015% 90 dB 32.50 µs 0 to 70 °C 40-Pin Plastic DIP CS5016-KP16 .0015% 90 dB 16.25 µs 0 to 70 °C 40-Pin Plastic DIP CS5016-JL32 .0030% 87 dB 32.50 µs 0 to 70 °C 44-Pin PLCC CS5016-JL16 .0030% 87 dB 16.25 µs 0 to 70 °C 44-Pin PLCC CS5016-KL32 .0015% 90 dB 32.50 µs 0 to 70 °C 44-Pin PLCC CS5016-KL16 .0015% 90 dB 16.25 µs 0 to 70 °C 44-Pin PLCC CS5016-AP32 .0030% 87 dB 32.50 µs -40 to +85 °C 40-Pin Plastic DIP CS5016-AP16 .0030% 87 dB 16.25 µs -40 to +85 °C 40-Pin Plastic DIP CS5016-BP32 .0015% 90 dB 32.50 µs -40 to +85 °C 40-Pin Plastic DIP CS5016-BP16 .0015% 90 dB 16.25 µs -40 to +85 °C 40-Pin Plastic DIP CS5016-AL32 .0030% 87 dB 32.50 µs -40 to +85 °C 44-Pin PLCC CS5016-AL16 .0030% 87 dB 16.25 µs -40 to +85 °C 44-Pin PLCC CS5016-BL32 .0015% 90 dB 32.50 µs -40 to +85 °C 44-Pin PLCC CS5016-BL16 .0015% 90 dB 16.25 µs -40 to +85 °C 44-Pin PLCC CS5016-SD16 .0076% 87 dB 16.25 µs -55 to +125 °C 40-Pin CerDIP CS5016-TD16 .0015% 90 dB 16.25 µs -55 to +125 °C 40-Pin CerDIP CS5016-SE16 .0076% 87 dB 16.25 µs -55 to +125 °C 44-Pin Ceramic LCC CS5016-TE16 .0015% 90 dB 16.25 µs -55 to +125 °C 44-Pin Ceramic LCC 5962-8967601QA .0076% 87 dB 16.25 µs -55 to +125 °C 40-Pin CerDIP 5962-8967602QA .0015% 90 dB 16.25 µs -55 to +125 °C 40-Pin CerDIP 5962-8967601XA .0076% 87 dB 16.25 µs -55 to +125 °C 44-Pin Ceramic LCC 5962-8967602XA .0015% 90 dB 16.25 µs -55 to +125 °C 44-Pin Ceramic LCC The following is a list of upgraded part numbers. Discontinued Equivalent Part Number Recommended Device CS5016-SD16B 5962-8967601QA CS5016-TD16B 5962-8967602QA CS5016-SE16B 5962-8967601XA CS5016-TE16B 5962-8967602XA CS5012A, CS5014, CS5016 DS14F6 2-47

D B A L C 13.72 51.69 1.02 0.36 0.51 3.94 3.18 0.20 2.41 15.24 14.22 52.71 1.65 0.56 1.02 5.08 3.81 0.38 15° 0.540 2.035 0.095 0.040 0.014 0.020 0.155 0.125 0.600 0.008 0.560 2.075 0.065 0.022 0.040 0.200 0.150 0.015 15° 40 pin Plastic DIP1 40 21 15.87 0.625 D B SEATING PLANE A B1 e1 A1 L C eA ∝∝ 2.67 0.105 ∝∝NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. NOM 13.97 52.20 1.27 0.46 0.76 4.32 0.25 2.54 NOM 0.550 2.055 0.100 0.050 0.018 0.030 0.170 0.010 eA

D D2/E2 44 pin PLCC NO. OF TERMINALS D2/E2 MAXMIN MAX MIN MILLIMETERS INCHES DIM A D/E 17.6517.40 0.685 B e AA1 B e 0.695 16.6616.51 0.650 0.656 4.574.20 0.180 0.165 0.530.33 0.021 0.013 2.29 0.090 16.0014.99 0.590 0.630 1.19 1.35 0.047 0.053 NOM 17.53 16.59 4.45 0.41 2.79 15.50 1.27 NOM 0.690 0.653 0.175 0.016 0.110 0.610 0.050 3.04 0.120 D1/E1

NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.13mm (0.005") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 40 pin CerDIP1 40 21 D B SEATING PLANE A B1 e1 A1 L C eA 0.46 0.25 52.32 14.73 2.54 15.24 3.81 0.018 0.010 2.060 0.580 0.100 0.600 0.150 12.70 50.29 1.27 0.38 0.51 4.06 2.92 0.20 2.41 15.11 15.37 52.57 1.65 0.56 1.27 5.84 4.06 0.30 15° 15.37 2.67 0.500 1.980 0.095 0.050 0.015 0.020 0.160 0.115 0.595 0.008 0.605 2.070 0.065 0.022 0.050 0.230 0.160 0.012 15° 0.605 0.105 MILLIMETERS INCHES DIM MIN MAX MIN D B A L eA C NOM NOM MAX

NO. OF TERMINALS MAXMIN MAXMINMAXMIN MAX MIN MILLIMETERS MILLIMETERSINCHES INCHES DIM E1Top View E D 28/44 pin CLCC A B D4/E4 NOM 3.05 0.46 NOM 0.120 0.018 NOM 3.05 0.46 NOM 0.120 0.018 D/E 0.6600.64016.26 16.76 11.18 11.68 0.480 0.500 0.440 0.460 12.46 11.43 1.27 7.62 10.92 0.490 0.450 0.050 0.300 0.430 16.51 17.53 1.27 12.70 16.00 0.650 0.690 0.050 0.500 0.630 0.64 0.025 0.64 0.025 D1/E1

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