CS5012A CIRRUS | Alldatasheet
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Technical content
Features
z Monolithic CMOS A/D Converters – Microprocessor Compatible – Parallel & Serial Output – Inherent Track/Hold Input z True 12-bit, 14-bit, and 16-bit Precision z Conversion Times – CS5016: 16.25 µs – CS5014: 14.25 µs – CS5012A: 7.20 µs z Linearity Error: ±0.001% FS – Guaranteed No Missing Codes z Self-calibration Maintains Accuracy – Accurate Over Time & Temperature z Low Power Consumption – 150 mW z Low Distortion
Description
The CS5012A/14/16 are 12-, 14-, and 16-bit mono- lithic analog to digital converters with conversion times of 7.2 µs, 14.25 µs and 16.25 µs. Unique self- calibration circuitry ensures excellent linearity and differential nonlinearity, with no missing codes. Off- set and full-scale errors are kept within 1/2 LSB (CS5012A/14) and 1 LSB (CS5016), eliminating the need for calibration. Unipolar and bipolar input ranges are digitally selectable. The pin compatible CS5012A/14/16 consist of a DAC, conversion and calibration microcontroller, oscillator, comparator, microprocessor-compatible 3-state I/O, and calibration circuitry. The input track-and-hold, inherent to the devices’ sampling architecture, acquires the input signal after each conversion using a fast-slewing, on-chip buffer am- plifier. This allows throughput rates up to 100 kSps(CS5012A), 56 kSps (CS5014), and 50 kSps (CS5016).
ORDERING INFORMATION
See “Ordering Information” on page39. I CLKIN REFBUF VREF AIN AGND HOLD CS RD BP/UP RST BW INTRLV CAL EOT EOC SCLK SDATA D0 (LSB) CS5016 D2 (LSB) CS5014 D4 (LSB) CS5012A D10 D11 D12 D13 D14 D15 (MSB) TST DGND VD- VD+ VA- VA+ Clock Generator Control Calibration Microcontroller Status Register Comparator Charge Memory Redistribution DAC AUG ‘05 DS14F9
CS5012A ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 2.5V to 4.5V; fclk = 6.4 MHz for -7, 4 MHz for -12; Analog Source Impedance = 200Ω) CS5012A Parameter* Min Typ Max Units Specified Temperature Range -40 to +85 Accuracy Linearity Error (Note 1) Drift (Note 2) ±1/4 ±1/8 ±1/2 LSB12 ∆LSB12 Differential Linearity (Note 1) Drift (Note 2) ±1/4 ±1/32 ±1/2 LSB12 ∆LSB12 Full Scale Error (Note 1) Drift (Note 2) ±1/4 ±1/16 ±1/2 LSB12 ∆LSB12 Unipolar Offset (Note 1) Drift (Note 2) ±1/4 ±1/16 ±1/2 LSB12 ∆LSB12 Bipolar Offset (Note 1) Drift (Note 2) ±1/4 ±1/16 ±1/2 LSB12 ∆LSB12 Bipolar Negative Full-Scale Error(Note 1) Drift (Note 2) ±1/4 ±1/16 ±1/2 LSB12 ∆LSB12 Total Unadjusted Error (Note 1) Drift (Note 2) ±1/4 ±1/4 LSB12 ∆LSB12 Dynamic Performance (Bipolar Mode) Peak Harmonic or (Note 1) Spurious Noise Full Scale, 1 kHz Input Full Scale, 12 kHz Input dB dB Total Harmonic Distortion 0.008 Signal-to-Noise Ratio (Note 1) 1 kHz, 0 dB Input 1 kHz, -60 dB Input dB dB Noise (Note 3) Unipolar Mode Bipolar Mode µVrms µVrms Notes: 1. Applies after calibration at any temperature within the specified temperature range. 2. Total drift over specified temperature range since calibration at power-up at 25 °C 3. Wideband noise aliased into the baseband. Referred to the input. * Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet). Specifications are subject to change without notice. 2-8 DS14F8 CS5012A CS5014 CS5016 DS14F9
CS5012A ANALOG CHARACTERISTICS (continued) CS5012A Parameter* Min Typ Max Units Specified Temperature Range -40 to +85 Analog Input Aperture Time ns Aperture Jitter 100 ps Input Capacitance (Note 4) Unipolar Mode CS5012A Bipolar Mode CS5012A 103 137 pF pF pF pF Conversion & Throughput Conversion Time (Notes 5 and 6) 7.2 µs Acquisition Time (Note 6) 2.5 2.8 µs Throughput (Note 6) 100 kSps Power Supplies DC Power Supply Currents (Note 7) IA+ IA- (CS5012A) ID+ ID- -12 -19 7.5 mA mA mA mA mA Power Dissipation (Note 7) 150 250 mW Power Supply Rejection (Note 8) Positive Supplies Negative Supplies dB dB Notes: 4. Applies only in track mode. When converting or calibrating, input capacitance will not exceed 15 pF. 5. Measured from falling transition on HOLD to falling transition on EOC. 6. Conversion, acquisition, and throughput times depend on CLKIN, sampling, and calibration conditions. The numbers shown assume sampling and conversion is synchronized with the CS5012A/14/16 ’s conversion clock, interleave calibrate is disabled, and operation is from the full-rated, external clock. Refer to the section Conversion Time/Throughput for a detailed discussion of conversion timing. 7. All outputs unloaded. All inputs CMOS levels. 8. With 300 mV p-p, 1 kHz ripple applied to each analog supply separately in bipolar mode. Rejection improves by 6 dB in the unipolar mode to 90 dB. Figure 13 shows a plot of typical power supply rejection versus frequency. CS5012A DS14F8 2-9 CS5012A CS5014 CS5016 DS14F9
CS5014 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; CLKIN = 4 MHz for -14, 2 MHz for -28; Analog Source Impedance = 200Ω) CS5014-B Parameter* Min Typ Max Units Specified Temperature Range -40 to +85 Accuracy Linearity Error (Note 1) Drift (Note 2) ±1/4 ±1/8 ±1/2 LSB14 LSB14 ∆LSB14 Differential Linearity (Note 1) Drift (Note 2) ±1/4 ±1/32 ±1/2 LSB14 ∆LSB14 Full Scale Error (Note 1) Drift (Note 2) ±1/2 ±1/4 LSB14 ∆LSB14 Unipolar Offset (Note 1) Drift (Note 2) ±1/4 ±1/4 ±3/4 LSB14 LSB14 ∆LSB14 Bipolar Offset (Note 1) Drift (Note 2) ±1/4 ±1/2 ±3/4 LSB14 LSB14 ∆LSB14 Bipolar Negative Full-Scale Error(Note 1) Drift (Note 2) ±1/2 ±1/4 LSB14 LSB14 ∆LSB14 Total Unadjusted Error (Note 1) Drift (Note 2) LSB14 ∆LSB14 Dynamic Performance (Bipolar Mode) Peak Harmonic or (Note 1) Spurious Noise Full Scale, 1 kHz Input Full Scale, 12 kHz Input dB dB dB dB Total Harmonic Distortion 0.003 Signal-to-Noise Ratio (Notes 1 and 9) 1 kHz, 0 dB Input 1 kHz, -60 dB Input dB dB dB Noise (Note 3) Unipolar Mode Bipolar Mode µVrms µVrms Notes: 9. A detailed plot of S/(N+D) vs. input amplitude appears in Figure 26 for the CS5014 and Figure 28 for the CS5016. * Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet). Specifications are subject to change without notice. CS5014 2-10 DS14F8 CS5012A CS5014 CS5016 DS14F9
CS5014 ANALOG CHARACTERISTICS (continued) CS5014 Parameter* Min Typ Max Units Specified Temperature Range -40 to +85 Analog Input Aperture Time ns Aperture Jitter 100 ps Input Capacitance (Note 4) Unipolar Mode Bipolar Mode 275 165 375 220 pF pF Conversion & Throughput Conversion Time -14 (Notes 5 and 6) 14.25 µs Acquisition Time -14 (Note 6) 3.0 3.75 µs Throughput -14 (Note 6) 55.6 kSps Power Supplies DC Power Supply Currents (Note 7) IA+ IA- ID+ ID- -19 mA mA mA mA Power Dissipation (Note 7) 120 250 mW Power Supply Rejection (Note 8) Positive Supplies Negative Supplies dB dB DS14F8 2-11 CS5012A CS5014 CS5016 DS14F9
CS5016 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; CLKIN = 4 MHz for -16, 2 MHz for -32; Analog Source Impedance = 200Ω; Synchronous Sampling.) CS5016 Parameter* Min Typ Max Min Typ Max Min Typ Max Units Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 Accuracy Linearity Error J, A, S (Note 1) Drift (Note 2) 0.001 ±1/4 0.0015 %FS ∆LSB16 Differential Linearity (Note 10) Bits Full Scale Error J, A, S (Note 1) Drift (Note 2) LSB16 ∆LSB16 Unipolar Offset J, A, S (Note 1) Drift (Note 2) LSB16 ∆LSB16 Bipolar Offset (Note 1) Drift (Note 2) LSB16 ∆LSB16 Bipolar Negative Full-Scale Error(Note 1) Drift (Note 2) LSB16 ∆LSB16 Dynamic Performance (Bipolar Mode) Peak Harmonic or (Note 1) Spurious Noise Full Scale, 1 kHz Input Full Scale, 12 kHz Input 100 104 dB dB Total Harmonic Distortion Full Scale, 1 kHz Input 0.001 Signal-to-Noise Ratio (Notes 1 and 9) 1 kHz, 0 dB Input 1 kHz, -60 dB Input dB dB Noise (Note 3) Unipolar Mode Bipolar Mode µVrms µVrms Notes: 10. Minimum resolution for which no missing codes is guaranteed * Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet). Specifications are subject to change without notice. 2-12 DS14F8 CS5012A CS5014 CS5016 DS14F9
CS5016 ANALOG CHARACTERISTICS (continued) CS5016-J, K CS5016-A, B CS5016-S, T Parameter* Min Typ Max Min Typ Max Min Typ Max Units Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 Analog Input Aperture Time ns Aperture Jitter 100 100 100 ps Input Capacitance (Note 4) Unipolar Mode Bipolar Mode 275 165 375 220 pF pF Conversion & Throughput Conversion Time -16 (Notes 5 and 6) -32 16.25 µs Acquisition Time -16 (Note 6) -32 3.0 3.75 µs Throughput -16 (Note 6) -32 kSps Power Supplies DC Power Supply Currents (Note 7) IA+ IA- ID+ ID- -19 mA mA mA mA Power Dissipation (Note 7) 120 250 120 250 120 250 mW Power Supply Rejection (Note 8) Positive Supplies Negative Supplies dB dB DS14F8 2-13 CS5012A CS5014 CS5016 DS14F9
SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF, BW = VD+) Parameter Symbol Min Typ Max Units CS5012A CLKIN Frequency: Internally Generated: Externally Supplied: fCLK 1.75 100 kHz 6.4 MHz MHz CS5014/5016 CLKIN Frequency: Internally Generated: -14, -16 -14, -32 Externally Supplied: -14, -16 -14, -32 fCLK 1.75 100 kHz 100 kHz MHz MHz MHz MHz CLKIN Duty Cycle Rise Times: Any Digital Input Any Digital Output trise 1.0 µs ns Fall Times: Any Digital Input Any Digital Output tfall 1.0 µs ns HOLD Pulse Width thpw 1/fCLK+50 tc ns Conversion Time: CS5012A CS5014 CS5016 tc 49/fCLK+50 57/fCLK 65/fCLK 53/fCLK+235 61/fCLK+235 69/fCLK+235 ns ns ns Data Delay Time tdd 100 ns EOC Pulse Width (Note 11) tepw 4/fCLK-20 ns Set Up Times: CAL, INTRLV to CS Low A0 to CS and RD Low tcs tas ns ns Hold Times: CS or RD High to A0 Invalid CS High to CAL, INTRLV Invalid tah tch ns ns Access Times: CS Low to Data Valid RD Low to Data Valid tca tra 120 120 ns ns Output Float Delay: CS or RD High to Output Hi-Z tfd 110 ns Serial Clock Pulse Width Low Pulse Width High tpwl tpwh 2/fCLK 2/fCLK ns ns Set Up Times: SDATA to SCLK Rising tss 2/fCLK-50 2/fCLK ns Hold Times: SCLK Rising to SDATA tsh 2/fCLK-100 2/fCLK ns Notes: 11. EOC remains low 4 CLKIN cycles if CS and RD are held low. Otherwise, it returns high within 4 CLKIN cycles from the start of a data read operation or a conversion cycle. CS5012A, CS5014, CS5016 2-14 DS14F8 CS5012A CS5014 CS5016 DS14F9
90% 10% tfall rise t 90% 10% Hi-Z Hi-Z ch t tcs tah tfd tas tra tca HOLD EOC Output Data thpw tc LAST CONVERSION DATA VALID tdd NEW DATA VALID t epw D0-D15 CS RD CAL, INTRLV SDATA t ss t sh SCLK tpwl tpwh Rise and Fall Times Conversion Timing Serial Output Timing Read and Calibration Control Timing CS5012A, CS5014, CS5016 DS14F8 2-15 CS5012A CS5014 CS5016 DS14F9
CS5012A, CS5014, CS5016 DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%) Parameter Symbol Min Typ Max Units High-Level Input Voltage VIH 2.0 V Low-Level Input Voltage VIL 0.8 V High-Level Output Voltage (Note 12) VOH (VD+) - 1.0V V Low-Level Output Voltage Iout = 1.6mA VOL 0.4 V Input Leakage Current Iin µA 3-State Leakage Current IOZ ±10 µA Digital Output Pin Capacitance Cout pF Notes: 12. Iout = -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ Iout = -40 µA). RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 13) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 VA+ -5.5 5.5 -5.5 V V V V Analog Reference Voltage VREF 2.5 4.5 (VA+) - 0.5 V Analog Input Voltage: (Note 14) Unipolar Bipolar VAIN VAIN AGND -VREF VREF VREF V V Notes: 13. All voltages with respect to ground. 14. The CS5012A/14/16 can accept input voltages up to the analog supplies (VA+ and VA-). It will output all 1’s for inputs above VREF and all 0’s for inputs below AGND in unipolar mode and -VREF in bipolar mode. ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with repect to ground.) WARNING: Operation at or beyond these limits may reult in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Min Max Units DC Power Supplies: Positive Digital (Note 15) Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- -0.3 0.3 -0.3 0.3 6.0 -6.0 6.0 -6.0 V V V V Input Current, Any Pin Except Supplies (Note 16) Iin ±10 mA Analog Input Voltage (AIN and VREF pins) VINA (VA-) - 0.3 (VA+) + 0.3 V Digital Input Voltage VIND -0.3 (VA+) + 0.3 V Ambient Operating Temperature TA -55 125 Storage Temperature Tstg -65 150 Notes: 15. In addition, VD+ should not be greater than (VA+) + 0.3V. 16. Transient currents of up to 100 mA will not cause SCR latch-up. 2-16 DS14F8 CS5012A CS5014 CS5016 DS14F9
15 CLKIN cycles after EOC indicating the ana-
Table 1. Conversion and Throughput Times (tclk = Master Clock Period)
The reset calibration always works perfectly, and should be used instead of burst mode. The CS5012A/14/16’s very low drift over temperature means that, under most circum- stances, calibration will only need to be performed at power-up, using reset. The CS5012A/14/16 feature a background cali- bration mode called "interleave." Interleave appends a single calibration experiment to each conversion cycle and thus requires no dead time for calibration. The CS5012A/14/16 gathers data between conversions and will adjust its transfer function once it completes the entire sequence of experiments (one calibration cycle per 2,014 con- versions in the CS5012A and one calibration per 72,051 conversions in the CS5014 and CS5016). This is initiated by bringing both the INTRLV input and CS low (or hard-wiring INTRLV low), interleave extends the CS5012A/14/16’s effective conversion time by 20 CLKIN cycles. Other than reduced throughput, interleave is totally transpar- ent to the user. Interleave calibration should not be used intermittently. The fact that the CS5012A/14/16 offer several calibration modes is not to imply that the devices need to be recalibrated often. The devices are very stable in the presence of large temperature changes. Tests have indicated that after using a single reset calibration at 25 °C most devices ex- hibit very little change in offset or gain when exposed to temperatures from -55 to +125 °C. The data indicated 30 ppm as the typical worst case total change in offset or gain over this tem- perature range. Differential linearity remained virtually unchanged. System error sources outside of the A/D converter, whether due to changes in temperature or to long-term aging, will generally dominate total system error. Microprocessor Interface The CS5012A/14/16 feature an intelligent micro- processor interface which offers detailed status information and allows software control of the self-calibration functions. Output data is available in either 8-bit or 16-bit formats for easy interfac- ing to industry-standard microprocessors. Strobing both CS and RD low enables the CS5012A/14/16’s 3-state output buffers with either output data or status information depending on the status of A0. An address bit can be con- nected to A0 as shown in Figure 4b thereby memory mapping the status register and output data. Conversion status can be polled in software by reading the status register (CS and RD strobed low with A0 low), and masking status bits S0-S5 and S7 (by logically AND’ing the status word with 01000000) to determine the value of S6. Similarly, the software routine can determine calibration status using other status bits (see Ta- ble 2). Care must be taken not to read the status register (A0 low) while HOLD is low, or a soft- ware reset will result (see Reset above). Alternatively, the End-of-Convert (EOC) output can be used to generate an interrupt or drive a DMA controller to dump the output directly into memory after each conversion. The EOC pin falls as each conversion cycle is completed and data is valid at the output. It returns high within four CLKIN cycles of the first subsequent data read operation or after the start of a new conversion cycle. CS5012A, CS5014, CS5016 2-22 DS14F8 CS5012A CS5014 CS5016 DS14F9
byte will appear on the next data read operation. converting will not introduce conversion errors. and returns high on the first subsequent read. indicates which byte will appear at the output next. the devices specified accuracy. High when the device is tracking the input. High when the device is converting the held input. High when the device is calibrating. Table 2. Status Pin Definitions Figure 7. CS5012A/14/16 Data Format
the data from the CS5012A/14/16 (See Figure 9). ease the demands placed on external circuitry. Figure 8. Microprocessor-Independent Connections
signal frequencies or their harmonics. exhibit extremely low output impedance at dc. ramic capacitor is recommended. Figure 9. Serial Output Timing
- Timing delay td (relative to CLKIN) can vary between 135 ns to 235 ns over the military temperature range
- EOC returns high in 4 CLKIN cycles if A0 = 1 and CS = RD = 0 (Microprocessor Independent Mode);
is recognized on a rising edge of CLKIN/4.
(6 clock cycles) and 2.25 µs for fine-charging. to decrease source impedance at high frequencies. in unipolar mode and 0.5V/µs in bipolar mode. Figure 12. Pipelined MUX Input Channels
Analog Input Range/Coding Format The reference voltage directly defines the input voltage range in both the unipolar and bipolar configurations. In the unipolar configuration (BP/UP low), the first code transition occurs
0.5 LSB above AGND, and the final code transi-
tion occurs 1.5 LSB’s below VREF. Coding is in straight binary format. In the bipolar configura- tion (BP/UP high), the first code transition occurs
0.5 LSB above -VREF and the last transition oc-
curs 1.5 LSB’s below +VREF. Coding is in an offset-binary format. Positive full scale gives a digital output of all ones, and negative full scale gives a digital output of all zeros. The BP/UP mode pin may be switched after cali- bration without having to recalibrate the converter. However, the BP/UP mode should be changed during the previous conversion cycle, that is, between HOLD falling and EOC falling. If BP/UP is changed at any other time, one dummy conversion cycle must be allowed for proper acquisition of the input. Grounding and Power Supply Decoupling The CS5012A/14/16 use the analog ground con- nection, AGND, only as a reference voltage. No dc power currents flow through the AGND con- nection, and it is completely independent of DGND. However, any noise riding on the AGND input relative to the system’s analog ground will induce conversion errors. Therefore, both the ana- log input and reference voltage should be referred to the AGND pin, which should be used as the entire system’s analog ground reference point. The digital and analog supplies to the CS5012A/14/16 are pinned out separately to minimize coupling between the analog and digital sections of the chip. All four supplies should be decoupled to their respective grounds using 0.1 µF ceramic capacitors. If significant low-fre- quency noise is present on the supplies, 1 µF tantalum capacitors are recommended in parallel with the 0.1 µF capacitors. The positive digital power supply of the CS5012A/14/16 must never exceed the positive analog supply by more than a diode drop or the device could experience permanent damage. If the two supplies are derived from separate sources, care must be taken that the analog sup- ply comes up first at power-up. The system connection diagram in Figure 36 shows a decou- pling scheme which allows the CS5012A/14/16 to be powered from a single set of ± 5V rails. As with any high-precision A/D converter, the CS5012A/14/16 require careful attention to grounding and layout arrangements. However, no unique layout issues must be addressed to prop- erly apply the device. CS5012A, CS5014, CS5016 2-28 DS14F8 CS5012A CS5014 CS5016 DS14F9
small fraction of an LSB during calibration. effectively subtracted once conversion is initiated. improves by 6 dB in the unipolar mode. conditions in the bipolar mode. ratios, and lead to nonideal widths for each code. can be seen in Figures 14, 15, 16. fined the point of maximum INL. step functions superimposed on the input signal.
1 MHz
Figure 13. Power Supply Rejection
grates to 35 µV rms in unipolar mode. digitally filtering to the desired signal bandwidth. ray at the moment the HOLD command is given. if the conversion process proceeds flawlessly. tion at low input frequencies (Figures 21 and 23). overall S/(N+D) performance (Figures 30-33). time the entire conversion cycle finishes. Figure 29. Histogram Plot of 5000 Conversion
sampling rate, a tone will appear as the clock fre- quency aliases into the baseband. The tone frequency can be calculated using the equation below and could be selectively filtered in soft- ware using DSP techniques. ftone = (N fs - fclk) where N = fclk/fs rounded to the nearest integer The magnitude of clock feedthrough depends on the master clock conditions and the source im- pedance applied to the analog input. When operating with the CS5014/16’s internally gener- ated clock, the CLKIN input is grounded and the dominant source of coupling is through the de- vice’s substrate. As shown in Figure 35, a typical CS5014/16 operating with their internal oscillator at 2 MHz and 50 Ω of analog input source im- pedance will exhibit only 15 µV rms of clock feedthrough. However, if a 2 MHz external clock is applied to CLKIN under the same conditions, feedthrough increases to 25 µV rms. Feedthrough also increases with clock frequency; a 4 MHz clock yields 40 µV rms. Clock feedthrough can be reduced by limiting the source impedance applied at the analog input. As shown in Figure 35, reducing source impedance from 50 Ω to 25 Ω yields a 15 µV rms reduction in feedthrough. Therefore, when operating the CS5014/16 with high-frequency external master clocks, it is important to minimize source imped- ance applied to the CS5014/16’s input. Also, the overall effect of clock feedthrough can be minimized by maximizing the input range and LSB size. The reference voltage applied to VREF can be maximized, and the CS5014/16 can be op- erated in bipolar mode which inherently doubles the LSB size over the unipolar mode. Differences between the CS5012A and the CS5012 The differences between the CS5012A and the CS5012 are tabulated in Table 3. The CS5012 is a short-cycled version of the CS5016 A/D con- verter and includes the same 18-bit calibration circuitry. This calibration circuitry sets the cali- bration resolution of the CS5012 at 1/64th of an LSB and achieves the near perfect differential linearity performance illustrated by the CS5012 DNL plot in Figure 15. The CS5012A calibration circuitry was modified to provide calibration to 15-bit resolution therefore achieving calibration to 1/8 of an LSB. This reduction in calibration resolution for the CS5012A reduces the time re- quired to calibrate the device (see Table 3) and reduces the size of the total array capacitance. The reduced array capacitance improves the high frequency performance by allowing higher slew rate in the input circuitry. Table 3 documents some other improvements in- cluded in the CS5012A. The burst mode calibration was made functional, although it should not be used. The device was also modified so the EOC signal goes low at the end of a reset calibration in either microprocessor or microproc- essor-independent mode. The CS5012A was modified to maintain a throughput rate of 64 CLKIN cycles in loopback mode for all frequen- cies of CLKIN. Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2 CS5012A, CS5014, CS5016 DS14F8 2-37 CS5012A CS5014 CS5016 DS14F9 CS5012A CS5014 CS5016 DS14F9
Figure 36. CS5012A/14/16 System Connection Diagram be connected to VD+ or DGND. Table 4. CS5012A/14/16 Truth Table CS and HOLD low, or a software reset will result.
18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 CS5012A CS5014 CS5016 Top View VD+ DGND VA- NC HOLD D15 D14 D13 D12 D11 D10 NC NC RST BW INTRLV CAL VD- EOT EOC SCLK SDATA CLKIN CS RD BP/UP VA+ AIN AGND VREF REFBUF NC TST
VD+ – Positive Digital Power, PIN 12. Positive digital power supply. Nominally +5 volts. VD- – Negative Digital Power, PIN 40. Negative digital power supply. Nominally -5 volts. DGND – Digital Ground, PIN 11. Digital ground. VA+ – Positive Analog Power, PIN 28. Positive analog power supply. Nominally +5 volts. VA- – Negative Analog Power, PIN 34. Negative analog power supply. Nominally -5 volts. AGND – Analog Ground, PIN 30. Analog ground. Oscillator CLKIN – Clock Input, PIN 23. All conversions and calibrations are timed from a master clock which can either be supplied by driving this pin with an external clock signal, or can be internally generated by tying this pin to DGND. Digital Inputs HOLD – Hold, PIN 1. A falling transition on this pin sets the CS5012A/14/16 to the hold state and initiates a conversion. This input must remain low at least one CLKIN cycle plus 50 ns. CS – Chip Select, PIN 24. When high, the data bus outputs are held in a high impedance state and the input to CAL and INTRLV are ignored. A falling transition initiates or terminates burst or interleave calibration (depending on the status of CAL and INTRLV) and a rising transition latches both the CAL and INTRLV inputs. If RD is low, the data bus is driven as indicated by BW and A0. RD – Read, PIN 25. When RD and CS are both low, data is driven onto the data bus. If either signal is high, the data bus outputs are held in a high impedance state. The data driven onto the bus is determined by BW and A0. CS5012A, CS5014, CS5016 DS14F8 2-41 CS5012A CS5014 CS5016 DS14F9
A0 – Read Address, PIN 26. Determines whether data or status information is placed onto the data bus. When high during the read operation, converted data is placed onto the data bus; when low, the status register is driven onto the bus. BP/UP – Bipolar/Unipolar Input Select, PIN 27. When high, the device is configured with a bipolar transfer function ranging from -VREF to +VREF. Encoding is in an offset binary format, with the mid-scale code 100...0000 centered at AGND. When low, the device is configured for a unipolar transfer function from AGND to VREF. Unipolar encoding is in straight binary format. Once calibration has been performed, either bipolar or unipolar mode may be selected without the need to recalibrate. RST – Reset, PIN 36. When taken high for at least 100 ns, all internal digital logic is reset. Upon being taken low, a full calibration sequence is initiated. BW – Bus Width Select, PIN 37. When hard-wired high, all 12 data bits are driven onto the bus simultaneously during a data read cycle. When low, the bus is in a byte wide format. On the first read following a conversion, the eight MSB’s are driven onto D0-D7. A second read cycle places the four LSB’s with four trailing zeros on D0-D7. Subsequent reads will toggle the higher/lower order byte. Regardless of BW’s status, a read cycle with A0 low yields the status information on D0-D7. INTRLV – Interleave, PIN 38. When latched low using CS, the device goes into interleave calibration mode. A full calibration will complete every 2,014 conversions in the CS5012A, and every 72,051 conversions in the CS5014/16. The effective conversion time extends by 20 clock cycles. CAL – Calibrate, PIN 39. When latched high using CS, burst calibration results. The device cannot perform conversions during the calibration period which will terminate only once CAL is latched low again. Calibration picks up where the previous calibration left off, and calibration cycles complete every 58,280 CLKIN cycles in the CS5012A, and every 1,441,020 CLKIN cycles in the CS5014/16 . If the device is converting when a calibration is signaled, it will wait until that conversion completes before beginning. Analog Inputs AIN – Analog Input, PIN 29. Input range in the unipolar mode is zero volts to VREF. Input range in bipolar mode is -VREF to +VREF. The output impedance of buffer driving this input should be less than or equal to 200 Ω. CS5012A, CS5014, CS5016 2-42 DS14F8 CS5012A CS5014 CS5016 DS14F9
VREF – Voltage Reference, PIN 31. The analog reference voltage which sets the analog input range. It represents positive full scale for both bipolar and unipolar operation, and its magnitude sets negative full scale in bipolar mode. Digital Outputs D0 through D15 – Data Bus Outputs, PINS 2 thru 8, 10, 14, 16 thru 22. 3-state output pins. Enabled by CS and RD, they offer the converter’s output in a format consistent with the state of BW if A0 is high. If A0 is low, bits D0-D7 offer status register data. EOT – End Of Track, PIN 41. If low, indicates that enough time has elapsed since the last conversion for the device to acquire the analog input signal. EOC – End Of Conversion, PIN 42. This output indicates the end of a conversion or calibration cycle. It is high during a conversion and will fall to a low state upon completion of the conversion cycle indicating valid data is available at the output. Returns high on the first subsequent read or the start of a new conversion cycle. SDATA – Serial Output, PIN 44. Presents each output data bit after it is determined by the successive approximation algorithm. Valid on the rising edge of SCLK, data appears MSB first, LSB last, and each bit remains valid until the next bit appears. SCLK – Serial Clock Output, PIN 43. Used to clock converted output data serially from the CS5012A/14/16. Serial data is stable on the rising edge of SCLK. Analog Outputs REFBUF – Reference Buffer Output, PIN 32. Reference buffer output. A 0.1 µF ceramic capacitor must be tied between this pin and VA-. Miscellaneous TST – Test, PIN 35. Allows access to the CS5012A/14/16’s test functions which are reserved for factory use. Must be tied to DGND. CS5012A, CS5014, CS5016 DS14F8 2-43 CS5012A CS5014 CS5016 DS14F9
The deviation of a code from a straight line passing through the endpoints of the transfer function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 1/2 LSB below the first code transition and "full-scale" is a point 1/2 LSB beyond the code transition to all ones. The deviation is measured from the middle of each particular code. Units in % Full-Scale. Differential Linearity Minimum resolution for which no missing codes is guaranteed. Units in bits. Full Scale Error The deviation of the last code transition from the ideal (VREF-3/2 LSB’s). Units in LSB’s. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above AGND) when in unipolar mode (BP/UP low). Units in LSB’s. Bipolar Offset AGND) when in bipolar mode (BP/UP high). Units in LSB’s. Bipolar Negative Full-Scale Error The deviation of the first code transition from the ideal when in bipolar mode (BP/UP high). The ideal is defined as lying on a straight line which passes through the final and mid-scale code transitions. Units in LSB’s. Peak Harmonic or Spurious Noise (More accurately, Signal to Peak Harmonic or Spurious Noise) The ratio of the rms value of the signal to the rms value of the next largest spectral component below the Nyquist rate (excepting dc). This component is often an aliased harmonic when the signal frequency is a significant proportion of the sampling rate. Expressed in decibels. Total Harmonic Distortion The ratio of the rms sum of all harmonics to the rms value of the signal. Units in percent. Signal-to-Noise Ratio The ratio of the rms value of the signal to the rms sum of all other spectral components below the Nyquist rate (excepting dc), including distortion components. Expressed in decibels. Aperture Time The time required after the hold command for the sampling switch to open fully. Effectively a sampling delay which can be nulled by advancing the sampling signal. Units in nanoseconds. Aperture Jitter The range of variation in the aperture time. Effectively the "sampling window" which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds. NOTE: Temperatures specified define ambient conditions in free-air during test and do not refer to the junction temperature of the device. CS5012A, CS5014, CS5016 2-44 DS14F8 CS5012A CS5014 CS5016 DS14F9
E D D2/E2 44 pin PLCC NO. OF TERMINALS D2/E2 MAX MIN MAX MIN MILLIMETERS INCHES DIM A D/E 17.65 17.40 0.685 B e A B e 0.695 16.66 16.51 0.650 0.656 4.57 4.20 0.180 0.165 0.53 0.33 0.021 0.013 2.29 0.090 16.00 14.99 0.590 0.630 1.19 1.35 0.047 0.053 NOM 17.53 16.59 4.45 0.41 2.79 15.50 1.27 NOM 0.690 0.653 0.175 0.016 0.110 0.610 0.050 3.04 0.120 D1/E1 CS5012A CS5014 CS5016 DS14F9 PACKAGE DIMENSIONS
- ORDERING INFORMATION 5. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JDEC J-STD-020. Model Conversion Time Throughput Linearity Temperature Package CS5012A-BL7 7.2 µs 100 kSps ±½ LSB -40 to +85 °C 44-pin PLCC CS5012A-BL7Z (lead free) CS5014-BL14 14.25 µs 56 kSps CS5014-BL14Z (lead free) Model Conversion Time S/N Ratio Linearity Temperature Package CS5016-BL16 16.25 µs 90 dB 0.0015% -40 to +85 °C 44-pin PLCC CS5016-BL16Z (lead free) Model Peak Relfow Temp MSL Rating* Maximum Floor Life CS5012A-BL7 225 °C
365 Days
CS5012A-BL7Z (lead free) 260 °C CS5014-BL14 225 °C CS5014-BL14Z (lead free) 260 °C CS5016-BL16 225 °C CS5016-BL16Z (lead free) 260 °C
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