CS496122-CQZ

Cirrus Logic

Digital Audio Networking Processor

Manufacturer: Cirrus Logic

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©Copyright 2005 Cirrus Logic, Inc. JUN ’05 DS651UM23http://www.cirrus.com Digital Audio Networking Processor CS1810xx, CS4961xx, & CM-2 Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. CobraNet Silicon Series CS18100x, CS18101x, CS18102x, and CM-2 CS49610x, CS49611x, and CS49612x Hardware User’ s Manual Version 2.3

1.0 Introduction

This document is intended to help hardware designers integrate the CobraNetTM interface into an audio system design. It covers the CS18100x, CS18101x, CS18102x, CS49610x, CS49611x, and CS49612x members of the CobraNetTM Silicon Series of devices, where “x” is the ROM version (ROM ID). This document also describes the CM-2 module with schematics, mechanical drawings, etc. CobraNet is a combination of hardware (the CobraNet interface), network protocol, and firmware. CobraNet operates on a switched Ethernet network and provides the following additional communications services. Isochronous (Audio) Data Transport Sample Clock Distribution Control and Monitoring Data Transport The CobraNet interface performs synchronous-to-isochronous and isochronous-to- synchronous conversions as well as the data formatting required for transporting real-time digital audio over the network. The CobraNet interface has provisions for carrying and utilizing control and monitoring data such as Simple Network Management Protocol (SNMP) through the same network connection as the audio. Standard data transport capabilities of Ethernet are shown here as unregulated traffic. Since CobraNet is Ethernet based, in most cases, data communications and CobraNet applications can coexist on the same physical network. Figure 1 illustrates the different data services available through the CobraNet system. Figure 1. CobraNet Data Services Isochronous Data (Audio) Control Data Clock Unregulated Traffic Ethernet Ethernet Control Data Isochronous Data (Audio) Unregulated Traffic Clock

Features

2.0 Features

2.1 CobraNet

Real-time Digital Audio Distribution via Ethernet No Overall Limit on Network Channel Capacity Fully IEEE 802.3 Ethernet Standards Compliant Fiber optic and gigabit Ethernet variants are fully supported. Ethernet infrastructure can be us ed simultaneously for audio and data communications. Free CobraCAD™ Audio Network Design Tool High-quality Audio Sample Clock Delivery Over Ethernet Bit-transparent 16-, 20-, and 24-bit Audio Transport Professional 48-kHz and 96-kHz sample rate Select Latency as Low as 1.33ms Flexible Many-to-many Network Audio Routing Capabilities Reduced-cost, Improved-performance, Convergent Audio Distribution Infrastructure

2.2 CobraNet Interface

120 MIPS Customer-configurable Audio DSP Auto-negotiating 100Mbit Full-duplex Ethernet Connections Up to 32-channel Audio I/O Capability Implements CobraNet Protocol for real-time transport of audio over Ethernet. Local Management via 8-bit Parallel Host Port UDP/IP Network Stack with Dynamic IP Address Assignment via BOOTP or RARP Remote Management via Simple Network Management Protocol (SNMP) Economical Three-chip Solution Available Module form factor allows for flexible integration into audio products. Non-volatile Storage of Configuration Parameters Safely Upgrade Firmware Over Ethernet Connection LED Indicators for Ethernet Link, Activity, Port Selection, and Conductor Status Watchdog Timer Output for System Integrity Assurance Comprehensive Power-on Self-test (POST) Error and Fault Reporting and Logging Mechanisms

2.3 Host Interface

8-bit Data, 4-bit Address Virtual 24-bit Addressing with 32-bit Data Polled, Interrupt, and DMA Modes of Operation Configure and Monitor CobraNet Interface Transmit or Receive Ethernet Packets at Near-100-Mbit Wire Speed

2.4 Asynchronous Serial Interface

Full-duplex Capable 8-bit Data Format Supports all Standard Baud Rates

2.5 Synchronous Serial Audio Interface

Up to Four Bi-directional Interfaces Supporting up to 32 Channels of Audio I/O 64FS (3.072 MHz) Bit Rate for CS18100x/CS49610x and CS18101x/ CS49611x 128FS (6.144 MHz) Bit Rate for CS18102x/CS49612x Accommodates Many Synchronous Serial Formats Including I 2S 32-bit Data Resolution on All Audio I/O

2.6 Audio Clock Interface

5 Host Audio-clocking Modes for Maximum Flexibility in Digital Audio Interface Design Low-jitter Master Audio Clock Oscillator (24.576 MHz) Synchronize to Supplied Master and/or Sample Clock Sophisticated jitter attenuation assures network perturbations do not affect audio performance.

2.7 Audio Routing and Processing

Single-channel Granularity in Routing From Synchronous Serial Audio Interface to CobraNet Network Two levels of inward audio routing affords flexibility in audio I/O interface design in the host system. Local Audio Loopback and Output Duplication Capability Peak-read Audio Metering with Ballistics

3.0 Hardware

Figure 2 shows a high-level view of the CobraNet CM-2 interface hardware architecture. Figure 2. CobraNet Interface Hardware Block Diagram Flash memory holds the CobraNet firmware and management interface variable settings. sample clock regeneration and performs all interactions with the host system. lock with the network clock. Ethernet standard. As per Ethernet requirements the interface is transformer isolated.

4.0 Pinout and Signal Descriptions

This section details the chip pinout and signal interfaces for each module and is divided as follows: "CS1810xx & CS4961xx Package Pinouts" on page 10 "Host Port Signals" on page 12 "Asynchronous Serial Port (UART Bridge) Signals" on page 12 "Synchronous Serial (Audio) Signals" on page 13 "Audio Clock Signals" on page 13 "Miscellaneous Signals" on page 14 "Power and Ground Signals" on page 14 "System Signals" on page 15

4.1 CS1810xx & CS4961 xx Package Pinouts

4.1.1 CS1810xx/CS4961xx Pinout

for these signals are expanded in the following sections. Table 1. CS1810xx/CS4961xx Pin Assignments

1 VCXO_CTRL 37 DATA1 73 VDDIO 109 HADDR1

2 MCLK_SEL 38 WE 74 ADDR10 110 HADDR0

3 DBDA 39 DATA0 75 ADDR14 111 HDATA7

4 DBCK 40 DATA15 76 GND 112 HDATA6

5 NC 41 DATA14 77 ADDR13 113 VDDIO

6 NC 42 DATA13 78 NC 114 HDATA5

7 NC 43 DATA12 79 NC 115 HDATA4

8 DAO_MCLK 44 VDDIO 80 NC 116 GND

9 TEST 45 DATA11 81 NC 117 HDATA3

10 VDDD 46 DATA10 82 ADDR15 118 HDATA2

11 HS3 47 GND 83 VDDD 119 VDDD

12 NC 48 DATA9 84 ADDR16 120 HDATA1

13 GND 49 DATA8 85 ADDR17 121 HDATA0

14 DAO2_LRCLK 50 NC 86 GND 122 GND

15 DAO1_DATA3 51 NC 87 ADDR18 123 XTAL_OUT

16 DAO1_DATA2/HS2 52 NC 88 ADDR19 124 XTO

17 DAO1_DATA1/HS1 53 NC 89 OE 125 XTI

18 VDDIO 54 VDDD 90 CS1 126 GND_a

19 DAO1_DATA0/HS0 55 ADDR12 91 VDDIO 127 FILT2

20 DAO1_SCLK 56 ADDR11 92 MUTE 128 FILT1

21 GND 57 GND 93 HRESET 129 VDDA

22 DAO1_LRCLK 58 ADDR9 94 GND 130 VDDD

23 UART_TX_OE 59 ADDR8 95 WATCHDOG 131 DAI1_DATA3

24 VDDD 60 VDDIO 96 IOWAIT 132 DAI1_DATA2

25 UART_TXD 61 ADDR7 97 REFCLK_IN 133 GND

26 UART_RXD 62 ADDR6 98 VDDD 134 DAI1_DATA1

27 GND 63 GND 99 GPIO0 135 DAI1_DATA0

28 NC 64 ADDR5 100 GPIO1 136 VDDIO

29 DATA7 65 CS2 101 GND 137 DAI1_SCLK

30 DATA6 66 VDDD 102 HACK 138 DAI1_LRCLK

31 DATA5 67 ADDR4 103 HDS 139 GND

32 DATA4 68 ADDR3 104 HEN 140 HREQ

33 VDDIO 69 GND 105 HADDR3 141 NC

34 DATA3 70 ADDR2 106 HADDR2 142 NC

35 DATA2 71 ADDR1 107 HR/W 143 IRQ1

36 GND 72 ADDR0 108 GPIO2 144 IRQ2

4.1.2 CM-2 Connector Pinout

interfaces for these signals are expanded following the table. Table 2. CM-2 Pin Assignments

4.2 Signal Descriptions

4.2.1 Host Port Signals

The host port is used to manage and monitor the CobraNet interface. Electrical operation and protocol is detailed in the "Host Management Interface (HMI)" on page 23 of this Manual. The host port can operate in two modes in order to accomodate Motorola® or Intel® style interfaces. The default mode is Motorola. Intel mode is set via a firmware modification.

4.2.2 Asynchronous Serial Po rt (UART Bridge) Signals

Level-shifting drive circuits are typically required between these signals and any external connections. Table 2-1: Host Port Signals Signal Description Direction CM-2 Pin # CS1810xx/ CS4961xx Pin # Notes HDATA[7:0] Host Data In/Out J1:A19, A[17:11] 111, 112, 114, 115, 117, 118, 102, 121 Host port data. HADDR[3:0] Host Address In J1:A20, A[10:8] 105, 106, 109,110 Host port address. HRW Host Direction In J1:A4 107 Host port transfer direction (Motorola mode). HRD Host Read In J1:A4 107 Host Read (Intel mode). HREQ Host Request Out J1:A6 140 Host port data request. HACK Host Alert Out J1:A3 102 Host port interrupt request. HDS Host Strobe In J1:A5 103 Host port strobe (Motorola mode). HWR Host Write In J1:A5 103 Host Write (Intel mode). HEN Host Enable In J1:A7 104 Host Port Enable. HCS Select In J1:A7 104 Select (Intel mode). Signal Description Direction CM-2 Pin # CS1810xx/ CS4961xx Pin # Notes UART_RXD Asynchronous Serial Receive Data In J1:A1 26 Pull-up to VCC if unused. UART_TXD Asynchronous Serial Transmit Data Out J1:B1 25 UART_TX_OE Transmit Drive Enable Out J1:A2 23 Enable transmit (active high) drive for two wire multi-drop interface.

4.2.3 Synchronous Serial (Audio) Signals

The synchronous serial interfaces are used to bring digital audio into and out of the system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing and format is described in "Digital Audio Interface" on page 19.

4.2.4 Audio Clock Signals

See "Synchronization" on page 17 for an overview of synchronization modes and issues. *An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out implementation. Signal Description Direction CM-2 Pin # CS1810xx/ CS4961xx Pin # Notes DAO1_SCLK Audio Bit Clock Out J3:A7 20 Synchronous serial bit clock.

64 FS for CS18100x & CS49610x (2x1 channel)

64 FS for CS18101x & CS49611x (2x4

channels)

128 FS for CS18102x & CS49612x (4x4

channels) Typically tied to DAI1_SCLK. DAO1_DATA[3:0] Audio Output Data Out J3:A18, B18 15-17, 19 Output synchronous serial audio data DAO1_DATA[3:1] not used for CS18100x & CS49610x. DAI1_DATA[3:0] Audio Input Data In J3: A[15:12] 131, 132, 134, 135 Input synchronous serial audio data DAI1_DATA[3:1] not used for CS18100x & CS49610x. DAI1_SCLK Audio Bit Clock In J4:A7 137 Should be tied to DAO1_SCLK. Synchronous serial bit clock. Signal Description Direction CM-2 Pin # CS1810xx/ CS4961xx Pin # Notes DAI1_LRCLK Sample clock input In 138 Should be tied to DAO1_LRCLK for all devices. DAO1_LRCLK (FS1) Sample clock output Out J3:A3 22 FS1 (word clock) for CS18100x/CS49610x and CS18101x/CS49611x. DAO2_LRCLK (FS1) Sample clock output Out J3:A3 14 FS1 (word clock) for CS18102x & CS49612x. REFCLK_IN Reference clock In J3:A6 97 Clock input for synchronizing network to an external clock source, for redundancy control and synchronization of FS divider chain to external source. See "Synchronization" on page 17 for more detail. MCLK_IN Master audio clock input In J3:A5 8* For systems featuring multiple CobraNet interfaces operating off a common master clock. See "Synchronization" on page 17 for more detail. MCLK_OUT Master audio clock output Out J3:A4 8* Low jitter 24.576 MHz master audio clock.

4.2.5 Miscellaneous Signals

4.2.6 Power and Ground Signals

Signal Description Direction CM-2 Pin # CS1810xx/ CS4961xx Pin # Notes HRESET Reset In J1:A18 93 System reset (active low). 10 ns max rise time. 1 ms min assertion time. WATCHDOG Watch Dog Out J3:A17 95 Toggles at 750 Hz nominal rate to indicate proper operation. Period duration in excess of 200 ms indicates hardware or software failure has occurred and the interface should be reset. Note that improper operation can also be indicated by short pulses (<100 ns). MUTE Interface Ready Out J3:A2 92 Asserts (active low) during initialization and when a fault is detected or connection to the network is lost. NC No Connect - - 28, 50-53, 78- 81, 141, 142 Signal Description CM-2 Pin # CS1810xx/CS4961xx Pin # Specification VCC_+3V System Digital +3.3 v J1:B20, B17, B15, B13, B11, B9, B7, B5, B3 J3:B14, B12, B10, B8, B6, B4, B2 N/A 3.3 ± 0.3v, 500 mA Typ., 750 mA Max. VCC_+5V J3;B[18:17] N/A Backw ards Compatibility VDDD N/A 10, 24, 54, 66, 83, 98, 119, 130 +1.8 V @ 500mA Typ. for Core Logic VDDIO N/A 18, 33, 44, 60, 73, 91, 113, 136 +3.3 V @ 120mA Typ. for I/O Logic VDDA N/A 129 Filtered +1.8 V @ 10mA Typ. AUX_POWER [3-0] J3:B[20:19], A[20:19] N/A GND Digital Ground J1:B19, B16, B14, B12, B10, B8, B6, B4, B2 J3:B16, B15, B13, B11, B9, B7, B5, B3, B1 94, 101, 116, 122, 126, 133, 139

4.2.7 System Signals

Use these CS1810xx/CS4961xx signals stricktly in the manner described in CM-2 Schematics (Section 9.2 on page 44). Each signal is briefly described below. Signal Description CS1810xx/CS4961xx Pin # VCXO_CTRL A Delta-sigma DAC Output for Controlling the On-board VCXO 1 MCLK_SEL Control Signal for Selecting MCLK Sources 2 DBDA, DBCK I2C Debugger Interface 3, 4 TEST Used for testing during manufacturing. Keep grounded for normal operation. 9 DATA[15:0] Data Bus for Flash & Ethernet Controller(s) 29-32, 34, 35, 37, 39-43, 45, 46, 48, 49 ADDR[19:0] Address Bus for Flash & Ethernet Controller(s) 82, 84, 85, 87, 88 WE Write Enable for Flash and Ethernet Controller(s) 38 CS1 Chip Select for Flash Memory Device 90 CS2 Chip Select for Ethernet Controller(s) 65 OE Output Enable 89 IOWAIT Wait State Signal from Ethernet Controller(s) 96 GPIO[2:0] General-purpose I/O Signals 99, 100, 108 XTI Reference Clock Input / Crystal Oscillator Input 125 XTO Crystal Oscillator Output 124 XTAL_OUT A Buffered Version of XTI 123 FILT2, FILT1 PLL Loop Filter 127, 128 DAO_MCLK MCLK Input 8 HS[3:0] CS1810xx/CS4961xx Boot Mode Selection 11, 16, 17, 19

4.3 Characteristics and Specifications

4.3.1 Absolute Maximum Ratings

Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

4.3.2 Recommended Operating Conditions

4.3.3 Digital DC Characteristics

(measurements performed under static conditions.)

4.3.4 Power Supply Characteristics

(measurements performed under operating conditions)) NOTES:1. Dependent on application firmware and DSP clock speed. Parameter Symbol Min Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDD| VDD VDDA VDDIO –0.3 –0.3 –0.3 2.0 2.0 5.0 0.3 V V V V Input current, any pin except supplies I in -+ / - 1 0 m A Input voltage on FILT1, FILT2 V filt 2.0 V Input voltage on I/O pins V inio -5 . 0 V Storage temperature T stg –65 150 °C Parameter Symbol Min Typ Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDD| VDD VDDA VDDIO 1.71 1.71 3.13 1.8 1.8 3.3 1.89 1.89 3.46 0.3 V V V V Ambient operating temperature - CQ - DQ T A - 40 + 70 + 85 Parameter Symbol Min Typ Max Unit High-level input voltage V IH 2.0 - - V Low-level input voltage, except XTI V IL -- 0 . 8V Low-level input voltage, XTI V ILXTI -- 0 . 6V Input Hysteresis V hys 0.3 V High-level output voltage at IO = –8.0 mAO = –16.0 mA VOH VDDIO * 0.9 - - V Low-level output voltage at IO = 8.0 mAO = –16.0 mA VOL -- V D D I O * 0 . 1 V Input leakage current (all pins without internal pull- up resistors except XTI) IIN --5 µA Input leakage current (pins with internal pull-up resistors, XTI) IIN-PU -- 5 0 µA Parameter Min Typ Max Unit Power supply current: Core and I/O operating: VDD (Note 1) PLL operating: VDDA With external memory and most ports operating: VDDIO 500 120 mA mA mA

5.0 Synchronization

Figure 3. Audio Clock Sub-system

5.1 Synchronization Modes

to CobraNet Programmer’s Reference Manual.

24.576 MHz

18 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User’s Manual Synchronization The following synchronization modes are further described below: "Internal Mode" on page 18 "External Word Clock Mode" on page 18 "External Master Clock Mode" on page 18

5.1.1 Internal Mode

All CobraNet clocks are derived from the onboard VCXO. The master clock generated by the VCXO is available to external circuits via the master clock output. Conductor—The VCXO is “parked” according to the syncClockTrim setting. Performer—The VCXO is “steered” to match the clock transmitted by the Conductor.

5.1.2 External Word Clock Mode

All CobraNet clocks are derived from the onboard VCXO. The VCXO is steered from an external clock supplied to the reference clock input. The clock supplied can be any integral division of the sample clock in the range of 750Hz to 48kHz. External synchronization lock range: ±5 µs. This specification indicates drift or wander between the supplied clock and the generated network clock at the conductor. Absolute phase difference between the supplied reference clock and generated sample clock is dependant on network topology. Conductor—This mode gives a means for synchronizing an entire CobraNet network to an external clock. Performer—The interface disregards the fine timing information delivered over the network from the conductor. Coarse timing information from the conductor is still used; fine timing information is instead supplied by the reference clock. The external clock source must be synchronous with the network conductor. This mode is useful in installations where a house sync source is readily available.

5.1.3 External Master Clock Mode

The VCXO is disabled and MCLK_IN is used as the master clock for the node. This is a “hard” synchronization mode. The supplied clock is used directly by the CobraNet interface for all timing. This mode is primarily useful for devices with multiple CobraNet interfaces sharing a common master audio clock. The supplied clock must be 24.576 MHz. The supplied clock must have a ±37 ppm precision. Conductor—The entire network is synchroniz ed to the supplied master clock. Performer—The node will initially lock to the netw ork clock and will “jam sync” via the supplied master clock. The external clock source must be synchronous with the network conductor.

6.0 Digital Audio Interface

Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) - CS18100x/CS49610x & Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) - CS18102x/CS49612x the rising or falling edge of FS1 (depending on the mode). recommends driving unused LS bits to zero.

Not present in CS18100x or CS49610x.

significant bits on outgoing data is zero filled.

6.1 Digital Audio Interface Timing

Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1 a MCLK_OUT edge by 0.0 to 10.0ns. Figure 7. Serial Port Data Timing Overview

6.1.1 Normal Mode Data Timing

Figure 8. Audio Data Timing Detail - Normal Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x Figure 9. Audio Data Timing Detail - Normal Mode, 128FS - CS18102x/CS49612x figure above shows 24-bit audio data. DAI_SCLK and data changes on the falling edge.

6.1.2 I 2S Mode Data Timing

Figure 10. Audio Data Timing Detail - I2S Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x Figure 11. Audio Data Timing Detail - I2S Mode, 128FS - CS18102x & CS49612x figure above shows 24-bit audio data. rising edge of DAI_SCLK and data changes on the falling edge.

6.1.3 Standard Mode Data Timing

Figure 12. Audio Data Timing Detail - Standard Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x Figure 13. Audio Data Timing Detail - Standard Mode, 128FS - CS18102x/CS49612x figure above shows 24-bit audio data. DAI_SCLK and data changes on the falling edge.

7.0 Host Management Interface (HMI)

7.1 Hardware

address bits and tie the most significant bit (A3) low. page 33 and "HMI Access Code" on page 34. Table 3. Host port memory map presumably the A, B, and C registers are read previously. Both are outputs to the host.

0 Message A (MS)

1 Message B

2 Message C

3 Message D (LS)

4 Data A (MS)

5 Data B

6 Data C

7 Data D (LS)

8 Control

9 Status

24 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User’s Manual Host Management Interface (HMI) HREQ may be wired to a host interrupt or DMA request input. HREQ is used to signal the host that data is available (read case, logic 0) or space is available in the host port data channel (write case, logic 1). The read and write case are distinguished by the HMI based on the preceding message. Identify, Goto Translation (read), Goto Packet (read) and Goto Counters cause HREQ to represent read status. Goto Translation (write) and Goto Packet (write) switch HREQ to write mode. All other commands have no effect on HREQ operation. In general, the host can read from the CS1810xx/CS4961xx when HREQ is low and can write data to CS1810xx/CS4961xx when HREQ is high.

7.2 Host Port Timing - Motorola® Mode

(CL = 20 pF) NOTES:1. The system designer should be aware that the ac tual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed to prevent overflowing the input data buffer. Parameter Symbol Min Max Unit Address setup before HEN and HDS low t mas 5- n s Address hold time after HEN and HDS low t mah 5- n s Read Delay between HDS then HEN low or HEN then HDS low t mcdr 0- n s Data valid after HEN and HDS low with HRW high t mdd -1 9 n s HEN and HDS low for read t mrpw 24 - ns Data hold time after HEN or HDS high after read t mdhr 8- n s Data high-Z after HEN or HDS high after read t mdis -1 8 n s HEN or HDS high to HEN and HDS low for next read t mrd 30 - ns HEN or HDS high to HEN and HDS low for next write t mrdtw 30 - ns HR/W rising to HREQ falling tmrwirqh -1 2 n s Write Delay between HDS then HEN low or HEN then HDS low t mcdw 0- n s Data setup before HEN or HDS high t mdsu 8- n s HEN and HDS low for write t mwpw 24 - ns HRW setup before HEN and HDS low t mrwsu 24 - ns HRW hold time after HEN or HDS high t mrwhld 8- n s Data hold after HEN or HDS high t mdhw 8- n s HEN or HDS high to HEN and HDS low with HRW high for next read tmwtrd 30 - ns HEN or HDS high to HEN and HDS low for next write t mwd 30 - ns HRW rising to HREQ falling tmrwbsyl -1 2 n s

7.3 Host Port Timing - Intel® Mode

(CL = 20 pF) NOTES:1. The system designer should be aware that the ac tual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed to prevent overflowing the input data buffer. Parameter Symbol Min Max Unit Address setup before HCS and HRD low or HCS and HWR low tias 5- n s Address hold time after HCS and HRD low or HCS and HWR high tiah 5- n s Read Delay between HRD then HCS low or HCS then HRD low t icdr 0- n s Data valid after HCS and HRD low t idd -1 8 n s HCS and HRD low for read t irpw 24 - ns Data hold time after HCS or HRD high t idhr 8- n s Data high-Z after HCS or HRD high t idis -1 8 n s HCS or HRD high to HCS and HRD low for next read t ird 30 - ns HCS or HRD high to HCS and HWR low for next write t irdtw 30 - ns HRD rising to HREQ rising tirdirqhl -1 2 n s Write Delay between HWR then HCS low or HCS then HWR low t icdw 0- n s Data setup before HCS or HWR high t idsu 8- n s HCS and HWR low for write t iwpw 24 - ns Data hold after HCS or HWR high t idhw 8- n s HCS or HWR high to HCS and HRD low for next read t iwtrd 30 - ns HCS or HWR high to HCS and HWR low for next write t iwd 30 - ns HWR rising to HREQ falling tiwrbsyl -1 2 n s

7.4 Protocol and Messages

as determined by commands issued by the host via the message conduit.

7.4.1 Messages

Table 4. HMI messages

CobraNet Hardware User’s Manual Host Management Interface (HMI) DS651UM23 ©Copyright 2005 Cirrus Logic, Inc. 29 Version 2.3 7.4.1.1. Translate Address Translate Address does not actually update the address pointers but initiates the processing required to eventually move them. The host can accomplish other tasks, including HMI Reads and Writes while the address translation is being processed. A logical description of Translate Address is given below. A contextual use of the Translate Address operation is shown in the reference implementations. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on page 34. void TranslateAddress( long address ) int msgack = MSG_D; MSG_A = ( address & 0xff0000 ) >> 16; MSG_B = ( address & 0xff00 ) >> 8; MSG_C = address & 0xff; MSG_D = CVR_TRANSLATE_ADDRESS; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); 7.4.1.2. Interrupt Acknowledge Causes HACK to be de-asserted. void InterruptAck( void ) int msgack = MSG_D; MSG_D = CVR_INTERRUPT_ACK; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); 7.4.1.3. Goto Packet Moves HMI pointers to bridgeRxPktBuffer (write = 0) or bridgeTxPktBuffer (write = 1). void GotoPacket( bool write ) int msgack = MSG_D; MSG_C = write ? MOP_GOTO_PACKET_TRANSMIT : MOP_GOTO_PACKET_RECEIVE; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); 7.4.1.4. Goto Translation Moves HMI data pointers to the results of the most recently completed translate address operation. The write parameter dictates the operation of the HREQ signal and only needs to be supplied for applications using hardware data handshaking via this signal. void GotoTranslation( bool write = 0 ) int msgack = MSG_D; MSG_C = write ? MOP_GOTO_TRANSLATION_WRITE : MOP_GOTO_TRANSLATION_READ; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );

30 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User’s Manual Host Management Interface (HMI) 7.4.1.5. Packet Received Sets bridgeRxPkt = bridgeRxReady thus acknowledging receipt of the packet in bridgeRxPktBuffer. void PacketReceive( void ) int msgack = MSG_D; MSG_C = MOP_PACKET_RECEIVE; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); 7.4.1.6. Packet Transmit Sets bridgeTxPkt = bridgeTxPktDone+1 thus initiating transmission of the contents of bridgeTxPktBuffer. Presumably bridgeTxPktBuffer has been previously written with valid packet data. void PacketTransmit( void ) int msgack = MSG_D; MSG_C = MOP_PACKET_TRANSMIT; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); 7.4.1.7. Goto Counters Moves HMI data pointers to interrupt status variables (beginning at hackStatus). void GotoCounters( void ) int msgack = MSG_D; MSG_C = MOP_GOTO_COUNTERS; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );

7.4.2 Status

page 33 and "HMI Access Code" on page 34. Table 5. HMI status bits

7.4.3 Data

Before accessing data, address setup must be performed. Address setup consists of issuing a Translate Address request, waiting for the request to complete, then issuing a Goto Translation. Pipelining requires that a “garbage read” be performed following an address change. The second word read contains the data for the address requested. No similar pipelining issue exists with respect to write operations. 7.4.3.1. Region length Distance from the original pointer position (as per Translate Address) to the end of the instantiated region. A value of 0 indicates an invalid pointer. 7.4.3.2. Writable Region When set, this bit indicates the address pointer is positioned within a writable region. MI variables may be modified in a writable region by writing data to the data conduit. 7.4.3.3. Translation Complete When set, this bit indicates that the address translator is available (translation results are available and a new translation request may be submitted). This bit is cleared when a Translate Address message is issued and is set when the translation completes. 7.4.3.4. Packet Transmission Complete This bit is cleared when transmission is initiated by issuance of the Transmit Packet message. The bit is set when the packet has been transmitted and the transmit buffer is ready to accept a new packet. 7.4.3.5. Received Packet Available This bit is set when a packet is received into the packet bridge. It is cleared when the packet data is read and receipt is acknowledged by issuance of an Acknowledge Packet Receipt message. Note that Received Packet Available only goes low when there are no longer any pending received packets for the packet bridge. The packet bridge has the capacity to queue multiple packets in the receive direction. 7.4.3.6. Message Togglebit This bit toggles on completion of processing of each message. A safe means for the host to acknowledge processing of messages is as follows: void WaitToggle( void ) int msgack = MSG_D; /* clean pipeline */ msgack = MSG_D; /* record current state of togglebit */ MSG_D = YOUR_COMMAND_HERE; /* issue command */ /* wait for togglebit to flip */ while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );

8.0 HMI Reference Code

The following C code provides examples in using HMI messages, HMI status, and the HMI memory map.

8.1 HMI Definitions

hmi.h CobraNet Host Management Interface example code Definitions $Header$ ** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc. #define MSG_A 0 #define MSG_B 1 #define MSG_C 2 #define MSG_D 3 #define DATA_A 4 #define DATA_B 5 #define DATA_C 6 #define DATA_D 7 #define CONTROL 8 #define STATUS 9 #define CVR_SET_ADDRESS 0xb2 /* Not availbale on CS1810xx/CS4961xx/CM-2. */ /*CM-1 and Reference Design only. */ #define CVR_TRANSLATE_ADDRESS 0xb3 #define CVR_INTERRUPT_ACK 0xb4 #define CVR_MULTIPLEX_OP 0xb5 #define MOP_GOTO_TRANSLATION_READ 0 #define MOP_GOTO_TRANSLATION_WRITE 5 #define MOP_GOTO_PACKET_RECEIVE 1 #define MOP_GOTO_PACKET_TRANSMIT 6 #define MOP_GOTO_COUNTERS 2 #define MOP_PACKET_TRANSMIT 3 #define MOP_PACKET_RECEIPT 4 #define MOP_IDENTIFY 7 #define MSG_TOGGLE_BO 0 #define MSG_RXPACKET_BO 1 #define MSG_TXPACKET_BO 2 #define MSG_TRANSLATION_BO 3 #define MSG_WRITABLE_BO 4 #define MSG_LENGTH_BO 8

8.2 HMI Access Code

hmi.c CobraNet Host Management Interface example code Simple edition $Header$ ** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc. #include "hmi.h" /* variables model HMI state */ long PeekLimit; long PeekPointer = -1; long PokeLimit; long PokePointer = -1; /* access host port hardware */ #define HMI_BASE 0 unsigned char ReadRegister( int hmiregister ) return *(unsigned char volatile *const) ( hmiregister + HMI_BASE ); void WriteRegister( int hmiregister, unsigned char value ) *(unsigned char volatile *const) ( hmiregister + HMI_BASE ) = value; void SendMessage( unsigned char message ) int msgack = ReadRegister( MSG_D ); /* issue (last byte of) message */ WriteRegister( MSG_D, message ); /* wait for acceptance of message */ while( !( ( msgack ^ ReadRegister( MSG_D ) ) & ( 1 << MSG_TOGGLE_BO ) ) ); void SetAddress( long address ) /* translate address */ WriteRegister( MSG_A, ( address & 0xff0000 ) >> 16 ); WriteRegister( MSG_B, ( address & 0xff00 ) >> 8 ); WriteRegister( MSG_C, address & 0xff ); SendMessage( CVR_TRANSLATE_ADDRESS ); /* wait for completion of translate address */

CobraNet Hardware User’s Manual HMI Reference Code DS651UM23 ©Copyright 2005 Cirrus Logic, Inc. 35 Version 2.3 while( !( ReadRegister( MSG_D ) & ( 1 << MSG_TRANSLATION_BO ) ) ); /* goto translation */ WriteRegister( MSG_C, MOP_GOTO_TRANSLATION_READ ); SendMessage( CVR_MULTIPLEX_OP ); /* "garbage" read clears data pipeline */ ReadRegister( DATA_D ); /* maintain local pointers */ PeekPointer = PokePointer = address; PeekLimit = PokeLimit = PeekPointer + ReadRegister( MSG_C ) + ( ReadRegister( MSG_B ) << 8 ); /* read-only region addressed */ if( !( ReadRegister( MSG_A ) & ( 1 << MSG_WRITABLE_BO ) ) ) { PokeLimit = PokePointer; unsigned long Peek( long address ) if( address != PeekPointer ) { SetAddress( address ); if( PeekPointer >= PeekLimit ) { throw "Peek addressing error!"; unsigned long value = ReadRegister( DATA_A ) << 24; value += ReadRegister( DATA_B ) << 16; value += ReadRegister( DATA_C ) << 8; value += ReadRegister( DATA_D ); PeekPointer++; /* maintain local pointer */ return value; void Poke( long address, unsigned long value ) if( address != PokePointer ) { SetAddress( address ); if( PokePointer >= PokeLimit ) { throw "Poke addressing error or read-only!"; WriteRegister( DATA_A, (unsigned char) ( ( value >> 24 ) & 0xff ) ); WriteRegister( DATA_B, (unsigned char) ( ( value >> 16 ) & 0xff ) ); WriteRegister( DATA_C, (unsigned char) ( ( value >> 8 ) & 0xff ) ); WriteRegister( DATA_D, (unsigned char) ( value & 0xff ) ); /* maintain local pointers */ PokePointer++; PeekPointer = -1; /* force SetAddress()next Peek() to freshen data */

8.3 CM-1, CM-2 Auto-detection

The following function is useful for systems that support both the CM-1 and CM-2 or where a CobraNet interface is an optional add-in. Detect() returns 0 if no CobraNet interface module is detected, 1 for CM-1 and 2 for CM-2. int Detect( void ) { /* check for presence of CM-1 */ MSG_B = 0x55; /* write to CM-1 CVR register */ DATA_A = 0xaa; /* write to unused CM-1 register to flip data bus */ if( MSG_B == 0x55 ) { /* read back CVR */ /* redo same detection with different data */ MSG_B = 0x3c; DATA_A = 0xc3; if( MSG_B == 0x3c ) { return 1; /* CM-1 detected */ /* check for presence of CM-2 */ /* issue identify command */ MSG_C = MOP_IDENTIFY; MSG_D = CVR_MULTIPLEX_OP; int msgack = MSG_D; /* clean pipeline */ msgack = MSG_D; /* wait for togglebit to flip in response to command */ int tm0 = gettimeofday(); while( !( ( MSG_D ^ toggle ) & ( 1 << MSG_TOGGLE_BO ) ) ) { int tm1 = gettimeofday(); if( ( tm1 - tm0 ) > time_out ) { return 0; /* command timed out, no CobraNet interface present */ int garbage = MSG_D; /* clean pipeline */ /* verify identify results */ if( DATA_A == 'C' ) if( DATA_B == 'S' ) if( DATA_C == ( 18101 >> 8 ) ) if( DATA_D == ( 18101&0xff ) { return 2; /* CM-2 detected */ return 0; /* no interface or non-supported interface */

9.0 Mechanical Drawings and Schematics

The section contains detailed drawings of the CM-2 board and CS1810xx/CS4961xx device package design. The mechanical drawings are arranged as follows: "CM-2 Module Assembly Drawing, Top" on page 38 "General PCB Dimensions" on page 40 "Example Configuration, Side View" on page 41 "Faceplate Dimensions" on page 42 "Connector Detail" on page 43 "CM-2 RevF Schematic Page 1 of 7" on page 44 "CM-2 RevF Schematic Page 2 of 7" on page 45 "CM-2 RevF Schematic Page 3 of 7" on page 46 "CM-2 RevF Schematic Page 4 of 7" on page 47 "CM-2 RevF Schematic Page 5 of 7" on page 48 "CM-2 RevF Schematic Page 6 of 7" on page 49 "CM-2 RevF Schematic Page 7 of 7" on page 50 "144-Pin LQFP Package Drawing" on page 51

9.1 CM-2 Mechanical Drawings

Figure 18. CM-2 Module Assembly Drawing, Top

Figure 19. CM-2 Module Assembly Drawing, Bottom

Figure 20. General PCB Dimensions 2x Mounting holes for front faceplate. Viewed from component side up.

Figure 21. Example Configuration, Side View

Figure 22. Faceplate Dimensions Note: Mechanical dimensions for the CM-2 and CM-1 Rev F are identical. reference, earlier versions of the CM-1 dimensions are shown in RED.

Figure 23. Connector Detail

9.2 CM-2 Schematics

Figure 24. CM-2 RevF Schematic Page 1 of 7 GPIO[0..1] is not used elsewhere. to keep these signals at valid levels. linear regulator is in fact required.

Figure 25. CM-2 RevF Schematic Page 2 of 7

24.576 MHz VCXO

30.9 Ohm, 1%

LED Filters go close to the connector.

24.9 Ohm, 1%

Figure 26. CM-2 RevF Schematic Page 3 of 7

Figure 27. CM-2 RevF Schematic Page 4 of 7

25 MHz

1 MegOhm

Figure 28. CM-2 RevF Schematic Page 5 of 7 Keep res close to chip pins.

49.9 Ohm, 1%

75 Ohm, 1%

very bad things (i.e., fire, smoke, bad hair days).

Figure 29. CM-2 RevF Schematic Page 6 of 7 Keep res close to chip pins. very bad things (i.e., fire, smoke, bad hair days). The secondary Ethernet MAC and connector are optional. (or removed entirely from a new design based on this circuit).

Figure 30. CM-2 RevF Schematic Page 7 of 7 Note: Similar AC signal return path caps must be included on the motherboard near the connector.

0 Ohm

the front panel of the CM-2. Note: Pull-ups/downs on SSI_DOUT[0..4] are located on the DSP schematic page. tri-stated or not connected. In some situations, these may not be required. SHIELD Place near the Ethernet connectors.

9.3 CS1810xx/CS4961xx Package

Figure 31. 144-Pin LQFP Package Drawing

Controlling dimension is millimeter.
Dimensioning and tolerancing per ASME

9.4 Temperature Specifications

Thermal Coefficient (junction-to-ambient): θja - 38° C / Watt Ambient Temperature Range: 0-70 deg C Junction Temperature Range: 0-125 deg C

CobraNet Hardware User’s Manual

Ordering Information

10.0 Ordering Information

10.1 Device Part Numbers

CS181002-CQ/A1 2x2 Channels 0 °C to +70°C 144-pin LQFP CS181012-CQ/A1 8x8 Channels 0 °C to +70°C 144-pin LQFP CS181022-CQ/A1 16x16 Channels 0 °C to +70°C 144-pin LQFP CS181002-CQZ/A1 2x2 Channels 0 °C to +70°C 144-pin LQFP Lead Free CS181012-CQZ/A1 8x8 Channels 0 °C to +70°C 144-pin LQFP Lead Free CS181022-CQZ/A1 16x16 Channels 0 °C to +70°C 144-pin LQFP Lead Free CS496102-CQZ/A1 2x2 Channels + DSP 0 °C to +70°C 144-pin LQFP Lead Free CS496112-CQZ/A1 8x8 Channels + DSP 0 °C to +70°C 144-pin LQFP Lead Free CS496122-CQZ/A1 16x16 Channels + DSP 0 °C to +70°C 144-pin LQFP Lead Free

10.2 Device Part Numbering Scheme

Figure 32. Device Part Numbering Explanation Note: Go to the Cirrus Logic Internet site at http://www.cirrus. com to find contact information for your local sales representative.

54 ©Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User’s Manual Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are adv ised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rig hts. Cirrus owns the copy- rights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WAR - RANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CR ITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS I N SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EX- PRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES O R PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OT HER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS ' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel, Inc.

Product Information

CS496122-CQZ specifications and overview.

Summary

Digital Audio Networking Processor

Description

Digital Audio Networking Processor

Source title CS496122-CQZ Datasheet(PDF) - Cirrus Logic

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