CS4954 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
lSix DACs providing simultaneous composite, S-video, and RGB or Component YUV outputs lProgrammable DAC output currents for low imped-ance (37.5W ) and high impedance (150W ) loads. lMulti-standard support for NTSC-M, NTSC- JAPAN, PAL (B, D, G, H, I, M, N, Combination N) lITU R.BT656 input mode supporting EAV/SAV codes and CCIR601 Master/Slave input modes lProgrammable HSYNC and VSYNC timing lMultistandard Teletext (Europe, NABTS, WST) support lVBI encoding support lWide-Screen Signaling (WSS) support, EIA-J CPX1204 lNTSC closed caption encoder with interrupt lCS4955 supports Macrovision copy protection Version 7 lHost interface configurable for parallel or I compatible operation lOn-chip voltage reference generator l+3.3 V or +5 V operation, CMOS, low-power modes, tri-state DACs
Description
The CS4954/5 provides full conversion from digital video formats YCbCr or YUV into NTSC and PAL Composite, Y/C (S-video) and RGB, or YUV analog video. Input for- mats can be 27 MHz 8-bit YUV, 8-bit YCbCr, or ITU R.BT656 with support for EAV/SAV codes. Video output can be formatted to be compatible with NTSC-M, NTSC- J, PAL-B,D,G,H,I,M,N, and Combination N systems. Closed Caption is supported in NTSC. Teletext is sup- ported for NTSC and PAL. Six 10-bit DACs provide two channels for an S-Video output port, one or two composite video outputs, and three RGB or YUV outputs. Two-times oversampling re- duces the output filter requirements and guarantees no DAC-related modulation components within the speci- fied bandwidth of any of the supported video standards. Parallel or high-speed I 2C compatible control interfaces are provided for flexibility in system design. The parallel interface doubles as a general purpose I/O port when the CS4954/5 is in I 2C mode to help conserve valuable board area.
ORDERING INFORMATION
APR ‘99 DS278PP4 CLK ISET DGND SCL SDA PDAT[7:0] RD WR ADDR XTAL_OUT VD[7:0] HSYNC VSYNC FIELD INT RESET I2C Interface Host Parallel Interface Color Sub-carrier Synthesizer Video Formatter Control Registers Chroma Modulate Chroma Amplifier Output Interpolate LPF Burst Insert Chroma Interpolate LPF Luma Interpolate Luma Amplifier Sync Insert U,V Y Video Timing Generator TEST Current Reference Voltage Reference VREF RDAC YDAC CVBSDAC C10-Bit DAC S VAA XTAL_IN Teletext EncoderTTXRQ TTXDAT YCbCr to RBG BDAC GDAC 10-Bit 10-Bit 10-Bit 10-Bit 10-Bit RGB RGB Y Y Color Space Converter
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Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com.
8.1.1. I
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- I 30. External Low Pass Filter C
- CHARACTERISTICS AND SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS AC & DC PARAMETRIC SPECIFICATIONS (AGND,DGND = 0 V, all voltages with respect to 0 V) WARNING: Operating beyond these limits can result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND,DGND = 0 V, all voltages with respect to 0 V.) Note: Operation outside the ranges is not recommended. DC CHARACTERISTICS (TA = 25° C; VAA, VDD = 5 V; GNDA, GNDD = 0 V.) Parameter Symbol Min Max Units Power Supply VAA/VDD -0.3 6.0 V Input Current Per Pin (Except Supply Pins) -10 10 mA Output Current Per Pin (Except Supply Pins) -50 +50 mA Analog Input Voltage -0.3 VAA + 0.3 V Digital Input Voltage -0.3 VDD + 0.3 V Ambient Temperature Power Applied -55 + 125 °C Storage Temperature -65 + 150 °C Parameter Symbol Min Typ Max Units Power Supplies: Digital Analog VAA/VDD 3.15 4.75 3.3 5.0 3.45 5.25 V Operating Ambient Temperature TA 0 + 25 + 70 °C Parameter Symbol Min Typ Max Units Digital Inputs High level Input Voltage V [7:0], PDAT [7:0], Hsync/Vsync/Field/CLKIN VIH 2.2 - VDD+0.3 V High Level Input Voltage I2C VIH 0.7 VDD - - V Low level Input Voltage All Inputs - -0.3 - 0.8 V Input Leakage Current - -10 - +10 mA Digital Outputs High Level Output Voltage lo = -4 mA VOH 2.4 - VDD V Low level Output Voltage lo = 4 mA VOL - - 0.4 V Low Level Output Voltage SDA pin only, lo = 6mA VOL - - 0.4 V Output Leakage Current High -Z Digital Outputs - -10 - + 10 mA
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DC CHARACTERISTICS (Continued) Notes: 1. Values are by characterization only 2. Output current levels with ISET = 4 KW , VREF = 1.232 V. 3. DACs are set to low impedance mode 4. DACs are set to high impedance mode 5. Times for black-to-white-level and white-to-black-level transitions. 6. Low-Z - 3 dacs on 7. High-Z - 6 dacs on Parameter Symbol Min Typ Max Units Analog Outputs Full Scale Output Current CVBS/Y/C/R/G/B (Notes 1, 2, 3) IO 32.9 34.7 36.5 mA Full Scale Output Current CVBS/Y/C/R/G/B (Notes 1, 2, 4) IO 8.22 8.68 9.13 mA LSB Current CVBS/Y/C/R/G/B (Notes 1, 2, 3) IB 32.2 33.9 35.7 mA LSB Current CVBS/Y/C/R/G/B (Notes 1, 2, 4) IB 8.04 8.48 8.92 mA DAC-to DAC Matching (Note 1) MAT - 2 - % Output Compliance (Note 1) VOC 0 - + 1.4 V Output Impedance (Note 1) ROUT - 15 - k W Output Capacitance (Note 1) COUT - - 30 pF DAC Output Delay (Note 1) ODEL - 4 12 ns DAC Rise/Fall Time (Note 1, 5) TRF - 2.5 5 ns Voltage Reference Reference Voltage Output VOV 1.170 1.232 1.294 V Reference Input Current (Note 1) UVC - - 10 uA Power Supply Supply Voltage VAA, VDD 3.15 4.75 3.3 5.0 3.45 5.25 V Digital Supply Current IAA1 - 70 - mA Analog Supply Low-Z (Note 6) IAA2 - 100 - mA Analog Supply High-Z (Note 7) IAA3 - 60 - mA Power Supply Rejection Ratio PSRR 0.02 0.05 %/% Static Performance DAC Resolution (Note 1) - - 10 Bits Differential Non-Linearity (Note 1) DNL -1 + 0.5 + 1 LSB Integral Non-Linearity (Note 1) INL - 2 + 1+ 2L S B Dynamic Performance Differential Gain (Note 1) DG - 2 5 % Differential Phase (Note 1) DP - + 0. 5 + 2 ° Hue Accuracy (Note 1) HA - - 2 ° Signal to Noise Ratio SNR 70 - - dB Saturation Accuracy (Note 1) SAT - 1 2 %
Figure 1. Video Pixel Data and Control Port Timing
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Figure 2. I2C Host Port Timing
Figure 3. Reset Timing
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- ADDITIONAL CS4954/5 FEATURES
- Five programmable DAC output combinations, including YUV and second composite
- Optional progressive scan @ MPEG2 field rates
- Stable color subcarrier for MPEG2 systems
- General purpose input and output pins
- Individual DAC power-down capability
- On-chip color bar generator
- Supports RS170A and ITU R.BT601 compos- ite output timing
- HSYNC and VSYNC output in ITU R.BT656 mode
- Teletext encoding selectable on two composite and S-video signals
- Programmable saturation, SCH Phase, hue, brightness and contrast
- Device power-down capability
- Super White and Super Black support 3. CS4954 INTRODUCTION The CS4954/5 is a complete multi-standard digital video encoder implemented in current CMOS tech- nology. The device can operate at 5 V as well as at 3.3 V. ITU R.BT601- or ITU R.BT656-compliant digital video input is converted into NTSC-M, NTSC-J, PAL-B, PAL-D, PAL-G, PAL-H, PAL-I, PAL-M, PAL-N, or PAL-N Argentina-compatible analog video. The CS4954/5 is designed to con- nect, without glue logic, to MPEG1 and MPEG2 digital video decoders. Two 10-bit DAC outputs provide high quality S- Video analog output while another 10-bit DAC si- multaneously generates composite analog video. In addition, there are three more DACs to provide si- multaneous analog RGB or analog YUV outputs. The CS4954/5 will accept 8-bit YCbCr or 8-bit YUV input data. The CS4954/5 is completely configured and con- trolled via an 8-bit host interface port or an I compatible serial interface. This host port provides access and control of all CS4954/5 options and fea- tures, such as closed caption insertion, interrupts, etc. In order to lower overall system costs, the CS4954/5 provides an internal voltage reference that eliminates the requirement for an external, dis- crete, three-pin voltage reference. In ISO MPEG-2 system configurations, the CS4954/5 can be augmented with a common color- burst crystal to provide a stable color subcarrier given an unstable 27 MHz clock input. The use of the crystal is optional, but the facility to connect one is provided for MPEG-2 environments in which the system clock frequency variability is too wide for accurate color sub-carrier generation. 4. FUNCTIONAL DESCRIPTION In the following subsections, the functions of the CS4954/5 will be described. The descriptions refer to the device elements shown in the block diagram on the cover page. 4.1. Video Timing Generator All timing generation is accomplished via a 27 MHz input applied to the CLK pin. The CS4954/5 can also accept a signal from an optional color burst crystal on the XTAL_IN & XTAL_OUT pins. See the section, Color Subcarri- er Synthesizer, for further details. The Video Timing Generator is responsible for or- chestrating most of the other modules in the device. It operates in harmony with external sync input timing, or it can provide external sync timing out- puts. It automatically disables color burst on appro- priate scan lines and automatically generates serration and equalization pulses on appropriate scan lines.
The CS4954/5 is designed to function as a video timing master or video timing slave. In both Master and Slave Modes, all timing is sampled and assert- ed with the rising edge of the CLK pin. In most cases, the CS4954/5 will serve as the video timing master. HSYNC , VSYNC , and FIELD are configured as outputs in Master Mode. HSYNC or FIELD can also be defined as a composite blanking output signal in Master Mode. In Master Mode, the timing of HSYNC , VSYNC , FIELD and Compos- ite Blank (CB) signals is programmable. Exact hor- izontal and vertical display timing is addressed in the Operational Description section. In Slave Mode, HSYNC and VSYNC are typically configured as input pins and are used to initialize independent vertical and horizontal timing genera- tors upon their respective falling edges. HSYNC and VSYNC timing must conform to the ITU- R BT.601 specifications. The CS4954/5 also provides a ITU R.BT656 Slave Mode in which the video input stream contains EAV and SAV codes. In this case, proper HSYNC and VSYNC timing are extracted automatically without any inputs other than the V [7:0]. ITU R.BT656 input data is sampled with the leading edge of CLK. In addition, it is also possible to output HSYNC and VSYNC signals during CCIR-656 Slave Mode. 4.2. Video Input Formatter The Video Input Formatter translates YCbCr input data into YUV information, when necessary, and splits the luma and chroma information for filter- ing, scaling, and modulation. 4.3. Color Subcarrier Synthesizer The subcarrier synthesizer is a digital frequency synthesizer that produces the appropriate subcarri- er frequency for NTSC or PAL. The CS4954/5 generates the color burst frequency based on the CLK input (27 MHz). Color burst accuracy and stability are limited by the accuracy of the 27 MHz input. If the frequency varies, then the color burst frequency will also vary accordingly. For environments in which the CLK input varies or jitters unacceptably, a local crystal frequency refer- ence can be used on the XTAL_IN and XTAL_OUT pins. In this instance, the input CLK is continuously compared with the external crystal ref- erence input and the internal timing of the CS4954/5 is automatically adjusted so that the color burst fre- quency remains within tolerance. Controls are provided for phase adjustment of the burst to permit color adjustment and phase com- pensation. Chroma hue control is provided by the CS4954/5 via a 10-bit Hue Control Register (HUE_LSB and H_MSB). Burst amplitude control is also made available to the host via the 8-bit burst amplitude register (SC_AMP). 4.4. Chroma Path The Video Input Formatter delivers 4:2:2 YUV outputs into separate chroma and luma data paths. The chroma path will be discussed here. The chroma output of the Video Input Formatter is directed to a chroma low-pass 19-tap FIR filter. The filter bandwidth is selected (or the filter can be bypassed) via the CONTROL_1 Register. The passband of the filter is either 650 KHz or 1.3 MHz and the passband ripple is less than or equal to 0.05 dB. The stopband for the 1.3 MHz selection begins at 3 MHz with an attenuation of greater than 35 dB. The stopband for the 650 KHz selection be- gins around 1.1 MHz with an attenuation of greater than 20 dB. The output of the chroma low-pass filter is connect- ed to the chroma interpolation filter in which up- sampling from 4:2:2 to 4:4:4 is accomplished. Following the interpolation filter, the U and V chroma signals pass through two independent vari- able gain amplifiers in which the chroma amplitude
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can be varied via the U_AMP and V_AMP 8-bit host addressable registers. The U and V chroma signals are fed to a quadrature modulator in which they are combined with the output from the subcarrier synthesizer to produce the proper modulated chrominance signal. The chroma then is interpolated by a factor of two in order to operate the output DACs at twice the pixel rate. The interpolated filters enable running the DACs at twice the pixel rate and this helps re- duce the sinx/x roll-off for higher frequencies and reduces the complexity of the external analog low pass filters. 4.5. Luma Path Along with the chroma output path, the CS4954/5 Video Input Formatter initiates a parallel luma data path by directing the luma data to a digital delay line. The delay line is built as a digital FIFO in which the depth of the FIFO replicates the clock period delay associated with the more complex chroma path. Brightness adjustment is also provid- ed via the 8-bit BRIGHTNESS_OFFSET Register. Following the luma delay, the data is passed through an interpolation filter that has a program- mable bandwidth, followed by a variable gain am- plifier in which the luma DC values are modifiable via the Y_AMP Register. The output of the luma amplifier connects to the sync insertion block. Sync insertion is accom- plished by multiplexing, into the luma data path, the different sync DC values at the appropriate times. The digital sync generator takes horizontal sync and vertical sync timing signals and generates the appropriate composite sync timing (including vertical equalization and serration pulses), blank- ing information, and burst flag. The sync edge rates conform to RS-170A or ITU R.BT601 and ITU R.BT470 specifications. It is also possible to delay the luminance signal, with respect to the chrominance signal, by up to three pixel clocks. This variable delay is useful to offset different propagation delays of the luma baseband and modulated chroma signals. This ad- justable luma delay is available only on the CVBS_1 output. 4.6. RGB Path and Component YUV Path The RGB datapath has the same latency as the luma and chroma path. Therefore all six simultaneous analog outputs are synchronized. The 4:2:2 YCbCr data is first interpolated to 4:4:4 and then interpo- lated to 27 MHz. The color space conversion is per- formed at 27 MHz. The coefficients for the color space conversion conform to the ITU R.BT601 specifications. After color space conversion, the amplitude of each component can be independently adjusted via the R_AMP, G_AMP, and B_AMP 8-bit host address- able registers. A synchronization signal can be add- ed to either one, two or all of the RGB signals. The synchronization signal conforms to NTSC or PAL specifications. Some applications (e.g., projection TVs) require analog component YUV signals. The chip provides a programmable mode that outputs component YUV data. Sync can be added to the luminance sig- nal. Independent gain adjustment of the three com- ponents is provided as well. 4.7. Digital to Analog Converters The CS4954/5 provides six discrete 27 MHz DACs for analog video. The default configuration is one 10-bit DAC for S-video chrominance, one 10-bit DAC for S-Video luminance, one 10-bit DAC for composite output, and three 10-bit DACs for RGB outputs. All six DACs are designed for driving ei- ther low-impedance loads (double terminated
75 W ) or high-impedance loads (double terminated
300 W ). There are five different DAC configura- tions to choose from (see Table 1, below). The DACs can be put into tri-state mode via host- addressable control register bits. Each of the six
also provides power shut-off control for the DACs. Each DAC has an associated DAC shut-off bit. current reference pin and electrical ground. rial interface for device configuration and control. Table 1. DAC configuration Modes
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4.12. Teletext Services The CS4954/5 encodes the most common teletext formats, such as European Teletext, World Stan- dard Teletext (PAL and NTSC), and North Ameri- can Teletext (NABTS). Teletext data can be inserted in any of the TV lines (blanking lines as well as active lines). In addition the blanking lines can be individually allocated for Teletext instantiation. The input timing for teletext data is user program- mable. See the section Teletext Services for further details. Teletext data can be independently inserted on ei- ther one or all of the CVBS_1, CVBS_2, or S-video signals. 4.13. Wide-Screen Signaling Support and CGMS Insertion of wide-screen signal encoding for PAL and NTSC standards is supported and CGMS (Copy Generation Management System) for NTSC in Japan. Wide-screen signals are inserted in lines 23 and 336 for PAL, and lines 20 and 283 for NTSC. 4.14. VBI Encoding This chip supports the transmission of control sig- nals in the vertical blanking time interval according to SMPTE RP 188 recommendations. VBI encoded data can be independently inserted into either or all of CVBS_1, CVBS_2 or S-video signals. 4.15. Control Registers The control and configuration of the CS4954/5 is accomplished primarily through the control regis- ter block. All of the control registers are uniquely addressable via the internal address register. The control register bits are initialized during device RESET. See the Programming section of this data sheet for the individual register bit allocations, bit operation- al descriptions, and initialization states. 4.16. Testability The digital circuits are completely scanned by an internal scan chain, thus providing close to 100% fault coverage. 5. OPERATIONAL DESCRIPTION 5.1. Reset Hierarchy The CS4954/5 is equipped with an active low asyn- chronous reset input pin, RESET. RESET is used to initialize the internal registers and the internal state machines for subsequent default operation. See the electrical and timing specification section of this data sheet for specific CS4954/5 device RESET and power-on signal timing requirements and re- strictions. While the RESET pin is held low, the host interface in the CS4954/5 is disabled and will not respond to host-initiated bus cycles. All outputs are valid after a time period following RESET pin low. A device RESET initializes the CS4954/5 internal registers to their default values as described by Ta- ble 9, Control Registers. In the default state, the CS4954/5 video DACs are disabled and the device is internally configured to provide blue field video data to the DACs (any input data present on the V [7:0] pins is ignored at this time). Otherwise, the CS4954/5 registers are configured for NTSC-M ITU R.BT601 output operation. At a minimum, the DAC Registers (0x04 and 0x05) must be written (to enable the DACs) and the IN_MODE bit of the CONTROL_0 Register (0x01) must be set (to en- able ITU R.BT601 data input on V [7:0]) for the CS4954/5 to become operational after RESET.
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layed by thirteen lines or advanced by eighteen lines. VSYNC and FIELD signal timing. ters are set to default values. tive lines of video, plus 21.5 lines of blanking. after 312.5 lines from the beginning of field one. Table 2. Vertical Timing
Figure 6. Vertical Timing
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and continuing through line 261. and continuing through line 309. after 312 lines from the beginning of the first field.
27 MHz active CbYCrY data, with start- and end-
Figure 7. NTSC Video Interlaced Timing
R.BT656 input timing is illustrated in Figure 11. chronize to these timing signals. Figure 8. PAL Video Interlaced Timing
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Figure 9. NTSC Video Non-Interlaced Progressive Scan Timing Figure 10. PAL Video Non-Interlaced Progressive Scan Timing
IN_MODE bit in the CONTROL_0 Register.
27 MHz CbYCrY source as input on the V [7:0]
ter or slave and ITU-R.BT656. registers with the values shown in Table 3.
1440 Clocks
268 Clocks (NTSC)
280 Clocks (PAL)
4 Clocks
Figure 11. CCIR656 Input Mode Timing
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in selecting a suitable clock source. subcarrier synthesis process. insertion on lines 21 and 284 independently. then enable closed caption insertion and interrupts. then clear the interrupt and wait for the next field. 244, and 264 for NTSC and PAL respectively. Table 4. Multi-standard Format Register Configurations
H-sync can be delayed by a full line, in 74 nsec in- tervals. V-sync can be shifted in both directions in time. The default values are 18 and 23 for NTSC and PAL respectively. Since the V-sync register is 5 bits wide (Sync Register 0), the V-sync pulse can be shifted by 31 lines in total. V-sync can preceed by a maximum of 18 lines (NTSC) or 23 lines (PAL) respectively from its de- fault location, and V-sync can follow by a maxi- mum of 13 lines (NTSC) or 8 lines (PAL) from its default location. 5.10. Wide Screen Signaling (WSS) and CGMS Wide screen signaling support is provided for NTSC and for PAL standards. Wide screen signal- ing is currently used in most countries with 625 line systems as well as in Japan for EDTV-II applica- tions. For complete description of WSS standard, please refer to ITU-R BT.1119 (625 line system) and to EIAJ CPX1204 for the Japanese 525 line system. The wide screen signal is transferred in a blanking line of each video field (NTSC: lines 20 and 283, PAL: lines 23 and 336). Wide screen signaling is enabled by setting WW_23 to “1”. Some countries with PAL standard don’t use line 336 for wide screen signaling (they use only line 23), therefore we provide another enable bit (WSS_22) for that particular line. There are 3 registers dedicated to contain the trans- mitted WSS bits (WSS_REG_0, WSS_REG_1, WSS_REG_2). The data insertion into the appro- priate lines are performed automatically by this de- vice. The run-in and start code bits do not have to be loaded into this device, it automatically inserts the correct code at the beginning of transfer. 5.11. Teletext Support This chip supports several teletext standards, like European teletext, NABTS (North American tele- text), and WST (World Standard Teletext) for NTSC and PAL. All these teletext standards are defined in the ITU- R BT.653-2 document. The European teletext is defined as “teletext system B” for 625/50 Hz TV systems. NABTS teletext is defined as “teletext system C” for 525/60 Hz TV systems. WST for PAL is defined as “teletext system D” for 624/50 Hz TV systems and WST for NTSC is de- fined as “teletext system D” for 525/60 Hz TV systems. This chip provides independant teletext encoding into composite 1, composite 2 and s-video signals. The teletext encoding into these various signals is software programmable. In teletext pulsation mode, (TTX_WINDOW=0), register 0×31 bit 3, the pin TTXDAT receives a teletext bitstream sampled at the 27 Mhz clock. At each rising edge of the TTXRQ output signal a sin- gle teletext bit has to be provided after a program- mable input delay at the TTXDAT input pin. Phase variant interpolation is achieved on this bit- stream in the internal teletext encoder, providing sufficient small phase jitter on the ouput text lines. TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of the bitstream at indepenantly selectable lines for both TV fields. The internal insertion win- dow for text is set to either 360, 296 or 288 teletext bits, depending on the selected teletext standard. The clock run-in is included in this window. Teletext in enabled by setting the TTX_EN bit to “1”. The TTX_WST bit in conjunction with the TV_FORMAT register select one of the 4 possible teletext encoding possibilities. The teletext timing is shown in the Figure 12. TTXHS and TTXHD are user programmable and
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when sending teletext data to this device. for more detailed information. (5.727272 Mbit/sec) (WST NTSC) respectively. tively disable the teletext insertion on single lines. TTX_LINE_DIS3 registers appropriately. Figure 12. Teletext Timing (Pulsation Mode) Figure 13. Teletext Timing (Window Mode)
to the ITU R.BT653-2 specifications. TTXDAT pin are valid (see Figure 13). VSYNC pins for the color bars to be displayed. luma and chroma values are listed in Table 6. . 283 are used for the transmission of ancillary data. Table 5. Teletext timing parameters Table 6. Internal Color Bar Values (8-bit values, Cb/Cr
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digital input signal and the analog output voltage. form to the ITU-R BT.601 specifications.
- Each interrupt can be individually disabled
with a disable, it must be cleared. pins for the GPIO_DATA_REG Register (0×0A). detection of address 0×0A can happen in two ways. Table 7. VBI Encoding Signal Amplitudes
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Figure 18. Chrominance output interpolation filter Figure 19. Luminance interpolation filter transfer char- Figure 20. Luminance interpolation filter transfer char- Figure 21. Chrominance interpolation filter transfer
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- ANALOG 7.1. Analog Timing All CS4954/5 analog timing and sequencing is de- rived from 27 MHz clock input. The analog outputs are controlled internally by the video timing genera- tor in conjunction with master and slave timing. The video output signals perform accordingly for NTSC and PAL specifications. Being that the CS4954/5 is almost entirely a digital circuit, great care has been taken to guarantee ana- log timing and slew rate performance as specified in the NTSC and PAL analog specifications. Refer- ence the Analog Parameters section of this data sheet for exact performance parameters. 7.2. VREF The CS4954/5 can operate with or without the aid of an external voltage reference. The CS4954/5 is designed with an internal voltage reference genera- tor that provides a VREFOUT signal at the VREF pin. The internal voltage reference is utilized by not making a connection to the VREF pin. The VREF pin can also be connected to an external precision 1.232 volt reference, which then overrides the in- ternal reference. 7.3. ISET All six of the CS4954/5 digital to analog converter DACs are output current normalized with a com- mon ISET device pin. The DAC output current per bit is determined by the size of the resistor connect- ed between ISET and electrical ground. Typically a 4K W , 1% metal film resistor should be used. The ISET resistance can be changed by the user to ac- commodate varying video output attenuation via post filters and also to suit individual preferred per- formance. In conjunction with the ISET value, the user can also independently vary the chroma, luma and col- orburst amplitude levels via host addressable con- trol register bits that are used to control internal digital amplifiers. The DAC output levels are de- fined by the following operations: VREF/RISET = IREF CVBS/Y/C/R/G/B outputs in low impedance mode: VOUT (max) = IREF*(16/145)*1023*37.5 W = 1.304V CVBS/Y/C/R/G/B outputs in high impedance mode: VOUT (max) = IREF*(4/145)*1023*150W =1 . 3 0 4V 7.4. DACs The CS4954/5 is equipped with six independent, video-grade, current-output, digital-to-analog con- verters (DACs). They are 10-bit DACs operating at a 27 MHz two-times-oversampling rate. All six DACs are disabled and default to a low power mode upon RESET. Each DAC can be individually powered down and disabled. The output-current- per-bit of all six DACs is determined by the size of the resistor connected between the ISET pin and electrical ground. 7.4.1. Luminance DAC The Y pin is driven from a 10-bit 27 MHz current output DAC that internally receives the Y, or lumi- nance portion, of the video signal (black and white only). Y is designed to drive proper video levels into a 37.5W load. Reference the detailed electrical section of this data sheet for the exact Y digital to analog AC and DC performance data. A EN_L en- able control bit in the Control Register 5 (0×05) is provided to enable or disable the luminance DAC. For a complete disable and lower power operation the luminance DAC can be totally shut down via the SVIDLUM_PD control bit in the Control Regis- ter 4 (0×04). In this mode, turn-on through the con- trol register will not be instantaneous. 7.4.2. Chrominance DAC The C pin is driven from a 10-bit 27 MHz current output DAC that internally receives the C or
chrominance portion of the video signal (color only). C is designed to drive proper video levels into a 37.5W load. Reference the detailed electrical section of this data sheet for the exact C digital to analog AC and DC performance data. A EN_C en- able control register bit in the Control Register 1 (0×05) is provided to enable or disable the chromi- nance DAC. For a complete disable and lower power operation the chrominance DAC can be to- tally shut down via the SVIDCHR_PD register bit in the Control Register 4 (0×04). In this mode turn- on through the control register will not be instanta- neous. 7.4.3. CVBS DAC The CVBS pin is driven from a 10-bit 27 MHz cur- rent output DAC that internally receives a com- bined luma and chroma signal to provide composite video output. CVBS is designed to drive proper composite video levels into a 37.5W load. Reference the detailed electrical section of this data sheet for the exact CVBS digital to analog AC and DC performance data. The EN_COM enable con- trol register bit, in Control Register 1 (0×05), is provided to enable or disable the output pin. When disabled, there is no current flow from the output. For a complete disable and lower power operation, the CVBS37 DAC can be totally shut down via the COMDAC_PD control register bit in Control Register 4 (0×04). In this mode turn-on through the control register will not be instantaneous. 7.4.4. Red DAC The Red pin is driven from a 10-bit 27 MHz current output DAC that internally receives a combined luma and chroma signal to provide composite vid- eo output. Red is designed to drive proper compos- ite video levels into a 37.5W load. Reference the detailed electrical section of this data sheet for the exact red digital to analog AC and DC performance data. The EN_R enable control register bit, in Con- trol Register 1 (0×05), is provided to enable or dis- able the output pin. When disabled, there is no current flow from the output. For a complete dis- able and lower power operation, the red DAC can be totally shut down via the R_PD control register bit in Control Register 4 (0×04). In this mode turn- on through the control register will not be instanta- neous. 7.4.5. Green DAC The green pin is driven from a 10-bit 27 MHz cur- rent output DAC that internally receives a com- bined luma and chroma signal to provide composite video output. Green is designed to drive proper composite video levels into a 37.5W load. Reference the detailed electrical section of this data sheet for the exact green digital to analog AC and DC performance data. The EN_G enable control register bit, in Control Register 1 (0×05), is provid- ed to enable or disable the output pin. When dis- abled, there is no current flow from the output. For a complete disable and lower power operation, the green DAC can be totally shut down via the G_PD control register bit in Control Register 4 (0×04). In this mode turn-on through the control register will not be instantaneous. 7.4.6. Blue DAC The blue pin is driven from a 10-bit 27 MHz cur- rent output DAC that internally receives a com- bined luma and chroma signal to provide composite video output. Blue is designed to drive proper composite video levels into a 37.5W load. Reference the detailed electrical section of this data sheet for the exact blue digital to analog AC and DC performance data. The EN_B enable control register bit, in Control Register 5 (0×05), is provid- ed to enable or disable the output pin. When dis- abled, there is no current flow from the output. For a complete disable and lower power operation, the blue DAC can be totally shut down via the B_PD control register bit in Control Register 4 (0×04). In this mode turn-on through the control register will not be instantaneous.
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4 kW must be connected to the ISET pin. analog video specifications for NTSC and PAL. rectly drive a television input. power down (see CONTROL_4 register). work in Slave Mode only - it is not a bus master. Table 8. Maximum DAC NumbersSDA Figure 26. I2C Protocol
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extend from internal address 0×00 through 0×5A. Macrovision ACP-PPV Licensed Buyers. Figure 29. 8-bit Parallel Host Port Timing: Address Write Cycle Table 9. Control Registers
Table 9. Control Registers (Continued)
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Address 0 ×00 CONTROL_0 Read/Write Default Value = 01h Control Register 1 Address 0 ×01 CONTROL_1 Read/Write Default Value = 02h Bit Number 76543210 Bit Name TV_FMT MSTR CCIR656 PROG IN_MODE CBCR_UV Default 00000001 Bit Mnemonic Function 7:5 TV_FMT selects the TV display format 000: NTSC-M CCIR601 timing (default) 001: NTSC-M RS170A timing 010: PAL-B, D, G, H, I 011: PAL-M 100: PAL-N (Argentina) 101: PAL-N (non Argentina) 110-111: reserved 4M S T R 1 = Master Mode, 0 = Slave Mode 3 CCIR656 video input is in ITU R.BT656 format (0 = off, 1 = on) 2P R O G Progressive scanning enable (enable = 1)
1 IN_MODE Input select (0 = solid background, 1 = use V [7:0] data)
0 CBCR_UV enable YCbCr to YUV conversion (1 = enable, 0 = disable)
Bit Name LUM DEL CH BW LPF_ON RGB_BW FLD PED CBCRSEL Default 00000010 Bit Mnemonic Function 7:6 LUM DEL luma delay on the composite1 output 00: no delay (default) 01: 1 pixel clock delay 10: 2 pixel clock delay 11: 3 pixel clock delay 5 CH BW chroma lpf bandwidth (0 = 650 kHz, 1 = 1.3 Mhz) 4L P F ON chroma lpf on/off (0 = off, 1 = on) 3R G B _ B W 0 = Full bandwidth on RGB, 1 = BW reduced to 2.5 MHz (3 dB point) (default 0) 2F L D _ P O L Polarity of Field (0: odd field = 0,1: odd field = 1) 1 PED Pedestal offset (0: 0 IRE, 1: 7.5 IRE)
0 CBCRSEL CbCr select (0 = chroma undelayed, 1 = chroma delayed by one clock)
Address 0 ×02 CONTROL_2 Read/Write Default Value = 00h Bit Number 76543210 Bit Name OUTPUT FORMAT TTX WST TTX EN SYNC_DLY XTAL SC_EN Default 00000000 Bit Mnemonic Function 7:5 OUTPUT FORMAT selects the output through the DACs 000 : rgb, s-video, composite1 (6 DACs) (default) 001 : yuv, s-video, composite1 (6 DACs) 010 : s-video, composite1, composite2, (4 DACs) 011 : rgb, composite1, composite2 (5 DACs) 100 : yuv, composite1, composite2 (5 DACs) 101-111: don’t care
4 TTX WST
To select between world standard (NTSC), world standard (PAL), or north american teletext standard during NTSC or PAL modes (1 = WST TTX) (default is 0) In NTSC-M or PAL-M mode. This bit works in conjunction with the TV FORMAT register. 0: NABTS, if TV FORMAT is NTSC or PAL-M 1: WST (NTSC), if TV FORMAT is NTSC or PAL-M 0: Europe TTX, if TV FORMAT is PAL-B, G..., N 1: WST (PAL), if TV FORMAT is PAL-B, G, ..., N
3 TTX EN Enable teletext process (1 = enable)
2 SYNC DLY Slave mode 1 pixel sync delay (1 = enable)
1X T A L Crystal oscillator for subcarrier adjustment enable (1 = enable) 0B U DIS Chroma burst disable (1 = disable)
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Address 0 ×03 CONTROL_3 Read/Write Default Value = 00h Control Register 4 Address 0 ×04 CONTROL_4 Read/Write Default Value = 3Fh Bit Number 76543210 Bit Name RESERVED FD THR C1 FD THR C2 FD THR SV FD THR EN CBAR Default 00000000 Bit Mnemonic Function 7:5 - reserved 4F D THR C1 feedthrough enabled for composite 1 output (0 = off, 1 = on) 3F D THR C2 feedthrough enabled for composite 2 output (0 = off, 1 = on) 2F D THR SV feedthrough enabled for s-video (on luma signal) (0 = off, 1 = on) 1F D THR_EN Enable (1 = enable) input to feed through during inactive lines
0 CBAR internal color bar generator (0 = off, 1 = on)
Bit Name CB_H_SEL CB_FLD_SEL COMDAC_PD SVIDLUM_PD SVIDCHR_PD R_PD G_PD B_PD Default 00111 1 1 1 Bit Mnemonic Function
7 CB_H_SEL Composite Blank / HSYNC output select (1 = CB select, 0 = HSYNC select)
6 CB_FLD_SEL Composite Blank / FIELD output select (1 = CB select, 0 = HSYNC select)
5 COMDAC_PD
0: power up, 1: power down
4 SVIDLUM_PD
power down luma s-video DAC 0: power up, 1: power down
3 SVIDCHR_PD
power down chroma s-video DAC 0: power up, 1: power down 2R _ P D power down red rgb video DAC 0: power up, 1: power down 1G _ P D power down green rgb video DAC 0: power up, 1: power down 0B _ P D power down blue rgb video DAC 0: power up, 1: power down
Address 0 ×05 CONTROL_5 Read/Write Default Value = 00h Control Register 6 Address 0 ×06 CONTROL_6 Read/Write Default Value = 00h Bit Number 76543210 Bit Name RSVD LOW IMP EN COM EN LE N CE N RE N GE N B Default 00000000 Bit Mnemonic Function 7- reserved 6L O W IMP selects between high output impedance (0) or low output impedance (1) mode of DACs 5E N COM enable DAC for composite output 0: tri-state, 1: enable 4E N L enable s-video DAC for luma output 0: tri-state, 1: enable 3E N C enable s-video DAC for chroma output 0: tri-state, 1: enable 2E N _ R enable rgb video DAC for red output 0: tri-state, 1: enable 1E N _ G enable rgb video DAC for green output 0: tri-state, 1: enable 0E N _ B enable rgb video DAC for blue output 0: tri-state, 1: enable Bit Number 76543210 Bit Name 656 SYNC OUT CLIP OFF TTXEN COM2 TTXEN COM1 TTXEN SVID BSYNC DIS GSYNC DIS RSYNC DIS Default 00000000 Bit Mnemonic Function 7 656 SYNC OUT Enable (=1) output of hsync and vsync in the ITU R.BT656 mode 6C L I P OFF Clipping input signals disable (0: clipping active 1: no clipping)
5 TTXEN COM2 Enable teletext at the composit2 output (0: disable teletext, 1 : enable teletext)
4 TTXEN COM1 Enable teletext at the composit1 output ( 0: disable teletext, 1 : enable teletext)
3 TTXEN SVID Enable teletext at the s-video output ( 0: disable teletext, 1: enable teletext)
2 BSYNC DIS Disable syncs in the blue or v output (0: enable syncs, 1: disable syncs)
1 GSYNC DIS Disable syncs in the green or u output ( 0: enable syncs, 1: disable syncs)
0 RSYNC DIS Disable syncs in the red or y output (0: enable syncs, 1: disable syncs)
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Address 0 ×08 BKG_COLOR Read/Write Default Value = 03h GPIO Control Register Address 0 ×09 GPIO__REG Read/Write Default Value = 00h GPIO Data Register Address 0 ×0A GPIO_REG Read/Write Default Value = 00h Sync Register 0 Address 0 ×0D Sync_0 Read/Write Default Value = 90h Bit Number 76543210 Bit Name BG Default 00000011 Bit Mnemonic Function 7:0 BG Background color (7:5 = R, 4:2 = G, 1:0 = B) (default is 0000 0011 - blue) Bit Number 76543210 Bit Name GPR_CNTRL Default 00000000 Bit Mnemonic Function 7:0 GPR CNTRL Input(0)/output(1) control of GPIO registers (bit 0: PDAT(0), bit 7: PDAT(7)) Bit Number 76543210 Bit Name GPIO REG Default 00000000 Bit Mnemonic Function 7:0 GPIO REG GPIO data register ( data is output on PDAT bus if appropriate bit in address 09 is set to “1”, otherwise data is input/output through I2C)- This register is only accessible in I2C mode. Bit Number 76543210 Bit Name PROG VS[4:0] PROG HS[10:8] Default 10010000 Bit Mnemonic Function 7:3 PROG VS[4:0] programmable vsync lines 2:0 PROG HS[10:8] programmable hsync pixels (3 most significant bits)
Address 0 ×0E Sync_1 Read/Write Default Value = F4h I2C Address Register Address 0 ×0F I 2C_ADR Read/Write Default Value = 00h Subcarrier Amplitude Register Address 0 ×10 SC_AMP Read/Write Default Value = 1Ch Subcarrier Synthesis Register Address 0 ×11 SC_SYNTH0 Read/Write Default Value = 3Eh 0×12 SC_SYNTH1 F8h 0×13 SC_SYNTH2 E0h 0×14 SC_SYNTH3 43h Bit Number 76543210 Bit Name PROG HS[7:0] Default 11110100 Bit Mnemonic Function 7:0 PROG HS[7:0] programmable hsync pixels lsb Bit Number 76543210 Bit Name RESERVED I2C ADR Default 00000000 Bit Mnemonic Function 7- reserved 6:0 I2C I2C device address (programmable) Bit Number 76543210 Bit Name BU AMP Default 00011100 Bit Mnemonic Function 7:0 BU AMP Color burst amplitude Register Bits Mnemonic Function SC_SYNTH0 7:0 CC 0 Subcarrier synthesis bits 7:0 SC_SYNTH1 7:0 CC 1 Subcarrier synthesis bits 15:8 SC_SYNTH2 7:0 CC 2 Subcarrier synthesis bits 23:16 SC_SYNTH3 7:0 CC 3 Subcarrier synthesis bits 31:24
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Address 0 ×15 HUE_LSB Read/Write Default Value = 00h Hue MSB Adjust Register Address 0 ×16 HUE_MSB Read/Write Default Value = 00h SCH Sync Phase Adjust Address 0 ×17 SCH Read/Write Default Value = 00h Closed Caption Enable Register Address 0 ×18 CC_EN Read/Write Default Value = 00h Bit Number 76543210 Bit Name HUE LSB Default 00000000 Bit Mnemonic Function 7:0 HUE LSB 8 LSBs for hue phase shift Bit Number 76543210 Bit Name RESERVED MSB Default 00000000 Bit Mnemonic Function 7:2 - reserved 1:0 HUE MSB 2 MSBs for hue phase shift Bit Mnemonic Function 7:0 SCH Default - 00h in increments of »1.4 degree per bit up to 360° Bit Number 765432 1 0 Bit Name RESERVED EN_284 EN_21 Default 000000 0 0 Bit Mnemonic Function 7:2 - reserved
1 CC EN[1] enable closed caption for line 284
0 CC EN[0] enable closed caption for line 21
Closed Caption Data Register Address 0 ×19 CC_21_1 Read/Write Default Value = 00h 0×1A CC_21_2 00h 0×1B CC_284_1 00h 0×1C CC_284_2 00h Wide Screen Signaling Register 0 Address 0 ×1E WSS_REG_0 Read/Write Default Value = 00h Bit Mnemonic Function 7:0 CC_21_1 first closed caption databyte of line 21 7:0 CC_21_2 second closed caption databyte of line 21 7:0 CC_284_1 first closed caption databyte of line 284 7:0 CC_284_2 second closed caption databyte of line 284 Bit Number 765432 1 0 Bit Name WSS_23 WSS_22 WSS_21 WSS_20 WSS_19 WSS_18 WSS_17 WSS_16 Default 000000 0 0 Bit Mnemonic Function
7 WSS_23 Enable wide screen signalling (enable =1)
6 WSS_22
PAL: enable WSS (enable = 1) on line 23 of field 2, NTSC: don’t care
5 WSS_21 PAL: group 4, bit 13, NTSC: don’t care
4 WSS_20 PAL: group 4, bit 12, NTSC: don’t care
3 WSS_19 PAL: group 4, bit 11, NTSC: bit 20
2 WSS_18 PAL: group 3, bit 10, NTSC: bit 19
1 WSS_17 PAL: group 3, bit 9, NTSC: bit 18
0 WSS_16 PAL: group 3, bit 8, NTSC: bit 17
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W ide Screen Signalling Register 1 Address 0 ×1F WSS_REG_1 Read/Write Default Value = 00h Wide Screen Signalling Register 2 Address 0 ×20 WSS_REG_2 Read/Write Default Value = 00h Filter Register 0 Address 0 ×22 CB_AMP Read/Write Default Value = 80h Bit Number 765432 1 0 Bit Name WSS_15 WSS_14 WSS_13 WSS_12 WSS_11 WSS_10 WSS_9 WSS_8 Default 000000 0 0 Bit Mnemonic Function
7 WSS_15 PAL: group 2, bit 7, NTSC: bit 16
6 WSS_14 PAL: group 2, bit 6, NTSC: bit 15
5 WSS_13 PAL: group 2, bit 5, NTSC: bit 14
4 WSS_12 PAL: group 2, bit 4, NTSC: bit 13
3 WSS_11 PAL: group 1, bit 3, NTSC: bit 12
2 WSS_10 PAL: group 1, bit 2, NTSC: bit 11
1 WSS_9 PAL: group 1, bit 1, NTSC: bit 10
0 WSS_8 PAL: group 1, bit 0, NTSC: bit 9
Bit Name WSS_7 WSS_6 WSS_5 WSS_4 WSS_3 WSS_2 WSS_1 WSS_0 Default 000000 0 0 Bit Mnemonic Function
7 WSS_7 PAL: don’t care, NTSC: bit 8
6 WSS_6 PAL: don’t care, NTSC: bit 7
5 WSS_5 PAL: don’t care, NTSC: bit 6
4 WSS_4 PAL: don’t care, NTSC: bit 5
3 WSS_3 PAL: don’t care, NTSC: bit 4
2 WSS_2 PAL: don’t care, NTSC: bit 3
1 WSS_1 PAL: don’t care, NTSC: bit 2
0 WSS_0 PAL: don’t care, NTSC: bit 1
Bit Name U_AMP Default 10000000 Bit Mnemonic Function 7:0 U_AMP U(Cb) amplitude coefficient
Address 0 ×23 CR_AMP Read/Write Default Value = 80h Filter Register 2 Address 0 ×24 Y_AMP Read/Write Default Value = 80h Filter Register 3 Address 0 ×25 R_AMP Read/Write Default Value = 80h Filter Register 4 Address 0 ×26 G_AMP Read/Write Default Value = 80h Bit Number 76543210 Bit Name V_AMP Default 10000000 Bit Mnemonic Function 7:0 V_AMP V(Cr) amplitude coefficient Bit Number 76543210 Bit Name Y_AMP Default 10000000 Bit Mnemonic Function 7:0 Y_AMP Luma amplitude coefficient Bit Number 76543210 Bit Name R_AMP Default 10000000 Bit Mnemonic Function 7:0 R_AMP Red amplitude coefficient Bit Number 76543210 Bit Name G_AMP Default 10000000 Bit Mnemonic Function 7:0 G_AMP Green amplitude coefficient
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Address 0 ×27 B_AMP Read/Write Default Value = 80h Filter Register 6 Address 0 ×28 Bright_Offsett Read/Write Default Value = 00h Teletext Register 0 Address 0 ×29 TTXHS Read/Write Default Value = A1h Teletext Register 1 Address 0 ×2A TTXHD Read/Write Default Value = 02h Bit Number 76543210 Bit Name B_AMP Default 10000000 Bit Mnemonic Function 7:0 B_AMP Blue amplitude coefficient Bit Number 76543210 Bit Name BRIGHTNESS_OFFSET Default 00000000 Bit Mnemonic Function 7:0 BRGHT_OFFSET Brightness adjustment ( range: -128 to +127) Bit Number 76543210 Bit Name TTXHS Default 10100001 Bit Mnemonic Function 7:0 TTXHS Start of teletext request pulses or start of window Bit Number 76543210 Bit Name TTXHD Default 00000010 Bit Mnemonic Function 7:0 TTXHD If TTX_WINDOW = 0 then this register is used as the Pipeline delay between TTXRQ and TTXDAT signal in the teletext source. User programmable delay step of 37 ns per LSB. If TTX_WINDOW = 1 then this register is used as the 8 LSBs of the teletext insertion windows; the 3 MSBs are located in register 0×31. (register 0×31 bit 3)
Address 0 ×2B TTXOVS Read/Write Default Value = 00h Teletext Register 3 Address 0 ×2C TTXOVE Read/Write Default Value = 00h Teletext Register 4 Address 0 ×2D TTXEVS Read/Write Default Value = 00h Teletext Register 5 Address 0 ×2E TTXEVE Read/Write Default Value = 00h Bit Number 76543210 Bit Name TTXOVS Default 00000000 Bit Mnemonic Function 7:0 TTXOVS Start of teletext line window in odd field Bit Number 76543210 Bit Name TTXOVE Default 00000000 Bit Mnemonic Function 7:0 TTXOVE End of teletext line window in odd field Bit Number 76543210 Bit Name TTXEVS Default 00000000 Bit Mnemonic Function 7:0 TTXEVS Start of teletext line window in even field Bit Number 76543210 Bit Name TTXEVE Default 00000000 Bit Mnemonic Function 7:0 TTXEVE End of teletext line window in even field
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Address 0 ×2F TTX_DIS1 Read/Write Default Value = 00h Teletext Register 7 Address 0 ×30 TTX_DIS2 Read/Write Default Value = 00h Teletext Register 8 Address 0 ×31 TTX_DIS3 Read/Write Default Value = 00h Bit Number 76543210 Bit Name TTX_LINE_DIS1 Default 00000000 Bit Mnemonic Function 7:0 TTX_LINE_DIS1 Teletext disable bits corresponding to the lines 5-12 respectively, (11111111=all eight lines are disabled), (MSB is for line 5, LSB is for line 12) Bit Number 76543210 Bit Name TTX_LINE_DIS2 Default 00000000 Bit Mnemonic Function 7:0 TTX_LINE_DIS2 Teletext disable bits corresponding to the lines 13-20 respectively, (11111111=all eight lines are disablled, (MSB is for line 13, LSB is for line 20) Bit Number 765 4 3 210 Bit Name TTXHD RESERVED TTX_WINDOW TTX_LINE_DIS3 Default 000 0 0 000 Bit Mnemonic Function 7:5 TTXHD If TTX_WINDOW = 0 these 3 bits are unused. If TTX_WINDOW = 1 these 3 bits are the MSBs of the register 0×2A; they are used to specify the length of the teletext insertion window
4 Reserved
3 TTX_WINDOW Selects between TTXRQ (= 0) pulsation or TTXRQ (= 1) Window mode
2:0 TTX_LINE_DIS3 Teletext disable bits corresponding to the lines 13-20 respectively, (111=all three lines are disabled), (MSB is for line 21, LSB is for line 23)
Address 0 ×32 INT_EN Read/Write Default Value = 00h Interrupt Register 1 Address 0 ×33 INT_CLR Read/Write Default Value = 00h Status Register 0 Address 0 ×34 STATUS_0 Read Only Default Value = 00h Status Register 1 Address 0 ×5A STATUS_1 Read only Default Value = 04h Bit Number 76543 2 1 0 Bit Name RESERVED INT_21_EN INT_284_EN INT_V_EN Default 00000 0 0 0 Bit Mnemonic Function 7:3 - reserved
2 INT_21_EN interrupt enable for closed caption line 21
1 INT_284_EN interrupt enable for closed caption line 284
0I N T _ V _ E N interrupt enable for new video field Bit Number 76543 2 1 0 Bit Name RESERVED CLR_INT_21 CLR_INT_284 CLR_INT_V Default 00000 0 0 0 Bit Mnemonic Function 7:3 - reserved
2 CLR_INT_21 clear interrupt for closed caption line 21 (INT 21)
1 CLR_INT_284 clear interrupt for closed caption line 284 (INT_284)
0 CLR_INT_V clear interrupt for new video field (INT_V)
Bit Number 543 2 : 0 Bit Name INT_21 INT_284 INT_V FLD Default 000 0 Bit Mnemonic Function 5I N T _ 2 1 Interrupt flag for line 21 (closed caption) complete
4 INT_284 Interrupt flag for line 284 (closed caption) complete
3I N T _ V Interrupt flag for video field change 2:0 FLD_ST Field Status bits(001 = field 1,000 = field 8) Bit Number 76543210 Bit Name DEVICE_ID Default 00000100 Bit Mnemonic Function 7:0 DEVICE_ID Device identification: CS4954: 0000 0100, CS4955: 0000 0101
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- BOARD DESIGN AND LAYOUT CONSIDERATIONS The printed circuit layout should be optimized for lowest noise on the CS4954/5 placed as close to the output connectors as possible. All analog supply traces should be as short as possible to minimize in- ductive ringing. A well designed power distribution network is es- sential in eliminating digital switching noise. The ground planes must provide a low-impedance re- turn path for the digital circuits. A PC board with a minimun of four layers is recommended. The ground layer should be used as a shield to isolate noise from the analog traces. The top layer (1) should be reserved for analog traces but digital traces can share this layer if the digital signals have low edge rates and switch little current or if they are separated from the analog traces by a signigicant distance (dependent on their frequency content and current). The second layer should then be the ground plane followed by the analog power plane on layer three and the digital signal layer on layer four. 9.1. Power and Ground Planes The power and ground planes need isolation gaps of at least 0.05" to minimize digital switching noise effects on the analog signals and components. A split analog/digital ground plane should be con- nected at one point as close as possible to the CS4954/5. 9.2. Power Supply Decoupling Start by reducing power supply ripple and wiring harness inductance by placing a large (33-100 uF) capacitor as close to the power entry point as pos- sible. Use separate power planes or traces for the digital and analog sections even if they use the same supply. If necessary, further isolate the digital and analog power supplies by using ferrite beads on each supply branch followed by a low ESR capac- itor. Place all decoupling caps as close as possible the the device as possible. Surface mount capacitors generally have lower inductance than radial lead or axial lead components. Surface mount caps should be place on the component side of the PCB to min- imize inductance caused by board vias. Any vias, especially to ground, should be as large as possible to reduce their inductive effects. 9.3. Digital Interconnect The digital inputs and outputs of the CS4954/5 should be isolated from the analog outputs as much as possible. Use separate signal layers whenever possible and do not route digital signals over the analog power and ground planes. Noise from the digital section is related to the digi- tal edge rates used. Ringing, overshoot, under- shoot, and ground bounce are all related to edge rate. Use lower speed logic such as HCMOS for the host port interface to reduce switching noise. For the video input ports, higher speed logic is re- quired, but use the slowest practical edge rate to re- duce noise. To reduce noise, it is important to match the source impedance, line impedance, and load impedance as much as possible. Generally, if the line length is greater than one fourth the signal edge rate, line termination is necessary. Ringing can also be reduced by damping the line with a se- ries resistor (22-150 W ). Under extreme cases, it may be advisable to use microstrip techniques to further reduce radiated switching noise if very fast edge rates (<2ns) are used. If microstrip techniques are used, split the analog and digital ground planes and use proper RF decoupling techniques. 9.4. Analog Interconnect The CS4954/5 should be located as close as possi- ble the output connectors to minimize noise pickup and reflections due to impedance mismatch. All un- used analog outputs should be placed in shutdown. This reduces the total power that the CS4954/5 re- quires, and eliminates the impedance mismatch
maximize high frequency power supply rejection. shown in Figure 30 can be used. Figure 30. External Low Pass Filter
52 DS278PP4
Figure 31. Typical Connection Diagram
27 MHz Clock
- PIN DESCRIPTION B CVBS GNDA VAA C Y FIELD /CB HSYNC /CB VSYNC INT TEST XTAL_OUT XTAL_IN PADR VDD GNDD GNDA VAA G R VREF ISET VAA GNDA RESET SCL SDA TTXRQ TTXDAT CLKIN WR RD PDAT0 PDAT1 PDAT2 PDAT3 PDAT4 PDAT5 PDAT6 PDAT7 CS4954-CQ CS4955-CQ 48-Pin TQFP Top View 48 47 46 45 44 43 4142 40 39 38 37 13 14 15 16 17 18 2019 21 22 23 24
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VSYNC 11 I/O Active low vertical sync.
34 IN Active low master RESET
Table 10. Device Pin Description
- PACKAGE DRAWING INCHES MILLIMETERS DIM MIN MAX MIN MAX A1 0.002 0.006 0.05 0.15 B 0.007 0.011 0.17 0.27 D 0.343 0.366 8.70 9.30 D1 0.272 0.280 6.90 7.10 E 0.343 0.366 8.70 9.30 E1 0.272 0.280 6.90 7.10 e* 0.016 0.024 0.40 0.60 L 0.018 0.030 0.45 0.75 * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 48L TQFP PACKAGE DRAWING E D1D e L µ B A