Logic IC

CS495313-DQZ

Cirrus Logic

32-bit Audio Decoder DSP Family with Dual DSP Engine Technology

Manufacturer: Cirrus Logic

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®Copyright 2008 Cirrus Logic, Inc. JUNE ’08 DS705PP2http://www.cirrus.com 32-bit Audio Decoder DSP Family with Dual DSP Engine Technology CS4953xx Data Sheet Preliminary Product Information PRELIM INARY This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

FEATURES

Multi-standard 32-bit Audio Decoding plus Post Processing Framework™ Applications Library in ROM — Dolby Digital ® EX, Dolby® Pro Logic® IIx, Dolby Headphone®, Dolby® Virtual Speaker® — DTS-ES 96/24 ™ , DTS-ES™ Discrete 6.1, DTS-ES™ Matrix 6.1, DTS:Neo6™ — AAC™ Multichannel 5.1 —S R S ® CS2® and TSXT® —T H X ® Ultra2™ , THX® ReEQ™ — Cirrus Original Multi-Channel Surround (COMS) — Crossbar Mixer, Signal Generator — Advanced Post-Processor including: 7.1Bass Manager, Tone Control, 12- Band Parametric EQ, Delay, 1:2 Upsampler —M i c r o s o f t ® HDCD® Framework™ Applications for Download — Thomson MP3 Surround — Internal DSD-to-PCM Conversion Up to 12 Channels of 32-bit Serial Audio Input 6 Channel DSD Input 16 Ch x 32-bit PCM Out with either two 192 kHz S/PDIF Tx (144-pin package) or one 192 kHz S/PDIF Tx (128-pin package) Two SPI™ /I2C®, One Parallel and One UART Port Customer Software Security Keys Large On-chip X, Y, and Program RAM & ROM SDRAM and Serial/Parallel Flash Memory Support 32-bit DSP A D M A 32-bit DSP B Ext. Memory Controller P S/PDIF X Y P X Y Serial Control 1

16 Ch PCM

12 Ch. Audio In / 6 Ch. SACD In The CS4953xx DSP family are the enhanced versions of the CS495xx DSP family with higher overall performance and lower system cost. The CS4953xx includes all mainstream audio processing codes in on-chip ROM. This saves external memory for code storage. In addition, the intensive decoding tasks of Dolby Digital ® Surround EX®, AAC multi-channel, DTS-ES 96/24, THX Ultra2 Cinema and Dolby Headphone can be accomplished without the expense of external SDRAM memory. With larger internal memories than the CS495xx, the CS49531x is designed to support up to 150 ms per channel of lip-sync delay. With 150 MHz internal clock speed, the CS4953xx supports the most demanding post- processing requirements. It is also designed for easy upgrading. Customers currently using the CS495xx can upgrade to the CS4953xx with minor hardware and software changes.

Ordering Information

See page 31 for ordering information

5.12 Switching Characteristics — Serial Control Port - I

CS4953xx family of processors. devices. This includes hardware functionality, characteristic data, pinout, and packaging information. the speed and firmware features of each device.

2.1 Migrating from the CS495xx(2) to the CS4953xx

The PLL supply voltage on the CS4953xx is 3.3V vs. 1.8V on the CS495xx(2). The PLL filter topology is simpler when using the CS4953xx rather than the CS495xx(2). The CS4953xx adds support for 6-channel DSD input. The CS4953xx adds support for TDM mode on both audio input and output ports. The CS4953xx does not support external SRAM operation. The CS4953xx CLKOUT pin can output XTALI or XTALI/2. The CS495xx(2) can only output XTALI.

2.2 Licensing

application notes. Please contact your local Cirrus Sales representative for more information. Table 1. CS4953xx Related Documentation

32-bit Audio Decoder DSP Family DS705PP2 ®Copyright 2008 Cirrus Logic, Inc. 5 PRELIM INARY 3. Code Overlays The suite of software available for the CS4953xx family consists of an operating system (OS) and a library of overlays. The overlays have been divided into three main groups called Decoders, Mid-processors, and Post- processors. All software components are defined below: 1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, error concealment, etc. 2. Decoders - Any Module that initially writes data into the audio I/O buffers, e.g. AC-3 ®, DTS, PCM, etc. All the decoding/processing algorithms listed below require delivery of PCM or IEC61937-packed, compressed data via I2S- or LJ-formatted digital audio to the CS4953xx. 3. Mid-processors - Any module that processes audio I/O buffer PCM data in-place before the Post- processors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer through processes like Virtualization (nÖ2 channels) or Matrix Decoding (2Ön channels). Examples are Dolby ProLogic IIx and DTS Neo:6. 4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the Mid-Processors. Examples are Bass Management, Audio Manager, Tone Control, EQ, Delay, Customer-specific Effects, Dolby Headphone/Virtual Speaker, etc. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new decoder is selected, the OS, mid-, and post-processors do not need to be reloaded — only the new decoder (the same is true for the other overlays). Table 2 below lists the firmware available based on device selection. Please refer AN288 CS4953xx Firmware User’s Manual for the latest listing of application codes and Cirrus Framework ™ modules available.

Table 2. Device and Firmware Selection Guide1

300 MIPS N/A

300 MIPS

Hardware Functional Description

4.1 DSP Core

data registers, and 12 index registers. core, leaving more MIPS available for signal processing instructions. decoder and post-processor modules which are available from Cirrus Logic. and Digital Broadcast Decoder applications.

4.1.1 DSP Memory

The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.

4.1.2 DMA Controller

controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable. Table 3. CS495303 DSP Memory Sizes Table 4. CS495313 DSP Memory Sizes

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of accepting PCM, IEC61937, or DSD. Up to 32-bit word lengths are supported. Up to 6 channels of DSD are supported and internally converted to PCM before processing. The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which off-loads the task of monitoring the S/PDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted via software.

4.2.2 Digital Audio Output Port (DAO)

There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a 192 kHz S/PDIF transmitter (data with embedded clock on a single line). Note: Only one S/PDIF transmitter pin is available in the 128-pin package.

4.2.3 Serial Control Port 1 & 2 (I

2C® or SPI™ ) There are two on-chip serial control ports that are capable of operating as master or slave in either I 2C or SPI modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external clock up to 50 MHz in SPI mode. It is present in both the 144- and 128-pin packages. This high clock speed enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for audio sub-system control. SCP2 does not include the SCP2_BSY# pin in the 128-pin package.

4.2.4 Parallel Control Port

The CS4953xx parallel port supports both Motorola ® and Intel® interfaces. It can be used for both control and data delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin package.

4.2.5 External Memory Interface

The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus. The memory controller supports up to 1 MB of Flash memory in 8-bit data bus-width mode or 2 MB in 16-bit data bus-width mode.

4.2.6 GPIO

Many of the CS4953xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.

4.2.7 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS4953xx defaults to running from the external reference frequency and can be switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external serial FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.

4.3 DSP I/O Description

4.3.1 Multiplexed Pins

Many of the CS4953xx pins are multi-functional. For details on pin functionality please refer to the CS4953xx Hardware User’s Manual.

4.3.2 Termination Requirements

Open-drain pins on the CS4953xx must be pulled high for proper operation. Please refer to the CS4953xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins on the CS4953xx are used to select the boot mode upon the rising edge of reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS4953xx Hardware User’s Manual.

4.3.3 Pads

The CS4953xx I/O operates from the 3.3 V supply and is 5V tolerant.

4.4 Application Code Security

The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device.

32-bit Audio Decoder DSP Family 10 ®Copyright 2008 Cirrus Logic, Inc. DS705PP2 PRELIM INARY 5. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T=2 5° C , CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.

5.1 Absolute Maximum Ratings

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

5.2 Recommended Operating Conditions

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.

5.3 Digital DC Characteristics

(Measurements performed under static conditions.) Parameter Symbol Min Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDDIO| VDD VDDA VDDIO –0.3 –0.3 –0.3 2.0 3.6 3.6 0.3 V V V V Input pin current, any pin except supplies I in -+ / - 1 0 m A Input voltage on PLL_REF_RES V filt -0.3 3.6 V Input voltage on I/O pins V inio -0.3 5.0 V Storage temperature T stg –65 150 °C Parameter Symbol Min Typ Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDDIO| VDD VDDA VDDIO 1.71 3.13 3.13 1.8 3.3 3.3 1.89 3.46 3.46 V V V V Ambient operating temperature - CQ - DQ TA - 40 + 70 + 85 Parameter Symbol Min Typ Max Unit High-level input voltage V IH 2.0 - - V Low-level input voltage, except XTI V IL -- 0 . 8V Low-level input voltage, XTI V ILXTI -- 0 . 6V Input Hysteresis V hys 0.4 V High-level output voltage (IO = -4mA), except XTI, SDRAM pins VOH VDDIO * 0.9 - - V Low-level output voltage (IO = 4mA), except XTI, SDRAM pins VOL -- V D D I O * 0 . 1 V SDRAM High-level output voltage (IO = -8mA) V OH VDDIO * 0.9 - - V SDRAM Low-level output voltage (IO = 8mA) V OL -- V D D I O * 0 . 1 V Input leakage current (all digital pins with internal pull-up resistors disabled) IIN --5 μA Input leakage current (all digital pins with internal pull-up resistors enabled, and XTI) IIN-PU -- 5 0 μA

5.4 Power Supply Characteristics

(measurements performed under operating conditions)

5.5 Thermal Data (144 LQFP)

5.6 Thermal Data (128 LQFP)

Notes: 1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20 % of the top & bottom layers. 2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20 % of the top & bottom layers and 0.5-oz copper covering 90 % of the internal power plane and ground plane layers. 3. To calculate the die temperature for a given power dissipation 4. Τj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ] 5. To calculate the case temperature for a given power dissipation 6. Τc = Τj - [ (Power Dissipation in Watts) * ψ jt ]

5.7 Switching Characteristics— RESET

Parameter Min Typ Max Unit Power supply current: Core and I/O operating: VDD1 PLL operating: VDDA With external memory and most ports operating: VDDIO 1. Dependent on application firmware and DSP clock speed. 500 3.5 120 mA mA mA Parameter Symbol Min Typ Max Unit Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 θja °C / Watt Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2 ψjt .39 .33 °C / Watt Parameter Symbol Min Typ Max Unit Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 θja °C / Watt Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2 ψjt .45 .39 °C / Watt Parameter Symbol Min Max Unit RESET# minimum pulse width low T rstl 1- μs All bidirectional pins high-Z after RESET# low T rst2z -1 0 0 n s Configuration pins setup before RESET# high T rstsu 50 - ns Configuration pins hold after RESET# high T rsthld 20 - ns

Figure 1. RESET Timing

5.8 Switching Characteristics — XTI

Figure 2. XTI Timing

CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside

recommendation for load capacitor selection.

5.9 Switching Characteristics — Internal Clock

Parameter Symbol Min Max Unit Internal DCLK frequency1 CS49530x-CVZ CS49531x-CQZ CS49531x-CVZ CS49530x-DVZ CS49531x-DQZ CS49531x-DVZ1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset. Fdclk - Fxtal Fxtal Fxtal Fxtal Fxtal Fxtal 150 150 150 TBD TBD TBD MHz Internal DCLK period CS49530x-CVZ CS49531x-CQZ CS49531x-CVZ CS49530x-DVZ CS49531x-DQZ CS49531x-DVZ DCLKP - 6.7 6.7 6.7 TBD TBD TBD 1/F xtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal ns

5.10 Switching Characteristics — Se rial Control Port - SPI Slave Mode. Figure 3. Serial Control Port - SPI Slave Mode Timing

The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that

5.11 Switching Characteristics — Se rial Control Port - SPI Master Mode

Figure 4. Serial Control Port - SPI Master Mode Timing

The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that

the actual maximum speed of the communication port may be limited by the firmware application.

SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a

5.12 Switching Characteristics — Serial Control Port - I 2C Slave Mode

Figure 5. Serial Control Port - I2C Slave Mode Timing

The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that

using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer.

5.13 Switching Characteristics — Serial Control Port - I 2C Master Mode

Figure 6. Serial Control Port - I2C Master Mode Timing

The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that

the actual maximum speed of the communication port may be limited by the firmware application.

5.14 Switching Characteristics — Parallel Control Port - Intel ® Slave Mode

Parameter Symbol Min Typical Max Unit Address setup before PCP_CS# and PCP_RD# low or PCP_CS# and PCP_WR# low tias 5- n s Address hold time after PCP_CS# and PCP_RD# low or PCP_CS# and PCP_WR# high tiah 5- n s Read Delay between PCP_RD# then PCP_CS# low or PCP_CS# then PCP_RD# low ticdr 0- n s Data valid after PCP_CS# and PCP_RD# low t idd -1 8 n s PCP_CS# and PCP_RD# low for read t irpw 24 - ns Data hold time after PCP_CS# or PCP_RD# high t idhr 8- n s Data high-Z after PCP_CS# or PCP_RD# high t idis -1 8 n s PCP_CS# or PCP_RD# high to PCP_CS# and PCP_RD# low for next read1 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent overflowing the input data buffer. AN288 CS4953xx Firmware Uses’s Manual should be consulted for the firmware speed limitations. tird 30 - ns PCP_CS# or PCP_RD# high to PCP_CS# and PCP_WR# low for next write1 tirdtw 30 - ns PCP_RD# rising to PCP_IRQ# rising t irdirqhl -1 2 n s Write Delay between PCP_WR# then PCP_CS# low or PCP_CS# then PCP_WR# low ticdw 0- n s Data setup before PCP_CS# or PCP_WR# high t idsu 8- n s PCP_CS# and PCP_WR# low for write t iwpw 24 - ns Data hold after PCP_CS# or PCP_WR# high t idhw 8- n s PCP_CS# or PCP_WR# high to PCP_CS# and PCP_RD# low for next read1 tiwtrd 30 - ns PCP_CS# or PCP_WR# high to PCP_CS# and PCP_WR# low for next write1 tiwd 30 - ns PCP_WR# rising to PCP_BSY# falling t iwrbsyl - 2*DCLKP + 20 - ns

5.15 Switching Characteristics — Parallel Control Port - Motorola ® Slave Mode

Parameter Symbol Min Max Unit Address setup before PCP_CS# and PCP_DS# low t mas 5- n s Address hold time after PCP_CS# and PCP_DS# low t mah 5- n s Read Delay between PCP_DS# then PCP_CS# low or PCP_CS# then PCP_DS# low tmcdr 0- n s Data valid after PCP_CS# and PCP_DS# low with PCP_R/W# high t mdd -1 9 n s PCP_CS# and PCP_DS# low for read t mrpw 24 - ns Data hold time after PCP_CS# or PCP_DS# high after read t mdhr 8- n s Data high-Z after PCP_CS# or PCP_DS# high after read t mdis -1 8 n s PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next read1 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent overflowing the input data buffer. AN288 CS4953xx Firmware Uses’s Manual should be consulted for the firmware speed limitations. tmrd 30 - ns PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next write1 tmrdtw 30 - ns PCP_RW# rising to PCP_IRQ# falling t mrwirqh -1 2 n s Write Delay between PCP_DS# then PCP_CS# low or PCP_CS# then PCP_DS# low tmcdw 0- n s Data setup before PCP_CS# or PCP_DS# high t mdsu 8- n s PCP_CS# and PCP_DS# low for write t mwpw 24 - ns PCP_R/W# setup before PCP_CS# AND PCP_DS# low t mrwsu 24 - ns PCP_R/W# hold time after PCP_CS# or PCP_DS# high t mrwhld 8- n s Data hold after PCP_CS# or PCP_DS# high t mdhw 8- n s PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low with PCP_R/W# high for next read1 tmwtrd 30 - ns PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next write1 tmwd 30 - ns PCP_RW# rising to PCP_BSY# falling t mrwbsyl - 2*DCLKP + 20 - ns

5.16 Switching Characteristics — UART

Figure 11. UART Timing

The minimum clock period is limited to DCLKP/32 or the minimum value, whichever is larger.

5.17 Switching Characteristics — Digital Audio Slave Input Port

Figure 12. Digital Audio Input (DAI) Port Timing Diagram

5.18 Switching Characteri stics — DSD Slave Input Port

Figure 13. Direct Stream Digital - Serial Audio Input Timing

5.19 Switching Characteristics — Digital Audio Output Port

CS4953xx has two Digital Audio Output modules having similar signal names ending in 1 and 2. Both DAO ports

share a common MCLK but have independent SCLKs and LRCLKs.

Master mode timing specifications are characterized, not production tested.
Master mode is defined as the CS4953xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is

divided to produce DAO_SCLK, DAO_LRCLK.

This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the

point at which the data is valid. 5.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

Figure 14. Digital Audio Port Timing, MCLK Master Mode

5.20 Switching Characteristics — External Memory Interface - Flash Mode

Parameter Symbol Min Max Unit Write Cycle Address Setup time to EXT_WE# falling txmwasu 1.2 * DCLKP ns EXT_CS# falling to EXT_WE# falling1 1. The following parameters are set by communication with the application firmware. Please refer to AN288 or CS4953xx Firmware Users Manual for more information. 0 < Flash_WEN_CYCLE < 15 0 < Flash_WR_CYCLE < 31 1 < Flash_RD_CYCLE < 31 0 < Flash_OEN_CYCLE < 15 4 < Flash_TURN_CYCLE < 15 txmcswe (Flash_WEN_CYCLE + 1.2) * DCLKP ns EXT_CS# falling to EXT_WE# rising1 txmcswa (Flash_WR_CYCLE + 2.2) * DCLKP ns EXT_WE# low time txmwp 2.2 * DCLKP ns Data Hold after EXT_WE# or EXT_CS# high txmwdh 0.9 * DCLKP ns Address Hold from end of write txmwah 0.8 * DCLKP ns EXT_WE# falling to data valid t xmwedv -0 n s EXT_CS# high time2 2. A data write transaction is either a burst of two 16-bit half words or four 8-bit bytes with EXT_CS# toggling between address phases. txmcsh TBD ns Read Cycle Single Word Read Cycle1 txmrdc (Flash_RD_CYCLE + 1) * DCLKP ns EXT_CS# falling to EXT_OE# falling1 txmcsoe Flash_OEN_CYCLE * DCLKP + 1 ns Data Hold after EXT_OE# or EXT_CS# high txmrdh 4 ns Data Input Setup Time txmrdsu 7 ns Bus Turnaround Cycle Delay, Read to Write Cycle or Static to Dynamic1, 3 3. A data read transaction is either a burst of two 16-bit half words (as shown) or four 8-bit bytes with EXT_CS# remaining asserted between address phases. txmturn (Flash_TURN_CYCLE + 1) * DCLKP ns

5.21 Switching Characteristics — SDRAM Interface

Refer to Figure 17 through Figure 20. (SD_CLKOUT = SD_CLKIN) Parameter Symbol Min Typical Max Unit SD_CLKIN high time t sdclkh 2.3 - ns SD_CLKIN low time t sdclkl 2.3 - ns SD_CLKOUT rise/fall time t sdclkrf -1 n s SD_CLKOUT Frequency 150 MHz SD_CLKOUT duty cycle - 45 55 % SD_CLKOUT rising edge to signal valid t sdcmdv -3 . 8 n s Signal hold from SD_CLKOUT rising edge t sdcmdh 1.1 - ns SD_CLKOUT rising edge to SD_DQMn valid t sddqv -3 . 8 - n s SD_DQMn hold from SD_CLKOUT rising edge t sddqh 1.38 - ns SD_DATA valid setup to SD_CLKIN rising edge t sddsu 1.3 - ns SD_DATA valid hold to SD_CLKIN rising edge t sddh 1.38 - ns SD_CLKOUT rising edge to ADDRn valid t sdav -3 . 8 - n s

Note: Please contact the factory for availability of the -D (automotive grade) package.

Environmental, Manufacturing, & Handling Information

MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Table 5. Ordering Information Table 6. Environmental, Manufacturing, & Handling Information

Figure 21. 128-Pin LQFP Pin-Out Drawing

Figure 22. 144-Pin LQFP Pin-Out Drawing

Package Mechanical Drawings

Figure 23. 128-Pin LQFP Package Drawing Table 7. 128-Pin LQFP Package Characteristics

Figure 24. 144-Pin LQFP Package Drawing Table 8. 144-Pin LQFP Package Characteristics

Controlling dimension is millimeter.
Dimensioning and tolerancing per ASME Y14.5M-

32-bit Audio Decoder DSP Family 36 ®Copyright 2008 Cirrus Logic, Inc. DS705PP2 PRELIM INARY 10. Revision History Revision Date Changes A1 FEB 2006 Advance release. A2 JUN 2006 Updated part numbers for ordering (Tables 5 & 6), Updated V OH and VOL specification to include the current load used for testing A3 JUL 2006 Updated part numbers for ordering (Tables 5 &6). Updated text in sections 3 and 4. Updated parameter descriptions in sections 5.1 and 5.3. Updated Tspickl, Tspickh, and Tspidov timing. Corrected Figure SPI Master Timing to use EE_CS#. Added footnote to XTI table. Removed SCLK/LRCLK relative timing from DAI port timing. Removed SCLK/LRCLK slave relative timing from DAO port timing. A4 OCT 2007 Updated the Tspidsu, Tspickl, and Tspickh timing parameters for master mode SPI. This applies to both SPI ports. PP1 May 28, 2008 Updated product feature list in Table 2. Updated Figure 21 and Figure 22. PP2 June 20, 2008 Added typical crystal frequency values in Table Footnote 1 and Max and Min values of F xtalin Section 5.8. Removed DSD Phase Modulation Mode from Section 5.18. Removed reference to MCLK in Section 5.18. Redefined Master mode clock speed for SCP_CLK in Section 5.11.. Redefined DC leakage characterization data in Section 5.3, correcting units of measurement. Modified Footnote 1 under Section 5.10.

32-bit Audio Decoder DSP Family DS705PP2 ®Copyright 2008 Cirrus Logic, Inc. 37 PRELIM INARY Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its sub- sidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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Product Information

CS495313-DQZ specifications and overview.

Summary

32-bit Audio Decoder DSP Family with Dual DSP Engine Technology

Description

32-bit Audio Decoder DSP Family with Dual DSP Engine Technology

Source title CS495313-DQZ Datasheet(PDF) - Cirrus Logic

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