CS495304-CVZR

CS4953XX_0911 CIRRUS | Alldatasheet

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Copyright 2009 Cirrus Logic, NOV ’09 DS705PP6 Audio Decoder DSP Family with Dual 32-bit DSP Engine Technology CS4953xx Data Sheet Preliminary Product Information PRELIM INARY This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. http://www.cirrus.com

FEATURES

‰ Multi-standard 32-bit Audio Decoding plus Post Processing ‰ Framework™ Third-Party Applications Library — Dolby Digital ® EX, Dolby® Pro Logic® IIz, Dolby Headphone® 2, Dolby® Virtual Speaker® 2 — DTS-ES 96/24 ™ , DTS-ES™ Discrete 6.1, DTS-ES™ Matrix 6.1, DTS Neo:6® —D S D ® to Linear PCM Decimation Filtering — MPEG-2 AAC ™ LC 5.1 —S R S ® CS2®, SRS TruVolume™ , SRS TruSurround HD4™ —T H X ® Ultra2™ , THX® Re-EQ™ — Audyssey 2EQ ™ ‰ Framework™ Cirrus Logic Applications Library — 2:1/4:1 Decimator, Cirrus Intelligent Room Calibration 2 (IRC2) — Cirrus Original Multi-Channel Surround 2 (COMS2) — Crossbar Mixer, Signal Generator — Advanced Post-Processor including: 7.1 Bass Manager, Tone Control, 11-Band Parametric EQ, Delay, 1:2/1:4 Upsampler ‰ Up to 12 Channels of 32-bit Serial Audio Input ‰ 16 Ch x 32-bit PCM Out with either two or one 192 kHz S/PDIF Tx ‰ Two SPI™ /I2C™ Ports and one Parallel Port* ‰ Customer Software Security Keys Coyote 32-bit DSP A D M A Coyote 32-bit DSP B Ext. Memory Controller P S/PDIF X Y P X Y Serial Control 1

16 Ch PCM

12 Ch. Audio In / 6 Ch. SACD In ‰ Large On-chip X, Y, and Program RAM & ROM ‰ SDRAM and Serial Flash Memory Support The CS4953xx DSP family are the enhanced versions of the CS495xx DSP family with higher overall performance and lower system cost. The CS4953xx includes all mainstream audio processing codes in on-chip ROM. This saves external memory for code storage. In addition, the intensive decoding tasks of Dolby Digital ® Surround EX®, AAC multi-channel, DTS-ES 96/24, THX Ultra2 Cinema and Dolby Headphone can be accomplished without the expense of external SDRAM memory. With larger internal memories than the CS495xx, the CS49531x is designed to support up to 150 ms per channel of lip-sync delay. With 150 MHz internal clock speed, the CS4953xx supports the most demanding post-processing requirements. It is also designed for easy upgrading. Customers currently using the CS495xx can upgrade to the CS4953xx with minor hardware and software changes.

Ordering Information

See page 28 for ordering information. * 144-Pin Package Only

32-bit Audio Decoder DSP Family

2 Copyright 2009 Cirrus Logic DS705PP6

5.12 Switching Characteristics — Serial Control Port - I

4 Copyright 2009 Cirrus Logic DS705PP6

CS4953xx family of processors. devices. This includes hardware functionality, characteristic data, pinout, and packaging information. CS4953x4/CS497xx System Designer’s Guide. a 128-pin or 144-pin QFP package. Table 1. CS4953xx Related Documentation

32-bit Audio Decoder DSP Family DS705PP6 Copyright 2009 Cirrus Logic 5 PRELIM INARY

2.1 Migrating from CS4953x3 to CS4953x4

 The recommended way to boot the DSP for normal operation is “master boot”. Refer to Chapter 1 of the CS4953x4/CS4970x4 System Designer’s Guide. CS4953x4 will support slave boot mode as well (used for programming the serial flash with the DSP code, through the SCP2 port).  CS4953x4 DSPs are only available in 128 pin package.  The serial flash chip select pin used is pin 14 (GPIO0) for Master Boot. Cirrus Logic recommends that at least an 8-Mbit serial Flash device be used. Refer to CS4953x4/CS4970x4 System Designer’s Guide for a list of Flash types that are currently supported  CS4953x4 DSP family supports DSP Condenser and DSP Manager API for run-time control/host communication. Please refer to CS4953x4/CS4970x4 System Designer’s Guide for details.

2.2 Licensing

Licenses are required for all of the 3rd party audio decoding/processing algorithms listed below, including the application notes. Please contact your local Cirrus Sales representative for more information. 3. Code Overlays The suite of software available for the CS4953xx family consists of an operating system (OS) and a library of overlays. The overlays have been divided into three main groups called Decoders, Matrix-processors, and Post-processors. All software components are defined below: 1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, error concealment, etc. 2. Decoders - Any Module that initially writes data into the audio I/O buffers, e.g. AC-3 ™ , DTS, PCM, etc. All the decoding/processing algorithms listed below require delivery of PCM or IEC61937-packed, compressed data via I2S- or LJ-formatted digital audio to the CS4953xx. 3. Matrix-processors - Any module that processes audio I/O buffer PCM data in-place before the Post- processors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer through processes like Virtualization (nÖ2 channels) or Matrix Decoding (2Ön channels). Examples are Dolby ProLogic IIx and DTS Neo:6. 4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the Matrix- Processors. Examples are Bass Management, Audio Manager, Tone Control, EQ, Delay, Customer-specific Effects, Dolby Headphone/Virtual Speaker, etc. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new decoder is selected, the OS, matrix-, and post-processors do not need to be reloaded — only the new decoder (the same is true for the other overlays). Table 2 below lists the firmware available based on device selection. Please refer AN288 CS4953xx/CS497xxx Firmware User’s Manual for the latest listing of application codes and Cirrus Framework ™ modules available.

Table 2. Device and Firmware Selection Guide1

300 MIPS N/A

300 MIPS

1. Hardware Functional Description

4.1 Coyote 32-bit DSP Core

registers, and 12 index registers. core, leaving more MIPS available for signal processing instructions. decoder and post-processor modules which are available from Cirrus Logic. and Digital Broadcast Decoder applications.

4.1.1 DSP Memory

The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.

4.1.2 DMA Controller

controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable. Table 3. CS49530x DSP Memory Sizes Table 4. CS49531x DSP Memory Sizes

32-bit Audio Decoder DSP Family

8 Copyright 2009 Cirrus Logic DS705PP6

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of accepting PCM, IEC61937, or DSD. Up to 32-bit word lengths are supported. Up to 6 channels of DSD are supported and internally converted to PCM before processing. The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which off-loads the task of monitoring the S/PDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted via software.

4.2.2 Digital Audio Output Port (DAO)

There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a 192 kHz S/PDIF transmitter (data with embedded clock on a single line). Note: Only one S/PDIF transmitter pin is available in the 128-pin package.

4.2.3 Serial Control Port 1 & 2 (I

2C™ or SPI™ ) There are two on-chip serial control ports that are capable of operating as master or slave in either I 2C or SPI modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external clock up to 50 MHz in SPI mode. It is present in both the 144- and 128-pin packages. This high clock speed enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for audio sub-system control. SCP2 does not include the SCP2_BSY# pin in the 128-pin package.

4.2.4 Parallel Control Port

The CS4953xx parallel port supports both Motorola ® and Intel® interfaces. It can be used for both control and data delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin package.

4.2.5 External Memory Interface

The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus.

4.2.6 GPIO

Many of the CS4953xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.

4.2.7 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS4953xx defaults to running from the external reference frequency and can be switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external serial FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.

4.3 DSP I/O Description

4.3.1 Multiplexed Pins

Many of the CS4953xx pins are multi-functional. For details on pin functionality please refer to the CS4953xx Hardware User’s Manual.

32-bit Audio Decoder DSP Family DS705PP6 Copyright 2009 Cirrus Logic 9 PRELIM INARY

4.3.2 Termination Requirements

Open-drain pins on the CS4953xx must be pulled high for proper operation. Please refer to the CS4953xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins on the CS4953xx are used to select the boot mode upon the rising edge of reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS4953xx Hardware User’s Manual.

4.3.3 Pads

The CS4953xx I/O operates from the 3.3 V supply and is 5V tolerant.

4.4 Application Code Security

The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device.

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10 Copyright 2009 Cirrus Logic DS705PP6

1. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T=2 5° C , C L = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.

5.1 Absolute Maximum Ratings

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

5.2 Recommended Operating Conditions

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.

5.3 Digital DC Characteristics

(Measurements performed under static conditions.) Parameter Symbol Min Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDDIO| VDD VDDA VDDIO –0.3 –0.3 –0.3 2.0 3.6 3.6 0.3 V V V V Input pin current, any pin except supplies Iin -+ / - 1 0 m A Input voltage on PLL_REF_RES Vfilt -0.3 3.6 V Input voltage on I/O pins Vinio -0.3 5.0 V Storage temperature Tstg –65 150 °C Parameter Symbol Min Typ Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDDIO| VDD VDDA VDDIO 1.71 3.13 3.13 1.8 3.3 3.3 1.89 3.46 3.46 V V V V Ambient operating temperature Commercial Grade (CQZ/CVZ) Automotive Grade (DQZ/DVZ) TA - 40 +25 +25 + 70 + 85 Parameter Symbol Min Typ Max Unit High-level input voltage VIH 2.0 - - V Low-level input voltage, except XTI VIL -- 0 . 8V Low-level input voltage, XTI VILXTI -- 0 . 6V Input Hysteresis Vhys 0.4 V High-level output voltage (IO = -4mA), except XTI, SDRAM pins VOH VDDIO * 0.9 - - V Low-level output voltage (IO = 4mA), except XTI, SDRAM pins VOL - - VDDIO * 0.1 V SDRAM High-level output voltage (IO = -8mA) VOH VDDIO * 0.9 - - V SDRAM Low-level output voltage (IO = 8mA) VOL - - VDDIO * 0.1 V Input leakage current (all digital pins with internal pull-up resistors disabled) IIN --5 μA

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5.4 Power Supply Characteristics

(measurements performed under operating conditions)

5.5 Thermal Data (144-pin LQFP)

5.6 Thermal Data (128-pin LQFP)

Notes: 1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20 % of the top & bottom layers. 2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20 % of the top & bottom layers and 0.5-oz copper covering 90 % of the internal power plane and ground plane layers. 3. To calculate the die temperature for a given power dissipation Τj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ] 4. To calculate the case temperature for a given power dissipation Τc = Τj - [ (Power Dissipation in Watts) * ψ jt ]

5.7 Switching Characteristics— RESET

Input leakage current (all digital pins with internal pull-up resistors enabled, and XTI) IIN-PU -- 7 0 μA Parameter Min Typ Max Unit Power supply current: Core and I/O operating: VDD1 PLL operating: VDDA With external memory and most ports operating: VDDIO 1. Dependent on application firmware and DSP clock speed. 500 3.5 120 mA mA mA Parameter Symbol Min Typ Max Unit Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 θja °C / Watt Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2 ψjt .39 .33 °C / Watt Parameter Symbol Min Typ Max Unit Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 θja °C / Watt Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2 ψjt .45 .39 °C / Watt Parameter Symbol Min Max Unit RESET minimum pulse width low Trstl 1- μs All bidirectional pins high-Z after RESET low Trst2z -1 0 0 n s Configuration pins setup before RESET high Trstsu 50 - ns Parameter Symbol Min Typ Max Unit

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Figure 1. RESET Timing

5.8 Switching Characteristics — XTI

Figure 2. XTI Timing

1. Part characterized with the following crystal frequency values: 12.288 and 24.576
2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside

recommendation for load capacitor selection.

32-bit Audio Decoder DSP Family DS705PP6 Copyright 2009 Cirrus Logic 13 PRELIM INARY

5.9 Switching Characteristics — Internal Clock

Parameter Symbol Min Max Unit Internal DCLK frequency1 CS49530x-CVZ CS49531x-CQZ CS49531x-CVZ CS49530x-DVZ CS49531x-DVZ 1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset. Fdclk - Fxtal Fxtal Fxtal Fxtal Fxtal 150 150 150 TBD TBD MHz Internal DCLK period1 CS49530x-CVZ CS49531x-CQZ CS49531x-CVZ CS49530x-DVZ CS49531x-DVZ DCLKP - 6.7 6.7 6.7 TBD TBD 1/F xtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal ns

14 Copyright 2009 Cirrus Logic DS705PP6

5.10 Switching Characteristics — Se rial Control Port - SPI Slave Mode. Figure 3. Serial Control Port - SPI Slave Mode Timing

1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that

5.11 Switching Characteristics — Se rial Control Port - SPI Master Mode

Figure 4. Serial Control Port - SPI Master Mode Timing

1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that

the actual maximum speed of the communication port may be limited by the firmware application.

1. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a

16 Copyright 2009 Cirrus Logic DS705PP6

5.12 Switching Characteristics — Serial Control Port - I 2C Slave Mode

Figure 5. Serial Control Port - I2C Slave Mode Timing

1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that

using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer.

5.13 Switching Characteristics — Serial Control Port - I 2C Master Mode

Figure 6. Serial Control Port - I2C Master Mode Timing

1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that

the actual maximum speed of the communication port may be limited by the firmware application.

32-bit Audio Decoder DSP Family

18 Copyright 2009 Cirrus Logic DS705PP6

5.14 Switching Characteristics — Parallel Control Port - Intel ® Slave Mode

Parameter Symbol Min Typical Max Unit Address setup before PCP_CS and PCP_RD low or PCP_CS and PCP_WR low tias 5- n s Address hold time after PCP_CS and PCP_RD low or PCP_CS and PCP_WR high tiah 5- n s Read Delay between PCP_RD then PCP_CS low or PCP_CS then PCP_RD low ticdr 0- n s Data valid after PCP_CS and PCP_RD low tidd -1 8 n s PCP_CS and PCP_RD low for read tirpw 24 - ns Data hold time after PCP_CS or PCP_RD high tidhr 8- n s Data high-Z after PCP_CS or PCP_RD high tidis -1 8 n s PCP_CS or PCP_RD high to PCP_CS and PCP_RD low for next read1 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing the input data buffer. AN288 CS4953xx /CS497xxx Firmware User’s Manual should be consulted for the firmware speed limitations. tird 30 - ns PCP_CS or PCP_RD high to PCP_CS and PCP_WR low for next write1 tirdtw 30 - ns PCP_RD rising to PCP_IRQ rising tirdirqhl -1 2 n s Write Delay between PCP_WR then PCP_CS low or PCP_CS then PCP_WR low ticdw 0- n s Data setup before PCP_CS or PCP_WR high tidsu 8- n s PCP_CS and PCP_WR low for write tiwpw 24 - ns Data hold after PCP_CS or PCP_WR high tidhw 8- n s PCP_CS or PCP_WR high to PCP_CS and PCP_RD low for next read1 tiwtrd 30 - ns PCP_CS or PCP_WR high to PCP_CS and PCP_WR low for next write1 tiwd 30 - ns PCP_WR rising to PCP_BSY falling tiwrbsyl - 2*DCLKP + 20 - ns

32-bit Audio Decoder DSP Family

20 Copyright 2009 Cirrus Logic DS705PP6

5.15 Switching Characteristics — Parallel Control Port - Motorola ® Slave Mode

Parameter Symbol Min Max Unit Address setup before PCP_CS and PCP_DS low tmas 5- n s Address hold time after PCP_CS and PCP_DS low tmah 5- n s Read Delay between PCP_DS then PCP_CS low or PCP_CS then PCP_DS# low tmcdr 0- n s Data valid after PCP_CS and PCP_DS low with PCP_R/W high tmdd -1 9 n s PCP_CS and PCP_DS low for read tmrpw 24 - ns Data hold time after PCP_CS or PCP_DS high after read tmdhr 8- n s Data high-Z after PCP_CS or PCP_DS high after read tmdis -1 8 n s PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next read1 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing the input data buffer. AN288 CS4953xx/CS497xxx Firmware User’s Manual should be consulted for the firmware speed limitations. tmrd 30 - ns PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next write1 tmrdtw 30 - ns PCP_RW rising to PCP_IRQ falling tmrwirqh -1 2 n s Write Delay between PCP_DS then PCP_CS low or PCP_CS then PCP_DS low tmcdw 0- n s Data setup before PCP_CS or PCP_DS high tmdsu 8- n s PCP_CS and PCP_DS low for write tmwpw 24 - ns PCP_R/W setup before PCP_CS AND PCP_DS low tmrwsu 24 - ns PCP_R/W hold time after PCP_CS or PCP_DS high tmrwhld 8- n s Data hold after PCP_CS or PCP_DS high tmdhw 8- n s PCP_CS or PCP_DS high to PCP_CS and PCP_DS low with PCP_R/W high for next read1 tmwtrd 30 - ns PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next write1 tmwd 30 - ns PCP_RW rising to PCP_BSY falling tmrwbsyl -2 * D C L K P + 2 0 -n s

22 Copyright 2009 Cirrus Logic DS705PP6

5.16 Switching Characteristics — Digital Audio Slave Input Port

Figure 11. Digital Audio Input (DAI) Port Timing Diagram

5.17 Switching Characteristics — DSD ® Serial Input Port

Figure 12. DSD Serial Audio Input Timing

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5.18 Switching Characteristics — Digital Audio Output Port

Figure 13. Digital Audio Port Output Timing Master Mode

1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS4953xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is

divided to produce DAO_SCLK, DAO_LRCLK.

1. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the

point at which the data is valid.

1. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)

5.19 Switching Characteristics — SDRAM Interface

Refer to Figure 15 through Figure 18.

28 Copyright 2009 Cirrus Logic DS705PP6

Note: Please contact the factory for availability of the -D (automotive grade) package. Table 5. Ordering Information

1. Recommended for new designs. See Section 2. for details about Cirrus Logic design recommendations.

1. Environmental, Manufacturing, and Handling Information

• MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Table 6. Environmental, Manufacturing, and Handling Information

30 Copyright 2009 Cirrus Logic DS705PP6

Section 2. for details about this Cirrus Logic recommendation. Figure 19. 128-pin LQFP Pin-Out Drawing (CS495303/CS495313)

details about this Cirrus Logic recommendation. Figure 20. 128-pin LQFP Pin-Out Drawing (CS495304/CS495314)

32 Copyright 2009 Cirrus Logic DS705PP6

about this Cirrus Logic recommendation. Figure 21. 144-pin LQFP Pin-Out Drawing (CS495313)

1. Package Mechanical Drawings

Figure 22. 128-pin LQFP Package Drawing Table 7. 128-pin LQFP Package Characteristics

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Figure 23. 144-pin LQFP Package Drawing Table 8. 144-pin LQFP Package Characteristics

1. Controlling dimension is millimeter.
2. Dimensioning and tolerancing per ASME

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36 Copyright 2009 Cirrus Logic DS705PP6

Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its sub- sidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowl- edgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, includ- ing use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the informa- tion only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPER- TY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT- NESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEM- NIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Dolby, Dolby Digital, Dolby Headphone, Dolby Virtual Speaker, Dolby Headphone, Pro Logic, and Surround EX are registered trademarks of Dolby Laboratories, Inc. AC-3 and AAC are trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. DTS , DTS Digital Surround, and DTS Neo:6 are registered trademarks of the Digital Theater Systems, Inc. DTS-ES 96/24, DTS-ES, DTS 6.1, and DTS 96/24 are trademarks of Digital Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final product. THX is a registered trademark of Lucasfilm Ltd. Re-equalization and Ultra 2 are trademarks of Lucasfilm Ltd. SRS, Circle Surround and Trusurround XT are registered trademarks of SRS Labs, Inc. Circle Surround II is a trademark of SRS Labs, Inc. The CIRCLE SURROUND TECHNOLOGY rights incorporated in the Cirrus Logic chip are owned by SRS Labs, Inc. and by Valence Technology Ltd., and licensed to Cirrus Logic, Inc. Users of any Cirrus Logic chip containing enabled CIRCLE SURROUND® TECHNOLOGY (i.e., CIRCLE SURROUND® LICENSEES) must first sign a license to pur- chase production quantities for consumer electronics applications which may be granted upon submission of a preproduction sample to, and the satisfactory passing of performance verification tests performed by SRS Labs, Inc., or Valence Technology Ltd. E-mail requests for performance specifications and testing rate schedule may be made to cslicense@srslabs.com. SRS Labs, Inc. and Valence Technology, Ltd., reserve the right to decline a use license for any submission that does not pass performance specifications or is not in the consumer electronics classification. All equipment manufactured using any Cirrus Logic chip containing enabled CIRCLE SURROUND® TECHNOLOGY must carry the Circle Surround® logo on the front panel in a manner approved in writing by SRS Labs, Inc., or Valenc e Technology Ltd. If the Circle Surround logo is printed in u sers manuals, service manuals or advertisements, it must appear in a form approved in writing by SRS Labs, Inc., or Valence Technology, Ltd. The rear panel of C ircle Surround® products, users manuals, service manuals, and all advertising must all carry the legends as described in LICENSOR'S most current version of the CIRCLE SURROUND Trademark Usage Manual. Microsoft and Windows Media are registered trademarks of Microsoft Corporation. The product includes technology owned by Microsoft Corporation and cannot be used or distributed without a license from Microsoft Licensing, Inc. , HDCD, High Definition Compatible Digital and Pacific Microsonics Inc. are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. HDCD technology provided under license from Microsoft Corporation. The product's design (and/or software) is covered by one or more of the following: 5,479,168; 5,638,074; 5,640,161; 5,808,574; 5,838,274; 5,854,600; 5,864,311; 5,872,531 with other patents pending. Supply of this product does not convey a license under the relevant intellectual property of Thomson multimedia and/or Fraunhofer Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. An independent license for such use is required. For details, please visit http://www.mp3licensing.com. Motorola and SPI are trademarks of Motorola, Inc. Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Semiconductor. DSD, and Direct Stream Digital are registered trademarks of SONY KABUSHIKI KAISHA CORPORATION.