CS4953-CL

CS4952 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

/c108 Simultaneous composite and S-video output /c108 Supports RS170A and CCIR601 composite output timing /c108 Multi-standard support for NTSC-M, PAL (B, D, G, H, I, M, N, Combination N) /c108 Optional progressive scan @ MPEG2 field rates /c108 CCIR656 input mode supporting EAV/SAV codes and CCIR601 Master/Slave input modes /c108 Stable color subcarrier for MPEG2 systems /c108 NTSC closed caption encoder with interrupt /c108 Supports Macrovision copy protection in CS4953 version /c108 Host interface configurable for parallel or I2C compatible operation /c108 General purpose input and output pins /c108 Individual DAC power-down capability /c108 On-chip voltage reference generator /c108 On-chip color bar generator /c108 +5 volt only, CMOS, low power modes, tri-state DACs

Description

The CS4952/3 provides full conversion from YCbCr or YUV digital video formats into NTSC & PAL Composite and Y/C (S-video) analog video. Input formats can be

27 MHz 8-bit YUV, 8-bit YCbCr, or CCIR656 with sup-

port for EAV/SAV codes. Output video can be formatted to be compatible with NTSC-M, or PAL B,D,G,H,I,M,N, and Combination N systems. Also supported is NTSC line 21 and line 284 closed captioning encoding. Four 9-bit DACs provide two channels for an S-Video out- put port and two composite video outputs. 2x oversampling reduces the output filter requirements and guarantees no DAC related modulation components within the spec- ified bandwidth of any of the supported video standards. Parallel or high speed I 2C compatible control interfaces are provided for flexibility in system design. The parallel interface doubles as a general purpose I/O port when the CS4952/3 is in I 2C mode to help conserve valuable board area.

ORDERING INFORMATION

PDAT[7:0] RD* WR* ADDR XTAL VD[7:0] HSYNC* VSYNC* FIELD INT RESET* C CVBS37 CVBS75 Y VREFIN VREFOU T ISET VAA GND TEST I C Interface Host Parallel Interface Color Sub-carrier Synthesizer Video Formatter Video Timing Generator Control Registers Output Interpolate Chroma Amplifier Chroma Modulate Burst Insert Chroma Interpolate Luma Delay Luma Amplifier Sync Insert 9-Bit DAC Voltage Reference Current Reference LPF LPF Output Interpolate LPF 9-Bit DAC 9-Bit DAC 9-Bit DAC Σ U, V Y OCT ‘97 DS223PP2

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AC & DC PARAMETRIC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS: (AGND, DGND = 0 V, all voltages with respect to 0 V.) Warning: Operating beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS: (AGND, DGND = 0 V, all voltages with respect to 0 V.) Parameter Symbol Min Max Units Power Supply VAA -0.3 6.0 V Input Current Per Pin Except Supply Pins -10 10 mA Output Current Per Pin Except Supply Pins -50 +50 mA Analog Input Voltage -0.3 V AA +0.3 V Digital Input Voltage -0.3 VAA +0.3 V Ambient Temperature Power Applied -55 +125 °C Storage Temperature -65 +150 °C P a r a m e t e r S y m b o l M i n T y pM a x U n i t s Power Supplies: Digital Analog VAA 4.75 5.0 5.25 V Operating Ambient Temperature TA 0+ 2 5 + 7 0 ° C

D.C. CHARACTERISTICS: (TA=25 C; VAA = 5 V; GND = 0 V.) Notes: 1. Output current levels with ISET = 10 kΩ , VREFIN = 1.232 V. 2. Times for black-to-white level and white-to-black level transitions. Parameter Symbol Min Typ Max Units Digital Inputs High Level Input Voltage V [7:0], PDAT [7:0], HSYNC /VSYNC /FIELD/CLKIN VIH 2.0 - VAA +0.3 V High Level Input Voltage I 2C VIH 0.7VAA -- V Low Level Input Voltage All Inputs VIL -0.3 - 0.8 V Input Leakage Current Digital Inputs - -10 - +10 µA Digital Outputs High Level Output Voltage Io = -4mA VOH 2.4 - VAA V Low Level Output Voltage Io = 4mA VOL -- 0 . 4 V Low Level Output Voltage SDA pin only, Io = 6mA VOL -- 0 . 4 V Output Leakage Current High-Z Digital Outputs - -10 - +10 µA Analog Outputs Full Scale Output Current CVBS37/Y/C (Note 1) IO37 32.9 34.7 36.5 mA Full Scale Output Current CVBS75 (Note 1) IO75 16.4 17.3 18.2 mA LSB Current CVBS37/Y/C (Note 1) IB37 64.5 68 71.5 µA LSB Current CVBS75 (Note 1) IB35 32.2 34 35.8 µA DAC-to-DAC Matching MAT - 2 - % Output Compliance V OC 0- + 1 . 4 V Output Impedance R OUT -1 5 - k Ω Output Capacitance C OUT -- 3 0 p F DAC Output Delay O DEL -4 1 2 n s DAC Rise/Fall Time (Note 2) TRF -2 . 5 5 n s Voltage Reference Reference Voltage Output VOV 1.198 1.232 1.272 V Reference Input Current IVC -- 1 0 µA Power Supply Supply Voltage VAA 4.75 5 5.25 V Supply Current All DACs on CVBS75/CVGS37 only CVBS75 only IAA 1 IAA 2 IAA 3 180 110 200 mA mA mA

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D.C. CHARACTERISTICS (Continued) Parameter Symbol Min Typ Max Units Static Performance DAC Resolution - - 9 Bits Differential Non-Linearity DNL -1 ±0.5 +1 LSB Integral Non-Linearity INL -1 ±0.35 +1 LSB Dynamic Performance Differential Gain DB - 2 5 % Differential Phase DP - ±0.5 ±2 ° Signal to Noise Ratio SNR -70 - - dB Hue Accuracy H A -- 2 ° Saturation Accuracy SA -- 2 %

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A.C. CHARACTERISTICS: (Continued) ADDR PDAT[7:0] TrdhTas Trpw Trda Trah Trd RD* ADDR PDAT[7:0] Tas Twpw WR* Twds Twr Twdh Twac RD* WR* TrecTrec Parameter Symbol Min Typ Max Units 8-bit Parallel Host Interface Read Cycle Time Trd 60 - - ns Read Pulse Width Trpw 30 - - ns Address Setup Time Tas 3-- n s Read Address Hold Time Trah 10 - - ns Read Data Access Time Trda -- 4 0 n s Read Data Hold Time Trdh 10 - 50 ns Write Recovery Time Twr 60 - - ns Write Pulse Width Twpw 40 - - ns Write Data Setup Time Twds 8-- n s Write Data Hold Time Twdh 3-- n s Write-Read/Read-Write Recovery Time Trec 50 - - ns Address from Write Hold Time Twac 0-- n s 8-bit Parallel Host Port Timing: Read Cycle 8-bit Parallel Host Port Timing: Address Write Cycle 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle Figure 3.

Figure 4. Reset Timing

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27 MHz Clock

Figure 5. Typical Connection Diagram (I2C host interface)

The CS4952/3 is a complete multi-standard digital video encoder implemented in current 5-volt only CMOS technology. CCIR601 or CCIR656 compli- ant digital video input can be converted into NTSC-M, PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N, or PAL N Argentina-compatible analog video. The CS4952/3 is designed to connect to MPEG1 and MPEG2 digital video decompres- sors without glue logic. Two 9-bit DAC outputs provide high quality S-Video analog output while two other 9-bit DACs simultaneously generate composite analog video. The CS4952/3 will accept 8-bit YCbCr or 8-bit YUV input data. The CS4952/3 is completely configured and con- trolled via an 8-bit host interface port or an I compatible serial interface. This host port provides access and control of all CS4952/3 options and fea- tures like closed caption insertion, interrupts, etc. In order to lower the end user set-top overall sys- tem costs, the CS4952/3 provides an internal volt- age reference which eliminates the requirement for an external discrete 3-pin voltage reference. FUNCTIONAL DESCRIPTION In the following subsections, the functions of the CS4952/3 will be described. The descriptions refer to the block diagram on the cover page. Video Timing Generator All timing generation is accomplished via a 27 MHz input applied to the CLK pin. The CS4952/3 can also accept an optional color burst crystal on the ADDR & XTAL pins. See section: Color Subcarrier Synthesizer (page 12), for further details. The Video Timing Generator is responsible for or- chestrating most all of the other modules in the de- vice. It works in harmony with external sync input timing or by providing external sync timing out- puts. It automatically disables color burst on appro- priate scan lines and generates serration and equalization pulses on appropriate scan lines. The CS4952/3 is designed to function as a video timing master or video timing slave. In both Master and Slave Modes, all timing is sampled and assert- ed with the rising edge of the CLK pin. In most cases the CS4952/3 will serve as the video timing master. The master timing cannot be exter- nally altered other than through the host interface by changing the video display modes: PAL or NTSC and Progressive Scan. HSYNC , VSYNC and FIELD are configured as outputs for Master Mode. HSYNC can also be defined as a composite blanking output signal in Master Mode. Exact hor- izontal and vertical display timing is addressed in section: Operational Description (page 14). In Slave Mode HSYNC and VSYNC are config- ured as input pins and are used to initialize inde- pendent vertical and horizontal timing generators upon their respective falling edges. FIELD remains an output in Slave Mode. The CS4952/3 also provides a CCIR-656 Slave Mode where the video input stream contains EAV and SAV codes. In this case, proper HSYNC VSYNC timing is extracted automatically without aid from any inputs other than the V [7:0]. CCIR-656 input data is sampled with the leading edge of CLK. Slave Mode vertical and horizontal timing derived via CCIR-656 or external hardware must be equivalent to timing generated by the CS4952/3 in Master Mode. Video Input Formatter The video input formatter translates YCbCr input data into YUV information, if necessary, and splits the luma and chroma information for filtering, scal- ing, and modulation.

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Color Subcarrier Synthesizer The subcarrier synthesizer is a digital frequency synthesizer that produces the correct subcarrier fre- quency for NTSC or PAL. The CS4952/3 generates the color burst frequency based on the input CLK (27 MHz). Color burst accuracy and stability are limited by the accuracy of the 27 MHz input. If the frequency varies then the color burst frequency will also vary accordingly. In order to handle situations in which the CLK var- ies unacceptably, a local crystal frequency refer- ence may be used on the ADDR & XTAL device pins. In this instance the input CLK is continuously compared with the external crystal reference input and the internal timing of the CS4952/3 is automati- cally adjusted so that the color burst frequency re- mains close to the requirements. Controls are provided for phase adjustment of the burst to permit color adjustment and phase com- pensation. Chroma hue control is provided by the CS4952/3 via a 10-bit Hue Control Register (HUE_LSB and H_MSB). Burst amplitude control is also made available to the host via the 8-bit burst amplitude register (SC_AMP). Chroma Path The Video Input Formatter at conclusion delivers 4:2:2 YUV outputs into separate chroma and luma data paths. The chroma path will be discussed here. The chroma output of the Video Input Formatter is directed to a chroma low pass 19-tap FIR filter. The filter bandwidth is selected or the filter may be by- passed via the CONTROL_1 register. The pass- band of the filter is either 650 KHz or 1.3 MHz and the passband ripple is less than or equal to 0.05 dB. The stopband for the 1.3 MHz selection begins at 3 MHz with an attenuation of greater that 35 dB. The stopband for the 650 KHz selection begins around 1.1 MHz with an attenuation of greater than 20 dB. The output of the chroma low pass filter is connect- ed to the chroma interpolation filter where upsam- pling from 4:2:2 to 4:4:4 is accomplished. The chroma digital data is fed to a quadrature modulator where they are combined with the output from the subcarrier synthesizer to produce the proper modu- lated chrominance signal. Following chroma modulation the chroma data passes through a variable gain amplifier where the chroma amplitude may be varied via the C_AMP 8-bit host addressable register. The chroma then is interpolated by a factor of 2 in order to operate the output DACs at 2 times the pixel rate. The interpo- lated filters help reduce the sinx/x roll-off for high- er frequencies and reduce the complexity of the external analog low pass filters. Luma Path Along with the chroma output path, the CS4952/3 Video Input Formatter initiates a parallel luma data path by directing the luma data to a digital delay line. The delay line is built as a digital FIFO where the depth of the FIFO replicates the clock period delay associated with the more complex chroma path. Following the luma delay, the data is passed through a variable gain amplifier where the luma DC values are modifiable via the Y_AMP register. The output of the luma amplifier connects to the sync insertion block. Sync insertion is accom- plished by multiplexing into the luma data path the different sync DC values at the appropriate times. The digital sync generator takes horizontal sync and vertical sync timing signals and generates the appropriate composite sync timing (including ver- tical equalization and serration pulses), blanking information, and burst flag. The sync edge rates conform to RS-170A or CCIR specifications. The luma only path is concluded via output interpo- lation by a factor of two in order to operate the out- put DACs at two times the pixel rate.

Digital to Analog Converters The CS4952/3 provides four complete simulta- neous 27 MHz DACs for analog video output: one 9-bit for S-video chrominance, one 9-bit for S-Vid- eo luminance, and two 9-bit composite outputs. Both S-Video DACs are designed for 37.5Ω over- all loads. The two composite 9-bit DACs are not identical. One DAC is designed to drive 37.5Ω de- rived from a double terminated 75Ω circuit. The second 9-bit DAC is targeted for an on-board local video connection where single point 75Ω termina- tion is sufficient i.e. Ch3/4 RF modulators, video amps, muxes. The DACs can be put into tri-state mode via host addressable control register bits. Each of the four DACs has its own separate DAC enable associated with it. In the disable mode, the 9-bit DACs source or sink zero current. For lower power standby scenarios the CS4952/3 also provides power shut-off control for the DACs. Each DAC has a separate DAC shut-off associated with it. Voltage Reference The CS4952/3 is equipped with an on-board

1.235 V voltage reference generator used by the

Video DACs. For most requirements, the voltage reference output pin can be connected to the volt- age reference input pin along with a decoupling ca- pacitor. Otherwise the voltage reference input may be connected to an external voltage reference. Current Reference The DAC output current per bit is derived in the current reference block. The current step is speci- fied by the size of resistor place between the ISET current reference pin and electrical ground. This has been optimized for 10kΩ (see “ISET” on page 25 for more informmation on selecting the proper ISET value). Host Interface The CS4952/3 provides a parallel 8-bit data inter- face for overall configuration and control. The host interface uses active low read and write strobes along with an active low address enable signal to provide microprocessor compatible read and write cycles. Indirect host addressing to the CS4952/3 in- ternal registers is accomplished via an internal ad- dress register which is uniquely accessible via bus write cycles with the host address enable signal as- serted. The CS4952/3 also provides an I 2C compatible se- rial interface for device configuration and control. This port can operate in standard or fast (400 KHz) modes. When in I 2C mode, the parallel data inter- face PDAT [7:0] pins may be used as a general pur- pose I/O port controlled by the I2C interface. Closed Caption Services The CS4952/3 supports the generation of NTSC Closed Caption services. Line 21 and Line 284 cap- tioning can be generated and enabled independent- ly via a set of control registers. When enabled, clock run-in, start bit, and data bytes are automati- cally inserted at the appropriate video lines. A con- venient interrupt interface simplifies the software interface between the host processor and the CS4952/3. Control Registers The control and configuration of the CS4952/3 is primarily accomplished through the control regis- ter block. All of the control registers are uniquely addressable via the internal address register. The control register bits are initialized during a chip re- set. See the detailed operation section of this data sheet for all of the individual register bit allocations, bit operational descriptions and initialization states.

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CS4952/53 to become operational after RESET. active pixel data on clock cycle 246 (NTSC).

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• • •NTSC 27MHz Clock Count PAL 27MHz Clock Count 1702 1682 active pixel #720 V[7:0] (SYNC_DLY=1) YC rY Cb Y Cr horizontal blanking active pixel active pixel Cb active pixel #719

Figure 6. CCIR601 Input Slave Mode Horizontal Timing

Scan where the display is non-interlaced. Table 1. Vertical Timing the horizontal alignment of the active video.

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• • •NTSC 27MHz Clock Count PAL 27MHz Clock Count CB* (output) 1702 1682 active pixel #720 V[7:0] (SYNC_DLY=1) YC rY Cb Y Cr horizontal blanking active pixel active pixel active pixel #719 Cb

Figure 7. CCIR601 Input Master Mode Horizontal Timing

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Figure 8. Vertical Timing

tive lines of video plus 21.5 lines of blanking.

1. The CS4952/3 exclusively reserves line 284 of

frame and 25 total frames occuring per second. of video plus 24.5 lines of blanking. Figure 9. NTSC Video Interlaced Timming

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Figure 10. PAL Video Interlaced Timing

VSYNC will transition low to begin field one and will remain low for 2.5 lines or (864 x 2.5) 2160 pixel cycles. Digital video input is expected to be delivered to the CS4952/3 V [7:0] pins for 287 lines beginning on active video line 24 and continu- ing through line 310. Field two begins with VSYNC transitioning low after 312.5 lines from the beginning of field one. VSYNC stays low for 2.5 lines times and transi- tions high with the beginning of line 315. Video in- put on the V [7:0] pins is expected between line 336 through line 622. Progressive Scan The CS4952/3 supports a progessive scan mode where the video output is non-interlaced. This is accomplished by displaying only the first video field for NTSC or PAL. To preserve exact MPEG-2 frame rates of 30 and 25 per second, the CS4952/3 displays the same first field repetitively but alter- nately varies the field times. Other digital video en- coders commonly support progressive scan by repetitively displaying a 262 line field (524/525 lines for NTSC). In the long run this method is flawed in that over time, the output display rate will overrun a system clock locked MPEG-2 decom- pressor and display a field twice every 8.75 sec- onds. PAL Progressive Scan VSYNC will transistion low to begin field one and will remain low for for 2.5 lines or (864 x 2.5) 2160 pixel times. Please reference Figure 11 for PAL non-interlaced timing. Digital video input is ex- pected to be delivered to the CS4952/3 V [7:0] pins for 288 lines beginning on active video line 23 and continuing through line 309. Field two begins with VSYNC transitioning low after 312 lines from the beginning of field one. VSYNC stays low for 2.5 line times and transitions high during the middle of line 315. Video input on the V [7:0] pins is expected between line 335 through line 622. Field two is 313 lines long while field one is 312. NTSC Progressive Scan VSYNC will transition low at line 4 to begin field one and will remain low for 3 lines or (858 x 3) 2574 pixel times. Please reference Figure 12 for NTSC interlaced timing. Digital video input is ex- pected to be delivered to the CS4952/3 V [7:0] pins for 240 lines beginning on active video line 22 and continuing through line 261. Field two begins with VSYNC transitioning low at line 266. VSYNC stays low for 2.5 line times and transitions high during the middle of line 268. Vid- eo input on the V [7:0] pins is expected between line 284 through line 524. Field two is 263 lines long while field one is 262. CCIR-656 The CS4952/3 supports an additional Slave Mode feature that is selectable through the CCIR601 bit of the CONTROL_0 register. The CCIR-656 slave feature is unique because the horizontal and verti- cal timing and digital video are combined into a single 8-bit 27 MHz input. With CCIR-656 there are no horizontal and vertical input or output strobes, only 8-bit 27 MHz active CbYCrY data with start and end of video codes being implement- ed with reserved 00 and FF code sequences within the video feed. As with all modes, V [7:0] are sam- pled with the rising edge of CLK. The CS4952/3 expects the digital CCIR-656 stream to be error free. The FIELD output toggles as with non CCIR-656 input. CCIR-656 input timing is illus- trated in Figure 13.

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Figure 11. PAL Video Non-Interlaced Progressive Scan Timing

Figure 12. NTSC Video Non-Interlaced Progressive Scan Timing

4 Clocks

268 Clocks (NTSC)

280 Clocks (PAL)

1440 Clocks

Figure 13. CCIR656 Input Mode Timing

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IN_MODE bit of the CONTROL_0 register.

27 MHz CbYCrY source as input on the V [7:0]

registers as shown in Table 2. ues of 43E0F83Eh following reset. different broadcast formats. lecting a suitable clock source. Table 2. Multi-standard Format Register Configurations

displayed (black and white picture only). insertion on lines 21 and 284 independently. IRE and data high corresponds to 50 IRE. then enable closed caption insertion and interrupts. then clear the interrupt and wait for the next field. VSYNC pins for the color bars to be displayed. luma and chroma values are listed in Table 4. Table 3. Multi-standard Format FSC Register Configurations

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Table 4. Internal Color Bar Values

1. Each interrupt can be individually disabled

with a disable, it must be cleared. detection of address 0x0A can happen in two ways. sheet for exact performance parameters.

The CS4952/3 can operate with or without the aid of an external voltage reference. The CS4952/3 is designed with an internal voltage reference genera- tor that provides a VREFOUT signal. The internal voltage reference is utilized by electrically con- necting the VREFOUT and VREFIN pins. VRE- FIN can also be connected to an external precision 1.235 volt reference. In either case, VREFIN is to be decoupled to ground with a 0.1µF capacitor. Decoupling should be applied as close to the device pin as possible. ISET All four of the CS4952/3 digital to analog converter DACs are output current normalized with a com- mon ISET device pin. The DAC output current per bit is determined by the size of the resistor connect- ed between ISET and electrical ground. Typically a 10 kΩ ±1% metal film resistor should be used. The ISET resistance can be changed by the user to ac- commodate varying video output attenuation via post filters and also to suit individual preferred per- formance. In conjunction with the ISET value, the user may also independently vary the chroma, luma and col- orburst amplitude levels via host addressable con- trol register bits that are used to control internal digital amplifiers. The DAC output levels are de- fined by the following operations: VREFIN/RISET = IREF 1.235 V/10 kΩ = 123.5 µA CVBS37/Y/C Outputs: VOUT (max) = IREF× (8/15)× 511 × 37.5Ω = 1.262 V CVBS75 Output: VOUT (max) = IREF× (4/15)× 511 × 75 Ω = 1.262 V DACs The CS4952/3 is equipped with 4 independent vid- eo grade current output digital to analog converters. They are 9-bit DACs operating at a 27 MHz two times oversampling rate. All four DACs are dis- abled and put in a low power mode upon RESET. All four DACs can be individually powered down and disabled. The output current per bit of all four DACs is determined by the size of resistor connect- ed between the ISET pin and electrical ground. Luminance DAC The Y pin is driven from a 9-bit 27 MHz current output DAC that internally receives the Y or lumi- nance portion of the video signal (black and white intensity and syncronization information only). Y is designed to drive proper video levels into a 37.5Ω load. Reference the detailed electrical sec- tion of this data sheet for the exact Y digital to an- alog AC and DC performance data. A Y_EN enable control bit in the DAC register (0x08) is provided to enable or disable the luminance DAC. For a complete disable and lower power operation the Luminance DAC can be totally shut down via the Y_PD control bit in the DAC register (0x08). In this mode turn-on through the control register will not be instantaneous. Chrominance DAC The C pin is driven from a 9-bit 27 MHz current output DAC that internally receives the C or chrominance portion of the video signal (color only). C is designed to drive proper video levels into a 37.5Ω load. Reference the detailed electrical section of this data sheet for the exact C digital to analog AC and DC performance data. A C_EN en- able control register bit in the DAC register (0x08) is provided to enable or disable the Chrominance DAC. For a complete disable and lower power op- eration the Chrominance DAC can be totally shut down via the C_PD control register bit in the DAC

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register (0x08). In this mode turn-on through the control register will not be instantaneous. CVBS75 DAC The CVBS75 pin is driven from a 9-bit 27 MHz current output DAC that internally receives a com- bined luma and chroma signal to provide compos- ite video output. CVBS75 is designed to drive proper composite video levels into a 75Ω load. Reference the detailed electrical section of this data sheet for the exact CVBS75 digital to analog AC and DC performance data. A C_75_EN enable con- trol register bit in the DAC register (0x08) is provid- ed to enable or disable the ouput pin. When disabled, no current flows from the output. For a complete disable and lower power operation the CVBS75 DAC can be totally shut down via the C_75_PD control register bit in the DAC register (0x08). In this mode turn-on through the control register will not be instantaneous. CVBS37 DAC The CVBS37 pin is driven from a 9-bit 27 MHz current output DAC that internally receives a com- bined luma and chroma signal to provide compos- ite video output. CVBS37 is designed to drive proper composite video levels into a 37.5Ω load. Reference the detailed electrical section of this data sheet for the exact CVBS37 digital to analog AC and DC performance data. The C_37_EN DAC en- able control register bit is in the DAC register (0x08) provided to enable or disable the ouput pin. When disabled, no current flow from the output. For a complete disable and lower power operation the CVBS37 DAC can be totally shut down via the C_37_PD control register bit in the DAC register (0x08). In this mode turn-on through the control register will not be instantaneous.

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extend from internal address 0x00 through 0x3D. Macrovision ACP-PPV Licensed Buyers. Table 5. Control Register Map

Address 0x00 CONTROL_0 Read/Write Default Value = 01h Control Register 1 Address 0x01 CONTROL_1 Read/Write Default Value = 04h B i t N u m b e r 76543210 Bit Name TV_FMT MSTR CCIR656 PROG IN_MODE CBCR_UV D e f a u l t00000001 Bit Mnemonic Function 7:5 TV_FMT selects the TV display format 000: NTSC-M CCIR601 timing (default) 001: NTSC-M RS170A timing 010: PAL-B, D, G, H, I 011: PAL-M 100: PAL-N (Argentina) 101: PAL-N (non Argentina) 110-111: reserved

4 MSTR 1: Master Mode, 0: Slave Mode

3 CCIR656 video input is in CCIR656 format (0: off, 1: on)

2 PROG Progressive scanning enable (enable with 1)

1 IN_MODE Input select (0: solid background, 1: use V [7:0] data)

0 CBCR_UV enable YCbCr to YUV conversion (1: enable, 0: disable)

B i t N u m b e r 76543210 Bit Name CBLANK Y_DELAY C_BW C_LPF_EN FLD PED CBAR CBCRSEL D e f a u l t 00000100 Bit Mnemonic Function

7 CBLANK Composite Blank / HSYNC output select (1: CB, 0: HSYNC)

6 Y_DELAY luma to chroma delay (0: no delay, 1: luma is delayed by one 13.5 MHz cycle) 5 C_BW chroma lpf bandwidth (0: 650 KHz, 1: 1.3 MHz)

4 C_LPF_EN chroma lpf on/off (0: off, 1: on)

3 FLD Polarity of Field (0: odd field - 0, 1: odd field - 1)

2 PED Pedestal offset (0: 0 IRE, 1: 7.5 IRE)

1 CBAR internal color bar generator (0: off, 1: on)

0 CBCRSEL CbCr select (0: chroma undelayed, 1: chroma delayed by one clock)

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Address 0x02 CONTROL_2 Read/Write Default Value = 00h DAC Power Down Register Address 0x04 DAC Read/Write Default Value = F0h B i t N u m b e r 7654321 0 Bit Name RESERVED SYNC_DLY XTAL SC_EN D e f a u l t0000000 0 Bit Mnemonic Function 7:4 - reserved 3Y _ B W Selects between 4.2 Mhz and 6 Mhz on-chip luminance low pass filters; default value is zero which selects the 4.2 Mhz low pass filter option

2 SYNC_DLY

Delays expected timing of first active pixel input data relative to falling edge of HSYNC from 245 27 MHz clock cycles to 246 for NTSC and from 265 to 266 for PAL. Default State is SYNC_DLY=0 for no delay

1 XTAL Crystal oscillator for subcarrier adjustment enable (1: enable)

0 SC_EN Chroma burst disable (1: disable)

B i t N u m b e r 76543210 Bit Name C_75_PD C_37_PD Y_PD C_PD C_75_EN C_37_EN Y_EN C_EN D e f a u l t11110000 Bit Mnemonic Function

7 C_75_PD power down composite DAC with 75 Ω load (0: power up, 1: power down)

6 C_37_PD power down composite DAC with 37.5 Ω load (0: power up, 1: power down)

5 Y_PD power down luma s-video DAC (0: power up, 1: power down)

4 C_PD power down chroma s-video DAC (0: power up, 1: power down)

3 C_75_EN enable composite video DAC output for 75 Ω (0: tri-state, 1: enable)

2 C_37_EN enable composite video DAC output for 37.5 Ω (0: tri-state, 1: enable)

1 Y_EN enable s-video DAC for luma output (0: tri-state, 1: enable)

0 C_EN enable s-video DAC for chroma output (0: tri-state, 1: enable)

Address 0x07 STATUS Read Only Default Value = 00h Background Color Register Address 0x08 BKG_COLOR Read/Write Default Value = 03h GPIO Control Register Address 0x09 GPIO_CTRL_REG Read/Write Default Value = 00h B i t N u m b e r 76 5 4 3 210 Bit Name RESERVED CC_INT_21 CC_INT_284 VS_INT FIELD Default 0 0 0 0 0 0 0 0 Bit Mnemonic Function 7:6 - reserved

5 CC_INT_21 Interrupt flag for line 21 (closed caption) complete

4 CC_INT_284 Interrupt flag for line 284 (closed caption) complete

3 VS_INT Interrupt flag for video field change

2:0 FIELD Field Status bits 000: field 8 001: field 1 010: field 2 011: field 3 100: field 4 101: field 5 110: field 6 111: field 7 B i t N u m b e r 76543210 Bit Name BG_COLR D e f a u l t00000011 Bit Mnemonic Function 7:0 BG_COLR Background color (7:5 = R, 4:2 = G, 1:0 = B) B i t N u m b e r 76543210 Bit Name GPIO_IO D e f a u l t00000000 Bit Mnemonic Function 7:0 GPIO_IO input(0)/output(1) control of GPIO registers (bit X: PDAT(X) I/O configuration)

32 DS223PP2

Address 0x0A GPIO_DATA_REG Read/Write Default Value = 00h Chroma Filter Register Address 0x0D C_AMP Read/Write Default Value = 80h Luma Filter Register Address 0x0E Y_AMP Read/Write Default Value = 80h I2C Address Register Address 0x0F I2C_ADR Read/Write Default Value = N/A B i t N u m b e r 76543210 Bit Name GPIO_DATA D e f a u l t00000000 Bit Mnemonic Function 7:0 GPIO_DATA GPIO data register; data is output on PDAT [7:0] bus if appropriate bit in GPIO_CTRL_REG (0x09) is set to “1”; data on PDAT [7:0] is latched into GPIO_DATA_REG [7:0] when register address 0x0A is accessed via I 2C. This register is only accessible in I2C mode. B i t N u m b e r 76543210 Bit Name C_COEF D e f a u l t10000000 Bit Mnemonic Function 7:0 C_COEF Chroma amplitude coefficient B i t N u m b e r 76543210 Bit Name Y_COEF D e f a u l t10000000 Bit Mnemonic Function 7:0 Y_COEF Luma amplitude coefficient B i t N u m b e r 7 6543210 Bit Name RESERVED ADDR Bit Mnemonic Function 7 - reserved 6:0 ADDR I 2C device address (programmable)

Subcarrier Amplitude Register Address 0x10 SC_AMP Read/Write Default Value = 1Ch Subcarrier Synthesis Register Address 0x11 SC_SYNTH0 Read/Write Default Value = 3Eh 0x12 SC_SYNTH1 F8h 0x13 SC_SYNTH2 E0h 0x14 SC_SYNTH3 43h Hue LSB Adjust Register Address 0x15 HUE_LSB Read/Write Default Value = 00h Hue MSB Adjust Register Address 0x16 HUE_MSB Read/Write Default Value = 00h B i t N u m b e r 76543210 Bit Name AMP D e f a u l t00011100 Bit Mnemonic Function 7:0 AMP Color burst amplitude Register Bits Mnemonic Function SC_SYNTH0 7:0 - Subcarrier synthesis bits 7:0 SC_SYNTH1 7:0 - Subcarrier synthesis bits 15:8 SC_SYNTH2 7:0 - Subcarrier synthesis bits 23:16 SC_SYNTH3 7:0 - Subcarrier synthesis bits 31:24 B i t N u m b e r 76543210 Bit Name LSB D e f a u l t00000000 Bit Mnemonic Function 7:0 LSB 8 LSBs for hue phase shift B i t N u m b e r 76543210 Bit Name RESERVED MSB D e f a u l t00000000 Bit Mnemonic Function 7:2 - reserved 1:0 MSB 2 MSBs for hue phase shift

34 DS223PP2

Closed Caption Enable Register Address 0x18 CC_EN Read/Write Default Value = 00h Closed Caption Data Register Address 0x19 CC_21_1 Read/Write Default Value = 00h 0x1A CC_21_2 00h 0x1B CC_284_1 00h 0x1C CC_284_2 00h Interrupt Enable Register Address 0x3B INT_EN Read/Write Default Value = 00h B i t N u m b e r 76543210 Bit Name RESERVED EN_284 EN_21 D e f a u l t00000000 Bit Mnemonic Function 7:2 - reserved

1 EN_284 enable closed caption for line 284

0 EN_21 enable closed caption for line 21

Register Bit Mnemonic Function CC_21_1 7:0 - first closed caption databyte of line 21 CC_21_2 7:0 - second closed caption databyte of line 21 CC_284_1 7:0 - first closed caption databyte of line 284 CC_284_2 7:0 - second closed caption databyte of line 284 B i t N u m b e r 76543210 Bit Name RESERVED EN_21 EN_284 VS_EN D e f a u l t00000000 Bit Mnemonic Function 7:3 - reserved

2 EN_21 interrupt enable for closed caption line 21

1 EN_284 interrupt enable for closed caption line 284

0 VS_EN interrupt enable for new field

Address 0x3C INT_CLR Read/Write Default Value = 00h Device ID Register Address 0x3D ID_REG Read Only Default Value = N/A B i t N u m b e r 76543210 Bit Name RESERVED CLR_21 CLR_284 VS_CLR D e f a u l t00000000 Bit Mnemonic Function 7:3 - reserved

2 CLR_21 clear interrupt for closed caption line 21 (INT_21)

1 CLR_284 clear interrupt for closed caption line 284 (INT_284)

0 VS_CLR clear interrupt for new video field (INT_V)

B i t N u m b e r 76543210 Bit Name DEV_ID RESERVED Default 0 0 0 0 - - - - Bit Mnemonic Function 7:4 DEV_ID 0000 device ID for CS4952 0001 device ID for CS4953 3:0 - These bits are reserved and the value they return on a read is not defined

36 DS223PP2

BOARD DESIGN & LAYOUT CONSIDERATIONS The printed circuit layout should be optimized for lowest noise on the CS4952/3 power and ground lines. Digital and analog sections should be physi- cally separated and the CS4952/3 placed as close to the output connectors as possible. All analog sup- ply traces should be as short as possible to mini- mize inductive ringing. A well designed power distribution network is es- sential in eliminating digital switching noise. The ground planes must provide a low-impedance re- turn path for the digital circuits. A PC board with a minimum of four layers is recommended. The ground layer should be used as a shield to isolate noise from the analog traces. The top layer (1) should be reserved for analog traces but digital traces may share this layer if the digital signals have low edge rates and switch little current or if they are separated from the analog traces by a sig- nificant distance (dependent on their frequency content and current). The second layer should then be the ground plane followed by the analog power plane on layer three and the digital signal layer on layer four Power and Ground Planes The power and ground planes need isolation gaps of at 0.05” to minimize digital switching noise ef- fects on the analog signals and components. A split analog/digital ground plane should be connected at one point as close as possible to the CS4952/3. A split analog/digital power plane should be connect- ed at one point as close as possible to the power en- try point and decoupled properly. Power Supply Decoupling Start by reducing power supply ripple and wiring harness inductance by placing a large (33 - 100uF) capacitor as close to the power entry point as pos- sible. Use separate power planes or traces for the digital and analog sections even if they use the same supply. If necessary, further isolate the digital and analog power supplies by using ferrite beads on each supply branch followed by a low ESR capac- itor. Place all decoupling caps as close as possible to the device as possible. Surface mount capacitors gen- erally have lower inductance than radial lead or ax- ial lead components. Surface mount caps should be placed on the component side of the PCB to mini- mize inductance caused by board vias. Any vias, especially to ground, should be as large as practical to reduce their inductive effects. VREF Decoupling The VREFOUT pin provides a 1.235 V reference for the internal DACs. VREFOUT is only intended to drive VREFIN. Do not connect to an external load. A small bypass cap, however, may be placed on VREFOUT to reduce noise. Usually a 0.1uF MLC surface mount capacitor is sufficient. Digital Interconnect The digital inputs and outputs of the CS4952/3 should be isolated from the analog outputs as much as possible. Use separate signal layers whenever possible and do not route digital signals over the analog power and ground planes. Noise from the digital section is directly related to the digital edge rates used. Ringing, overshoot, un- dershoot, and ground bounce are all related to edge rate. Use lower speed logic such as HCMOS for the host port interface to reduce switching noise. For the video input ports, higher speed logic is re- quired, but use the slowest practical edge rate to re- duce noise. To reduce digital noise, it is important to match the source impedance, line impedance, and load im- pedance as much as possible. Generally, if the line length is greater than one fourth the signal edge rate, line termination is necessary. Ringing may also be reduced by damping the line with a series resistor (22 - 150Ω ). Under extreme cases, it may

use proper RF decoupling techniques. used analog outputs should be placed in shutdown. mize high frequency power supply rejection. lowing low pass filter in Figure 15 can be used. Figure 15. Low Pass Filter

38 DS223PP2

C Y VREFOUT VREFIN ISET VAA GND RESET SCL SDA INT CLKIN WR RD PDAT0 PDAT1 PDAT2 PDAT3 PDAT4 PDAT5 PDAT6 PDAT7 DEVICE PINOUT - 44 PLCC

Pin Name Pin Number Type Description V [7:0] 14, 13, 12, 11, 10, 9, 8, 7 IN Digital video data inputs CLK 33 IN 27 MHz input clock ADDR 19 IN Address enable line / subcarrier crystal input XTAL 18 OUT subcarrier crystal output HSYNC /CB 16 I/O Active low horizontal sync, or composite blank signal VSYNC 17 I/O Active low vertical sync. FIELD 15 OUT Video field ID. Selectable polarity RD 31 IN Host parallel port read strobe, active low WR 32 IN Host parallel port write strobe, active low PDAT [7:0] 23,24,25,26,27,28,29,30 I/O Host parallel port/ general purpose I/O SDA 35 I/O I 2C data SCL 36 IN I 2C clock input CVBS75 5 CURRENT Composite video output for driving 75 Ω loads CVBS37 4 CURRENT Composite video output for driving 37.5 Ω loads Y 43 CURRENT Luminance analog output for driving 37.5 Ω loads C 44 CURRENT Chrominance analog output for driving 37.5 Ω loads VREFOUT 42 OUT Internal voltage reference output VREFIN 41 IN External voltage reference input ISET 40 OUT DAC current set INT 34 OUT Interrupt output, active high RESET

37 IN Active low master reset

TEST 6 IN TEST pin. Ground for normal operation VAA 1, 3, 20, 39 PS +5 V supply GND 2, 22, 21, 38 PS Ground

40 DS223PP2

A 0.165 0.180 4.043 4.572 A1 0.090 0.120 2.205 3.048 B 0.013 0.021 0.319 0.533 D 0.685 0.695 16.783 17.653 D1 0.650 0.656 15.925 16.662 D2 0.590 0.630 14.455 16.002 E 0.685 0.695 16.783 17.653 E1 0.650 0.656 15.925 16.662 E2 0.590 0.630 14.455 16.002 e 0.040 0.060 0.980 1.524 JEDEC # : MS-018 44L PLCC PACKAGE DRAWING D E1 E D2/E2 B e A

C Y VREFOUT VREFIN ISET VAA GND RESET SCL SDA INT CLKIN WR RD PDAT0 PDAT1 PDAT2 PDAT3 PDAT4 PDAT5 PDAT6 PDAT7 CS4952/3-CL 44-pin TQFP Top View 404244 34 3638 14 16 18 20 22 DEVICE PINOUT - 44 TQFP

42 DS223PP2

Pin Name Pin Number Type Description V [7:0] 8, 7, 6, 5, 4, 3, 2, 1 IN Digital video data inputs CLKIN 27 IN 27 MHz input clock ADDR 13 IN Address enable line / subcarrier crystal input XTAL 12 OUT subcarrier crystal output HSYNC /CB 10 I/O Active low horizontal sync, or composite blank signal VSYNC 11 I/O Active low vertical sync. FIELD 9 OUT Video field ID. Selectable polarity RD 25 IN Host parallel port read strobe, active low WR 26 IN Host parallel port write strobe, active low PDAT [7:0] 17,18,19,20,21,22,23,24 I/O Host parallel port/ general purpose I/O SDA 29 I/O I 2C data SCL 30 IN I 2C clock input CVBS75 43 CURRENT Composite video output for driving 75 Ω loads CVBS37 42 CURRENT Composite video output for driving 37.5 Ω loads Y 37 CURRENT Luminance analog output for driving 37.5 Ω loads C 38 CURRENT Chrominance analog output for driving 37.5 Ω loads VREFOUT 36 OUT Internal voltage reference output VREFIN 35 IN External voltage reference input ISET 34 OUT DAC current set INT 28 OUT Interrupt output, active high RESET

31 IN Active low master reset

TEST 44 IN TEST pin. Ground for normal operation VAA 14, 33, 39, 41 PS +5 V supply GND 15, 16, 32, 40 PS Ground

A 0.000 0.065 0.000 1.600 A1 0.002 0.006 0.050 0.150 B 0.012 0.018 0.300 0.450 D 0.478 0.502 11.700 12.300 D1 0.404 0.412 9.900 10.100 E 0.478 0.502 11.700 12.300 E1 0.404 0.412 9.900 10.100 e 0.029 0.037 0.700 0.900 L 0.018 0.030 0.450 0.750 ∝ 0.000 7.000 0.000 7.000 JEDEC # : MS-026 44L TQFP PACKAGE DRAWING E1 E D e L B A