CS49326

CS49300 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

zCS4930X: DVD Audio Sub-family — PES Layer decode for A/V sync — DVD Audio Pack Layer Support — Meridian Lossless Packing Specification (MLP)™ — Dolby Digital™, Dolby Pro Logic II™ — MPEG-2, Advanced Audio Coding Algorithm (AAC) — MPEG Multichannel — DTS Digital Surround™, DTS-ES Extended Surround™ zCS4931X: Broadcast Sub-family — PES Layer decode for A/V sync — Dolby Digital — MPEG-2, Advanced Audio Coding Algorithm (AAC) — MPEG-1 (Layers 1, 2, 3) Stereo — MPEG-2 (Layers 2, 3) Stereo zCS4932X: AVR Sub-family — Dolby Digital, Dolby Pro Logic II — DTS & DTS-ES decoding with integrated DTS tables — Cirrus Original Surround 5.1 PCM Enhancement — MPEG-2, Advanced Audio Coding Algorithm (AAC) — MPEG Multichannel — MP3 (MPEG-1, Layer 3) zCS49330: General Purpose Audio DSP —T H X ® Surround EX™ and THX ® Ultra2 Cinema — General Purpose AVR and Broadcast Audio Decoder (MPEG Multichannel, MPEG Stereo, MP3, C.O.S.) — Car Audio zFeatures are a super-set of the CS4923/4/5/6/7/8/9 — 8 channel output, including dual zone output capability — Dynamic Channel Remapability — Supports up to 192 kHz Fs @ 24-bit throughput — Increased memory/MIPs — SRAM Interface for increased delay and buffer capability — Dual-Precision Bass Manager — Enhance your system functionality via firmware upgrades through the Crystal Ware TM Software Licensing Program

Description

The CS493XX is a family of multichannel audio decoders intended to supersede the CS4923/4/5/6/7/8/9 family as the leader of audio decoding in both the DVD, broadcast and receiver markets. The family will be split into parts tailored for each of these distinct market segments. For the DVD market, parts will be offered which support Meridian Lossless Packing (MLP), Dolby Digital, Dolby Pro Logic II, MPEG Multichannel, DTS Digital Surround, DTS-ES, AAC, and subsets thereof. For the receiver market, parts will be offered which support Dolby Digital, Dolby Pro Logic II, MPEG Multichannel, DTS Digital Surround, DTS-ES, AAC, and various virtualizers and PCM enhancement algorithms such as HDCD DTS Neo:6TM, LOGIC7®, and SRS Circle Surround II®. For the broadcast market, parts will be offered which support Dolby Digital, AAC, MPEG-1, Layers 1,2 and 3, MPEG-2, Layers 2 and Under the Crystal brand, Cirrus Logic is the only single supplier of high-performance 24-bit multi-standard audio DSP decoders, DSP firmware, and high-resolution data converters. This combination of DSPs, system firmware, and data converters simplify rapid creation of world-class high-fidelity digital audio products for the Internet age. Ordering Information: See page 85 APPLICATION CORE DECODER FUNCTIONALITY CS49300 DVD Audio MLP, AC-3, AAC, DTS, MPEG 5.1, MP3, etc. CS49310 Broadcast AAC, AC-3, MPEG Stereo, MP3, etc. CS49311 Broadcast AAC, MPEG Stereo, MP3, etc. CS49312 Broadcast AC-3, MPEG Stereo, MP3, etc. CS49325 AVR AC-3, COS, MPEG 5.1, MP3, etc. CS49326 AVR AC-3, DTS, COS, MPEG 5.1, MP3, etc. CS49329 AVR AC-3, AAC, DTS, MPEG 5.1, MP3, etc. CS49330 Car Audio DSP Car Audio Code CS49330 General Purpose MPEG 5.1, MPEG Stereo, MP3, C.O.S., etc CS49330 Post-Processor DPP, THX Surround EX, THX Ultra2 Cinema DATA7:0, CS Parallel or Serial Host Interface CMPCLK, Compressed PLL FILT1 VA Framer DD DC MCLK SCLK LRCLK AUDATA[2.0] XMT958/AUDATA3 CMPDAT, SCLKN2 CMPREQ, LRCLKN2 SCLKN1, STCCLK2 LRCLKN1 SDATAN1 Data Input Interface Digital Audio Input Interface FILT2 AGND Clock Manager CLKIN CLKSEL Shifter Input Buffer Controller RAM Input Buffer DGND[3:1] VD[3:1] 24-Bit DSP Processing RAM Program Memory RAM Data Memory ROM Program Memory ROM Data Memory STC EMAD7:0, GPIO7:0 R/W, EMOE, GPIO11 RD, DS, EMWR, GPIO10 WR, SCDOUT, PSEL, GPIO9 SCDIO, A0, SCCLK A1, SCDIN ABOOT, INTREQ EXTMEM, GPIO8 Output FormatterRAM Buffer Output RESET SDATAN2 MAR ‘02 DS339PP4

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1.5 Switching Characteristics — RESET

1.7 Switching Characteristics — Intel

Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts Dolby Digital, AC-3, Dolby Pro Logic, Dolby Pro Logic II, Dolby Surround, Surround EX, Virtual Dolby Digital, MLP and the “AAC” logo are trademarks and the “Dolby Digital” logo, “Dolby Digital with Pro Logic II” logo, “Dolby” and the double-”D” symbol are registered trademarks of Dolby Laboratories Licensing Corporation. DTS, DTS Digital Surround, DTS-ES Extended Surround, DTS Neo:6, and DTS Virtual 5.1 are trademarks and t he “DTS”, “DTS-ES”, “DTS Virtual 5.1” logos are registered trademarks of the Digital Theater Systems Corporation. The “MPEG Logo” is a registered trademark of Philips Electronics N.V. Home THX Cinema and THX are registered trademarks of Lucasfilm Ltd. Surround EX is a jointly develo ped technology of THX and Dolby Labs, Inc. AAC (Advanced Audio Coding) is an “MP EG-2-standard-based” digital audio compression algorithm (offe ring up 5.1 discrete decoded channels for this implementation) collaboratively developed by AT&T, the Fraunhofer Institute, Dolby Laborator ies, and the Sony Corporation. In regards to the MP3 capable functionality of the CS49300 Family DSP (via downloading of mp3_493xxx_vv.ld and mp3e_493xxx_vv.ld application codes) the following statements are applicable: “Supply of this product conveys a license for personal, private and non-commercial use. MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and THOMSON Multimedia.” MLP and Meridian Lossless Packing are registered trademarks of Meridian Audio Ltd. Harman VMAx is a re gistered trademark of Harman International. The LOGIC7 logo and LOGIC7 are registered trademarks of Lexicon. SRS Circle Surround, and SRS TruSurround are trademarks of SRS Labs, Inc. The HDCD logo, HDCD , High Definition Compatible Digital and Pacific Microsonics are either registered trademarks or trademarks of Pacific Microsonics, Inc. in the United States and/or other countries. HDCD technology provided under license from Pacific Microsonics, Inc. This product’s software is covered by one or more of the following in the United States: 5,479,168; 5,638,074; 5,640,161; 5,872,531; 5,808,574; 5,838,274; 5,854,600; 5,864,311; and in Australia: 669114; with other patents pending. Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductor. Purchase of I 2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I 2C Patent Rights to use those components in a standard I 2C system. The “Cirrus Logic Logo” is a registered trademark of Cirrus Logic, Inc. All other names are trademarks, registered trademarks, or service marks of their respective com panies. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic web site or disk may be printed for use by the user. Howeve r, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transm itted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

6.1.2 I

8.2.1 Autoboot INTREQ

10.1.1 I

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Figure 3. Intel Figure 13. I

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1. CHARACTERISTICS AND SPECIFICATIONS 1.1. Absolute Maximum Ratings (AGND, DGND = 0 V; all voltages with respect to 0 V) CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 1.2. Recommended Operating Conditions (AGND, DGND = 0 V; all voltages with respect to 0 V) 1.3. Digital D.C. Characteristics (TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; measurements performed under static conditions.) 1.4. Power Supply Characteristics (TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; measurements performed under operating conditions) Parameter Symbol Min Max Unit DC power supplies: Positive digital Positive analog VD VA –0.3 –0.3 2.75 2.75 0.3 V V V Input current, any pin except supplies I in - ±10 mA Digital input voltage V IND –0.3 3.63 V Storage temperature T stg –65 150 °C Parameter Symbol Min Typ Max Unit DC power supplies: Positive digital Positive analog VD VA 2.37 2.37 2.5 2.5 2.63 2.63 0.3 V V V Ambient operating temperature T A 0- 7 0 °C Parameter Symbol Min Typ Max Unit High-level input voltage V IH 2.0 - - V Low-level input voltage V IL --0 . 8V High-level output voltage at IO = –2.0 mA V OH VD × 0.9 - - V Low-level output voltage at IO = 2.0 mA V OL -- V D × 0.11 V Input leakage current I in --1 . 0 µA Parameter Symbol Min Typ Max Unit Power supply current: Digital operating: VD[3:1] Analog operating: VA 200 1.7 310 mA mA

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1.7. Switching Characteristics — Intel ® Host Mode (TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP = 1/DCLK. The DSP clock can be defined as follows: External CLKIN Mode: DCLK == CLKIN/4 before and during boot DCLK == CLKIN after boot Internal Clock Mode: DCLK == 10MHz before and during boot, i.e. DCLKP == 100ns DCLK == 65 MHz after boot, i.e. DCLKP == 15.4ns It should be noted that DCLK for the internal clock mode is application specific. The application code users guide should be checked to confirm DCLK for the particular application. 2. This specification is characterized but not production tested. A 470 ohm pull-up resistor was used for characterization to minimize the effects of external bus capacitance. 3. See T idd from Intel Host Mode in Table 6 on page 43 Parameter Symbol Min Max Unit Address setup before CS and RD low or CS and WR low Tias 5- n s Address hold time after CS and RD low or CS and WR low Tiah 5- n s Delay between RD then CS low or CS then RD low Ticdr 0 ∞ ns Data valid after CS and RD low (Note 3) Tidd -2 1 n s CS and RD low for read (Note 1) Tirpw DCLKP + 10 - ns Data hold time after CS or RD high Tidhr 5- n s Data high-Z after CS or RD high (Note 2) Tidis -2 2 n s CS or RD high to CS and RD low for next read (Note 1) Tird 2*DCLKP + 10 - ns CS or RD high to CS and WR low for next write (Note 1) Tirdtw 2*DCLKP + 10 - ns Delay between WR then CS low or CS then WR low Ticdw 0 ∞ ns Data setup before CS or WR high Tidsu 20 - ns CS and WR low for write (Note 1) Tiwpw DCLKP + 10 - ns Data hold after CS or WR high Tidhw 5- n s CS or WR high to CS and RD low for next read (Note 1) Tiwtrd 2*DCLKP + 10 - ns CS or WR high to CS and WR low for next write (Note 1) Tiwd 2*DCLKP + 10 - ns

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1.8. Switching Characteristics — Motorola ® Host Mode (TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP = 1/DCLK. The DSP clock can be defined as follows: External CLKIN Mode: DCLK == CLKIN/4 before and during boot DCLK == CLKIN after boot Internal Clock Mode: DCLK == 10MHz before and during boot, i.e. DCLKP == 100ns DCLK == 65 MHz after boot, i.e. DCLKP == 15.4ns It should be noted that DCLK for the internal clock mode is application specific. The application code users guide should be checked to confirm DCLK for the particular application. 2. This specification is characterized but not production tested. A 470 ohm pull-up resistor was used for characterization to minimize the effects of external bus capacitance. 3. See T mdd from Motorola Host Mode in Table 7 on page 45 Parameter Symbol Min Max Unit Address setup before CS and DS low Tmas 5- n s Address hold time after CS and DS low Tmah 5- n s Delay between DS then CS low or CS then DS low Tmcdr 0 ∞ ns Data valid after CS and RD low with R/W high (Note 3) Tmdd -2 1 n s CS and DS low for read (Note 1) Tmrpw DCLKP + 10 - ns Data hold time after CS or DS high after read Tmdhr 5- n s Data high-Z after CS or DS high low after read (Note 2) Tmdis -2 2 n s CS or DS high to CS and DS low for next read (Note 1) Tmrd 2*DCLKP + 10 - ns CS or DS high to CS and DS low for next write (Note 1) Tmrdtw 2*DCLKP + 10 - ns Delay between DS then CS low or CS then DS low Tmcdw 0 ∞ ns Data setup before CS or DS high Tmdsu 20 - ns CS and DS low for write (Note 1) Tmwpw DCLKP + 10 - ns R/W setup before CS AND DS low Tmrwsu 5- n s R/W hold time after CS or DS high Tmrwhld 5- n s Data hold after CS or DS high Tmdhw 5- n s CS or DS high to CS and DS low with R/W high for next read (Note 1) Tmwtrd 2*DCLKP + 10 - ns CS or DS high to CS and DS low for next write (Note 1) Tmwd 2*DCLKP + 10 - ns

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1.9. Switching Characteristics — SPI Control Port (TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes: 1. The specification f sck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the software. The relevant application code user’s manual should be consulted for the software speed limitations. 2. Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK. 3. SCDOUT should not be sampled during this time period. 4. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the second-to-last bit of the last byte of data during a read operation as shown. 5. If INTREQ goes high as indicated in (Note 4), then INTREQ is guaranteed to remain high until the next rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat this condition as a new read transaction. Raise chip select to end the current read transaction and then drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start a new read transaction. 6. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time. 7. This time is by design and not tested. Parameter Symbol Min Max Units SCCLK clock frequency (Note 1) f sck - 2000 kHz CS falling to SCCLK rising t css 20 - ns Rise time of SCCLK line (Note 7) t r -5 0 n s Fall time of SCCLK lines (Note 7) t f -5 0 n s SCCLK low time t scl 150 - ns SCCLK high time t sch 150 - ns Setup time SCDIN to SCCLK rising t cdisu 50 - ns Hold time SCCLK rising to SCDIN (Note 2) t cdih 50 - ns Transition time from SCCLK to SCDOUT valid (Note 3) t scdov -4 0 n s Time from SCCLK rising to INTREQ rising (Note 4) t scrh - 200 ns Rise time for INTREQ (Note 4) t rr - (Note 6) ns Hold time for INTREQ from SCCLK rising (Note 5, 7) t scrl 0- n s Time from SCCLK falling to CS rising t sccsh 20 - ns High time between active CS tcsht 200 - ns Time from CS rising to SCDOUT high-Z (Note 7) t cscdo 20 ns

Figure 7. SPI Control Port Timing

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1.10. Switching Characteristics — I 2C® Control Port (TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes:. 1. The specification f scl indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the software. The relevant application code user’s manual should be consulted for the software speed limitations. 2. Data must be held for sufficient time to bridge the 300-ns transition time of SCCLK. This hold time is by design and not tested. 3. This rise time is shorter than that recommended by the I2C specifications. For more information, see Section 6.1, “Serial Communication” on page 33. 4. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the last data bit of the last byte of data during a read operation as shown. 5. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat this condition as a new read transaction. Send a new start condition followed by the 7-bit address and the R/W bit (set to 1 for a read). This time is by design and is not tested. 6. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time. 7. This time is by design and not tested. Parameter Symbol Min Max Units SCCLK clock frequency (Note 1) f scl 400 kHz Bus free time between transmissions t buf 4.7 µs Start-condition hold time (prior to first clock pulse) t hdst 4.0 µs Clock low time t low 1.2 µs Clock high time t high 1.0 µs SCDIO setup time to SCCLK rising t sud 250 ns SCDIO hold time from SCCLK falling (Note 2) t hdd 0 µs Rise time of SCCLK (Note 3), (Note 7) t r 50 ns Fall time of SCCLK (Note 7) t f 300 ns Time from SCCLK falling to CS493XX ACK t sca 40 ns Time from SCCLK falling to SCDIO valid during read operation t scsdv 40 ns Time from SCCLK rising to INTREQ rising (Note 4) t scrh 200 ns Hold time for INTREQ from SCCLK rising (Note 5) t scrl 0n s Rise time for INTREQ (Note 6) t rr ** ns Setup time for stop condition t susp 4.7 µs

Figure 8. I2C® Control Port Timing

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1.11. Switching Characteristics — Digital Audio Input (TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes: 1. Master mode timing specifications are characterized, not production tested. 2. Master mode is defined as the CS493XX driving LRCLKN1(2) and SCLKN1(2). Master or Slave mode can be programmed. 3. This timing parameter is defined from the non-active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid. 4. This timing parameter is defined from the active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid. 5. Slave mode is defined as SCLKN1(2) and LRCLKN1(2) being driven by an external source. Parameter Symbol Min Max Unit SCLKN1(2) period for both Master and Slave mode (Note 1) T sclki 40 - ns SCLKN1(2) duty cycle for Master and Slave mode (Note 1) 45 55 % Master Mode (Note 1, 2) LRCLKN1(2) delay after SCLKN1(2) transition (Note 3) T lrds -1 0 n s SDATAN1(2) setup to SCLKN1(2) transition (Note 4) T sdsum 10 - ns SDATAN1(2) hold time after SCLKN1(2) transition (Note 4) T sdhm 5- n s Slave Mode (Note 5) Time from active edge of SCLKN1(2) to LRCLKN1(2) transition T stlr 10 - ns Time from LRCLKN1(2) transition to SCLKN1(2) active edge T lrts 10 - ns SDATAN1(2) setup to SCLKN1(2) transition (Note 4) T sdsus 5- n s SDATAN1(2) hold time after SCLKN1(2) transition (Note 4) T sdhs 5- n s

Figure 9. Digital Audio Input Data, Master and Slave Clock Timing

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users guide should be checked to confirm DCLK for the particular application. Figure 10. Serial Compressed Data Timing Figure 11. Parallel Data Timing (when not in a parallel control mode)

1.14. Switching Characteristics — Digital Audio Output (TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes: 1. MCLK can be an input or an output. These specifications apply for both cases. 2. Master mode timing specifications are characterized, not production tested. 3. Master mode is defined as the CS493XX driving both SCLK and LRCLK. When MCLK is an input, it is divided to produce SCLK and LRCLK. 4. This timing parameter is defined from the non-active edge of SCLK. The active edge of SCLK is the point at which the data is valid. 5. Slave mode is defined as SCLK and LRCLK being driven by an external source. 6. This specification is characterized, not production tested. Parameter Symbol Min Max Unit MCLK period (Note 1) T mclk 40 - ns MCLK duty cycle (Note 1) 40 60 % SCLK period for Master or Slave mode (Note 2) T sclk 40 - ns SCLK duty cycle for Master or Slave mode (Note 2) 45 55 % Master Mode (Note 2, 3) SCLK delay from MCLK rising edge, MCLK as an input T sdmi 15 ns SCLK delay from MCLK rising edge, MCLK as an output T sdmo –5 10 ns LRCLK delay from SCLK transition (Note 4) T lrds 10 ns AUDATA2–0 delay from SCLK transition (Note 4) T adsm 10 ns Slave Mode (Note 5) Time from active edge of SCLKN1(2) to LRCLKN1(2) transition T stlr 10 - ns Time from LRCLKN1(2) transition to SCLKN1(2) active edge T lrts 10 - ns AUDATA2–0 delay from SCLK transition (Note 4, 6) T adss 15 ns

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Figure 12. Digital Audio Output Data, Input and Output Clock Timing

1. FAMILY OVERVIEW The CS49300 family contains system on a chip solutions for multichannel audio decompression and digital signal processing. The CS49300 family is split into 4 sub-families targeted at the DVD, broadcast and audio/video receiver (AVR), and effects and post processing markets. This document focuses on the electrical features and characteristics of these parts. Different features are described from a hardware design perspective. It should be understood that not all of the features portrayed in this document are supported by all of the versions of application code available. The application code user’s guides should be consulted to confirm which hardware features are supported by the software. The parts use a combination of internal ROM and RAM. Depending on the application being used, a download of application software may be required each time the part is powered up. This document uses “download” and “code load” interchangeably. These terms should be interpreted as meaning the transfer of application code into the internal memory of the part from either an external microcontroller or through the autoboot procedure. 2.1. Multichannel Decoder Family of Parts CS49300 - DVD Audio Decoder . The CS49300 device is targeted at audio decoding in the DVD via ES or PES in a serial or parallel bursty fashion for MLP or for DVD Audio Pack Layer Support. (All the other decoding/processing algorithms listed below require delivery of PCM or IEC61937- packed compressed data via I 2S or LJ formatted digital audio to the CS49300). Specifically the CS49300 will support all of the following decoding/processing standards:  Meridian Lossless Packing ™ (MLP™ )* (for ES and PES data delivery only)  DVD Audio Pack Layer Support* (for ES and PES data delivery only)  Dolby Digital ™ (AC-3™ ) with Dolby Pro Logic™  Dolby Digital ™ with Dolby Pro Logic ™ plus Cirrus Extra Surround™  Dolby Digital ™ with Dolby Pro Logic II™  Dolby Digital ™ with Dolby Pro Logic II™ plus Cirrus Extra Surround™  Virtual Dolby Digital ™  MPEG-2, Advanced Audio Coding Algorithm (AAC)  MPEG Multichannel  MPEG Multichannel with Dolby Pro Logic II  MPEG Multichannel plus Cirrus Extra Surround™  MPEG-1, Layer 3 (MP3)  DTS Digital Surround ™  DTS Digital Surround ™ with Dolby Pro Logic II™  DTS Digital Surround ™ plus Cirrus Extra Surround™  DTS-ES Extended Surround ™ (DTS-ES Discrete 6.1 & Matrix 6.1)  DTS Neo:6 ™  LOGIC5 ® (5.1 Channel, Max Fs=48kHz and LOGIC7® (7.1 Channel, Max Fs=96kHz)  VMAx VirtualTheater ® (Virtual Dolby Digital)  SRS TruSurround ™ (Virtual Dolby Digital and DTS Virtual 5.1™ Versions)  SRS Circle Surround ™ I/II  HDCD ®  Cirrus P.D.F. (Dolby Pro Logic 2Fs Decoder and PCM Upsampler)  Cirrus PL2_2FS (Dolby Pro Logic II 2Fs Decoder and PCM Upsampler) Please refer to the CS4932x/CS49330 Part Matrix vs. Code Matrix (PDF) document available from the CS49300 Web Site Page for the latest listing of audio decoding/processing algorithms. The part

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will also support PES layer decode for audio/video synchronization and DVD Audio Pack layer support. The CS49300 will support all of the above decoding and PCM processing standards. CS4931X - Broadcast Sub-family . The CS4931X sub-family is targeted at audio decoding in the broadcast markets in systems such as digital TV, HDTV, set-top boxes and di gital audio broadcast units (digital radios). Specifically the CS4931X sub-family will support the following decode standards:  Dolby Digital ™ (AC-3 ™ ) with Dolby Pro Logic™  MPEG-2, Advanced Audio Coding Algorithm (AAC)  MPEG-1, Layers 1, 2 Stereo  MPEG-1, Layers 3 (MP3) Stereo  MPEG-2, Layer 2 Stereo  MPEG-2, Layer 3 (MP3) Stereo The part will also support PES layer decode for audio/video synchronization. The CS49310 will support all of the above decode standards while other parts in the CS4931X sub-family will decode subsets of the above audio decoding standards. CS4932X - Audio/Video Receiver (AVR) Sub- family. The CS4932X sub-family is targeted at audio decoding in the audio/video receiver markets. Typical applications will include amplifiers with integrated decoding capability, outboard decoder pre-amplifiers, car radios and any system where the compressed audio is received in an IEC61937 format. Specifically the CS4932X sub-family will support the following decode standards:  Dolby Digital ™ (AC-3™ ) with Dolby Pro Logic™  Dolby Digital ™ with Dolby Pro Logic ™ plus Cirrus Extra Surround™  Dolby Digital ™ with Dolby Pro Logic II™  Dolby Digital ™ with Dolby Pro Logic II™ plus Cirrus Extra Surround™  Virtual Dolby Digital ™  MPEG-2, Advanced Audio Coding Algorithm (AAC)  MPEG Multichannel  MPEG Multichannel with Dolby Pro Logic II  MPEG Multichannel plus Cirrus Extra Surround™  MPEG-1, Layer 3 (MP3)  DTS Digital Surround ™  DTS Digital Surround ™ with Dolby Pro Logic II™  DTS Digital Surround ™ plus Cirrus Extra Surround™  DTS-ES Extended Surround ™ (DTS-ES Discrete 6.1 & Matrix 6.1)  DTS Neo:6 ™  LOGIC5 ® (5.1 Channel, Max Fs=48kHz and LOGIC7® (7.1 Channel, Max Fs=96kHz)  VMAx VirtualTheater ® (Virtual Dolby Digital)  SRS TruSurround ™ (Virtual Dolby Digital and DTS Virtual 5.1™ Versions)  SRS Circle Surround ™ I/II  HDCD ®  Cirrus P.D.F. (Dolby Pro Logic 2Fs Decoder and PCM Upsampler)  Cirrus PL2_2FS (Dolby Pro Logic II 2Fs Decoder and PCM Upsampler) The CS49326 will support all of the above decode standards while other parts in the CS4932X sub- family will decode subs ets of the above audio decoding standards. Except for the CS49329 which offers AAC support this subfamily will offer integrated ROM support for the AC-3 code, DTS code, Cirrus Original Surround code and DTS tables. The CS49329 will

require an external download for all applications but will still support the DTS tables on chip. CS49330 - General Purpose, Car Audio Processor, PCM Effects & Multichannel Post- Processing Device . The CS49330 sub-family is targeted at any system that may require post processing or multichanne l effects processing, a general purpose MPEG Stereo, MPEG Multichannel, MP3, decoder or PCM effects processor or mixer, or for car audio applications. Typical applications will include multichannel amplifiers, outboard pre-amplifiers, HDTVs and car radios. Specifically the CS49330 sub-family will support the following:  Cirrus Digital Post-Processor, Home THX Cinema ® and THX Surround EX™ 5.1 and 7.1 Channel Post-Processors  Any general purpose application which only requires MPEG Multichannel; MPEG-1, Layer 3; MPEG-2, Layer 3*, or C.O.S. PCM Effects Processor. (MPEG-1, Layer 3 and MPEG-2, Layer 3 are only available for applications where serial or parallel bursty elementary stream data is available. MPEG-1, Layer 3 audio decoding is only available for IEC61937- packed MP3 data.)  Multichannel Effects Processing  General purpose broadcast application that only requires MPEG-1 Stereo (Layers 1, 2, or 3) and MPEG-2 Stereo (Layers 2 or 3)  Car Audio Post-Processor This sub-family will continue to grow as more post processing algorithms are supported. This data sheet covers the CS49300, CS4931X, CS4932X and CS49330 sub-families and devices. These parts are identical from an external electrical perspective. Internally, each part has been tailored for supporting different decoding standards. For this document individual part numbers have been replaced by CS493XX if the description applies to the entire CS49300 Family DSP. If a description only applies to a par ticular sub-family, CS49300, CS4931X, CS4932X or CS49330 will be used. When CS49300, CS4931X, CS4932X or CS49330 is used, this should be interpreted as applying to all parts within the particular sub-family or a particular device.

24 DS339PP4

1. TYPICAL CONNECTION DIAGRAMS Six typical connection diagrams have been presented to illustrate using the part with the different communication modes available. They are as follows: Figure 13, "I 2C® Control" on page 26 Figure 14, "I2C® Control with External Memory" on page 27 Figure 15, "SPI Control" on page 28 Figure 16, "SPI Control with External Memory" on page 29 Figure 17, "Intel ® Parallel Control Mode" on page Figure 18, "Motorola ® Parallel Control Mode" on page 31 The following should be noted when viewing the typical connection diagrams: The pins are grouped functionally in each of the typical connection diagrams. Please be aware that the CS493XX symbol may appear differently in each diagram. The external memory interface is only supported when a serial communication mode has been chosen. The typical connection diagrams demonstrate the PLL being used (CLKSEL is pulled low). To use CLKIN as the DSP clock, CLKSEL should be pulled high. The system designer must be aware that certain software features may not be available if external CLKIN is us ed as the DSP must run slower when external CLKIN is used. The system designer should also be aware of additional duty cycle requirements when using external CLKIN as a DSP clock. It is highly suggested that the system designer use the PLL and pull CLKSEL low. 3.1. Multiplexed Pins The CS493XX family of digital signal processors (DSPs) incorporate a large amount of flexibility into a 44 pin package. Because of the high degree of integration, many of these pins are internally multiplexed to serve multiple purposes. Some pins are designed to operate in one mode at power up, and serve a different purpose when the DSP is running. Other pins have functionality which can be controlled by the application running on the DSP. In order to better explain the behavior of the part, the pins which are multiplexed have been given multiple names. Each name is specific to the pin’s operation in a particular mode. An example of this would be the use of pin 20 in one of the serial control modes. During the boot period of the CS493XX, pin 20 is called ABOOT ABOOT is sampled on the rising edge of RESET . If ABOOT is high the host must download code to the DSP. If ABOOT is low when sampled, the CS493XX goes into autoboot mode and loads itself with code by generating addresses and reading data on EMAD[7:0]. When the part has been loaded with code and is running an application, however, pin 20 is called INTREQ . INTREQ is an open drain output used to inform the host that the DSP has an outgoing message which should be read. In this document, pins will be referred to by their functionality. Section 12, “Pin Descriptions” on page 80 describes each pin of the CS493XX and lists all of its names. Please refer to this section when exact pin numbers are in question. The part has 12 general purpose input and output (GPIO[11:0]) pins that all have multiple functionality. While in one of the parallel communication modes (Section 6.2, “Parallel Host Communication” on page 41), these pins are used to implement the parallel host communication interface. While in one of the serial host modes these pins are used to implement an external memory interface. Alternatively while in one of the serial host modes these pins could be used for another general purpose if the application code has been programmed to support the special purpose. In this document the pins are referenced by the

name corresponding to their particular use. used when referring to the pins in a general sense. will be prone to oscillation if they are left floating. mode please see the typical connection diagrams. the GPIO pins and unused inputs. which could affect performance. 2.5V analog power supply for the internal PLL. ensure reliable performance. between the power and ground of the CS493XX. closest to the part (typically 5mm or closer). Table 1. PLL Filter Component Values

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NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. Figure 13. I2C® Control

NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. Figure 14. I2C® Control with External Memory

28 DS339PP4

NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. Figure 15. SPI Control

NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. Figure 16. SPI Control with External Memory

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NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. Figure 17. Intel® Parallel Control Mode

NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. Figure 18. Motorola® Parallel Control Mode

32 DS339PP4

communication or data integrity problems. the inputs without damaging the part. CLKIN requirements when bypassing the PLL. the DSP: SCLKN2, SCLKN1, and CLKIN.

12.288 MHz CLKIN is used in this scenario so that

and Intel byte wide parallel host control mode. to determine the interface type as shown in Table 2. application software running on the DSP.

01 X Serial I2C®

Table 2. Host Modes

diagrams will illustrate read and write cycles. of these signals on the CS493XX. write sequence with the CS493XX. clocked into the device preceding any write. Table 3. SPI Communication Signals Figure 19. SPI Write Flow Diagram

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hardware protocol is followed. read sequence with the CS493XX. significant bit set to 1 to designate a read. transitions occur on the falling edge of SCCLK. Figure 20. SPI Read Flow Diagram

second to last bit of the last byte to be transferred. continue reading data from the serial control port. lines for an SPI read and write. signal that the DSP has data to transmit to the host. number of each of these signals on the CS493XX. write sequence with the CS493XX. low for a write should be sent to the CS493XX. read/write bit set to 0 to designate a write. Table 4. I2C® Communication Signals

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Figure 21. SPI Timing to be transferred out of the CS493XX.

1. INTREQ is guaranteed to remain HIGH until the next rising edge of SCCLK at which point it

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sequence should be restarted. rising edge of SCCLK for the ACK/NACK bit). continue reading data from the serial control port. Figure 23. I2C® Read Flow Diagram

The timing diagram in Figure 24, "I2C® Timing" on page 40 shows the relative edges of the control lines for an I2C® read and write. 6.1.3. INTREQ Behavior: A Special Case When communicating with the CS493XX there are two types of messages which force INTREQ to go low. These messages are known as solicited messages and unsolicited messages. For more information on the specific types of messages that require a read from the host, one of the application code user’s guides should be referenced. In general, when communicating with the CS493XX, INTREQ will not go low unless the host first sends a read request command message. In other words the host must solicit a response from the DSP. In this environment, the host must read from the CS493XX until INTREQ goes high again. Once the INTREQ pin has gone high it will not be driven low until the host sends another read request. When unsolicited messages, such as those used for Autodetect, have been enabled, the behavior of INTREQ is noticeably different. The CS493XX will drop the INTREQ pin whenever the DSP has an outgoing message, even though the host may not have requested data. There are three ways in which INTREQ can be affected by an unsolicited message: 1) During normal operation, while INTREQ is high, the DSP could drop INTREQ to indicate an outgoing message, without a prior read request. 2) The host is in the process of reading from the CS493XX, meaning that INTREQ is already low. An unsolicited message arrives which forces INTREQ to remain low after the solicited message is read. 3) The host is reading from the CS493XX when the unsolicited message is queued, but INTREQ goes high for one period of SCCLK and then goes low again before the end of the read cycle. In case (1) the host should perform a read operation as discussed in the previous sections. In case (2) an unsolicit ed message arrives before the second to last SCCLK of the final byte transfer of a read, forcing the INTREQ pin to remain low. In this scenario the host should continue to read from the CS493XX without a stop/start condition or data will be lost. In case (3) an unsolicited message arrives between the second to last SCCLK and the last SCCLK of the final byte transfer of a read. In this scenario, INTREQ will transition high for one clock (as if the read transaction has ended), and then back low (indicating that more data has queued). This final case is the most complicated and shall be explained in detail. There are two constraints which completely characterize the behavior of the INTREQ pin during a read. The first constraint is that the INTREQ pin is guaranteed to remain low until the second to last SCCLK (SCCLK number N-1) of the final byte being transferred from the CS493XX (not necessarily the second to last bit of the data byte). The second constraint is that once the INTREQ pin has gone high it is guaranteed to remain high until the rising edge of the last SCCLK (SCCLK number N) of the final byte being transferred from the CS493XX (not necessarily the last bit of the data byte). If an unsolicited message arrives in the window of time between the rising edge of the second to last SCCLK and the final SCCLK, INTREQ will drop low on the rising edge of the final SCCLK as illustrated in the functional timing diagrams shown for I 2C® and SPI read cycles. INTREQ behavior for I 2C® communication is illustrated in Figure 24, "I2C® Timing" on page 40. When using I2C® communication the INTREQ pin will remain low until the rising edge of SCCLK

40 DS339PP4

Notes: 1. The ACK for the address byte is driven by the CS493XX.

1. The ACKs for the data bytes being read from the CS493XX should be driven by the host.
2. INTREQ is guaranteed to stay LOW until the rising edge of SCCLK for bit D0 of the last byte

to be transferred out of the CS493XX.

1. A NACK should be sent by the host after the last byte to indicate the end of the read cycle.

condition, a new start condition followed by an address byte should be sent. Figure 24. I2C® Timing

for the data bit D0 (SCCLK N-1), but it can go low at the rising edge of SCCLK for the NACK bit (SCCLK N) if an unsolicited message has arrived. If no unsolicited messages arrive, the INTREQ pin will remain high after rising. INTREQ behavior for SPI communication is illustrated in Figure 21, "SPI Timing" on page 36 . When using SPI communication, the INTREQ pin will remain low until the rising edge of SCCLK for the data bit D1 (SCCLK N-1), but it can go low at the rising edge of SCCLK for data bit D0 (SCCLK N) if an unsolicited message has arrived. If no unsolicited messages arrive, the INTREQ pin will remain high after rising. Ideally, the host will sample INTREQ on the falling edge of SCCLK number N-1 of the final byte of each read response message. If INTREQ is sampled high, the host should conclude the current read cycle using the stop condition defined for the communication mode chosen. The host should then begin a new read cycle complete with the appropriate start condition and the chip address. If INTREQ is sampled low, the host should continue reading the next message from the CS493XX without ending the current read cycle. When using automated communication ports, however, the host is often limited to sampling the status of INTREQ after an entire byte has been transferred. In this situation a low-high-low transition (case 3) would be missed and the host will see a constantly low INTREQ pin. Since the host should read from the CS493XX until it detects that INTREQ has gone high, this condition will be treated as a multiple-message read (more than one read response is provided by the CS493XX). Under these conditions a single byte of 0x00 will be read out before the unsolicited message. The length of every read response is defined in the user’s manual for each piece of application code. Thus, the host should know how many bytes to expect based on the first byte (the OPCODE) of a read response message. It is guaranteed that no read responses will begin with 0x00, which means that a NULL byte (0x00) detected in the OPCODE position of a read response message should be discarded. Please see an Application Code User’s Guide for an explanation of the OPCODE. It is important that the host be aware of the presence of NULL bytes, or the communication channel could become corrupted. When case (3) occurs and the host issues a stop condition before starting a new read cycle, the first byte of the unsolicited message is loaded directly into the shift register and 0x00 is never seen. Alternatively, if case (3) occurs and the host continues to read from the CS493XX without a stop condition (a multiple message read), the 0x00 byte must be shifted out of the CS493XX before the first byte of the unsolicited message can be read. In other words, if a system can only sample INTREQ after an entire byte transfer the following routine should be used if INTREQ is low after the last byte of the message being read: 1) Read one byte 2) If the byte = 0x00 discard it and skip to step 3. If the byte != 0x00 then it is the OPCODE for the next message. For this case skip to step 4. 3) Read one more byte. This is the OPCODE for the next message. 4) Read the rest of the message as indicated in the previous sections. 6.2. Parallel Host Communication The parallel host communication modes of the CS493XX provide an 8-bit interface to the DSP. An Intel-style parallel mode and a Motorola-style parallel mode are supported. The host interface is implemented using four communication registers within the CS493XX as shown in Table 5, “Parallel Input/Output Registers,” on page 42.

42 DS339PP4

independent registers for input and output (read and write). Reserved Always write a 0 for future compatibility. holds the port in reset. Writing zero enables the port. This bit must be low for normal operation. Reserved Always write a 0 for future compatibility. Table 5. Parallel Input/Output Registers

outgoing byte that may be read. directly to the internal FIFOs of the CS493XX. implemented using the pins given in Table 6. bit of the Host Control Register (A[1:0] = 01b). data type (e.g. PCM --> AC-3). Table 6. Intel Mode Communication Signals

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Intel Parallel Host Mode Write Cycle are met. will now be described in detail. of the desired Parallel I/O Register. Intel Parallel Host Mode Read Cycle are met. will now be described in detail. Control register can be read. DATA[7:0] pins of the CS493XX. Figure 24. Intel Mode, One-Byte Write Flow Diagram Figure 25. Intel Mode, One-Byte Read Flow Diagram

46 DS339PP4

Figure 27 will now be described in detail. Control register can be read. DATA[7:0] pins of the CS493XX. performed most significant byte first. Write_Byte_MOT() or Write_Byte_INT(). Motorola communication protocol. Figure 27. Motorola Mode, One-Byte Read Flow

48 DS339PP4

Message Register (A[1:0] = 00b). back to step 4 and read out the new message). shared pins that are needed by each mode. memory is not required for that application. pin number of each signal on the CS493XX. is an active low write enable. Figure 29. Typical Parallel Host Mode Control Read

functional timing of a 16 bit address memory write. the DSP visibility to up to 64 kilobytes of memory. data is read by the CS493XX. (see Figures 30, 31, and 32 for details). which corresponds to only 15 address lines. address cycles are illustrated. discussed in the next section. (discussed in Section 8.2, “Autoboot” on page 56). Table 8. Memory Interface Pins

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one application code image residing in each 32 kilobyte page. Paging of the external memory is handled entirely by the host controller. The host controller should directly control all address bits outside of the memory space to be used by the DSP. As 32 kilobyte pages are desired to hold each application code, the DSP would need 15 bits for the address space. The system designer would connect the 15 address signals from the address latches while the host would directly cont rol all address signals above 15 bits to page the memory accordingly.

8 BIT

Only one of R1 and R2 should be stuffed. Only one of R3 and R4 shou ld be stuffed. Figure 30. External Memory Interface Figure 31. External Memory Read (16-bit address) Figure 32. External Memory Write (16-bit address)

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autoboot and reset are covered in this section. download algorithm is the same. parallel mode you must check HOUTRDY. be used in the boot sequence. “Hardware Configuration” on page 72. the decoder is in a wait state. download sequence for the CS493XX. Table 9. Boot Write Messages Table 10. Boot Read Messages

Figure 33. Typical Serial Boot and Download Procedure

1. It should be noted that mode

statically pulled HIGH or LOW.

1. Time-out values reflect worst
2. 5 ms is typical but this time is

Section 6, “Control” on page 32. application code user’s manual.

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Figure 34. Typical Parallel Boot and Download Procedure

1. It should be noted that mode
2. Time-out values reflect worst
3. 5 ms is typical but this time is

Section 6, “Control” on page 32. application code user’s manual.

CS493XX sends out the boot message BOOT_START (0x01) and the host should proceed to step 5. 4) If initialization fails, the CS493XX sends out an INIT_FAILURE boot message byte (0xFD or 0xFE), INVALID_MSG byte (0xFB), or BOOT_ERROR byte (0xFA or 0xFC) and spins waiting for a hard reset. The host should re-try steps 1 through 3 and if failure is met again, the serial communication timing and protocol should be inspected. 5) After receiving the BOOT_START byte, the host should write the downloadable image (from the .LD file). 6) The end of the .LD file contains a three byte checksum. If the checksum is good after download, the CS493XX will send a BOOT_SUCCESS message (0x02) to the host. If the checksum was bad, the CS493XX responds with the BAD_CHECKSUM message byte (0xFF) and spins, waiting for hard reset. 7) After reading out the BOOT_SUCCESS byte, the host should send the BOOT_SUCCESS_RECEIVED message (0x000005) which will cause an internal application code re set and allow the downloaded application to run. 8) After waiting 5ms to allow the downloaded application to initialize, the host can send configuration messages for both hardware and software configuration. 8.1.2. Parallel Download Sequence The following is a detailed description of a parallel download sequence for the CS493XX. Note: When reading from the chip in a parallel communication mode, the host must read the HOSTCTL register and test the HOUTRDY bit before starting the read cycle. 1) A download sequence is started when the host issues a hard reset and holds the mode pins appropriately (WR, RD, and PSEL). 2) The host should then send the boot message DOWNLOAD_BOOT (0x000004). This causes the CS493XX to initialize itself for download. 3) If the initialization was successful the CS493XX sends out the boot message BOOT_START (0x01) and the host should proceed to step 5. 4) If initialization fails, the CS493XX sends out an INIT_FAILURE boot message byte (0xFD or 0xFE), INVALID_MSG byte (0xFB), or BOOT_ERROR byte (0xFA or 0xFC) and spins waiting for a hard reset. The host should re-try steps 1 through 3 and if failure is met again, the serial communication timing and protocol should be inspected. 5) After receiving the BOOT_START byte, the host should write the downloadable image (from the .LD file). 6) The end of the .LD file contains a three byte checksum. If the checksum is good after download, the CS493XX will send a BOOT_SUCCESS message (0x02) to the host. If the checksum was bad, the CS493XX responds with the BAD_CHECKSUM message byte (0xFF) a nd spins, waiting for hard reset. 7) After reading out the BOOT_SUCCESS byte, the host should send the BOOT_SUCCESS_RECEIVED message (0x000005) which will cause an internal application code reset and allow the downloaded application to run. 8) After waiting 5ms to allow the downloaded application to initialize, the host can send configuration messages for both hardware and software configuration.

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is used to enable the ROM outputs. await the data coming from the ROM. Figure 35. Autoboot Timing Diagram

bytes represent a true 24-bit address). “Hardware Configuration” on page 72. described in the user’s guide for each application. are multiplexed on pin 20 of the CS493XX. low around the rising edge of RESET. Figure 37. Autoboot INTREQ Behavior

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Figure 36. Autoboot Sequence Notes: 1. RESET must be held LOWTrstl.

1. The RD and WR pins must be configured to select a
2. INTREQ should be ignored during this period. 200 ms
3. The READ_* and WRITE_* functions are

6.1, “Serial Communication” on page 33.

longer to initialize all of the internal state variables. required for each application code in their system. Autoboot itself from external ROM. FAE in order to obtain these gfabt codes. (200/3) with gfabt8, 6, and 4, respectively.

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Figure 38. Fast Autoboot Sequence Using GFABT Codes Notes: 1. RESET must be held LOWTrstl.

1. It should be noted that mode pins are used

latched internally on the rising edge of reset.

1. Time-out values reflect worst case response
2. Hardware configuration messages are

covered in Section 6, “Control” on page 32.

1. The READ_* and WRITE_* functions are

8.3.1. Design Considerations when using GFABT Codes The designer should be aware that the gfabt codes do not lock the PLL, so therefore the actual time in- volved with autobooting is subject to the open loop VCO frequency. The PLL is only locked when the command is sent from the host, typically along with the kickstart command. Also, the designer should take into account the access time of the Flash Memory, EPROM, and latches used in their specific design. While there is a temptation to use the gfabt4 code which would theoretically mini- mize the Autoboot time, the designer should realize that this may result in the DSP to attempting to Au- toboot too quickly, resulting in clocking times that exceed that of the specified access times of partic- ular external memory devices or the associated latches. The designer should note that the times listed in Table 11 were taken from 3 sample CS493264-CL Rev. G devices and are in no way a guarantee of the times that your design will achieve as all values are dependent on the open loop frequency of the DSP. Furthermore the times listed in Table 11 DO NOT include the code initialization time (the time spent after download while the code prepares for messages). Therefore, the times listed above should be used as the upper bound on boot time when using the gfabt codes. 8.4. Internal Boot Certain applications are stored in the ROM of the CS493253, CS493254, CS493263 and CS493264. To enable these applications a special loader called an internal boot assist program must be used. This internal boot assist (or IBA) code can be downloaded using either host boot or autoboot methods. After the IBA program has been downloaded, it enables the internally stored application code. The IBA codes are typically around 350 bytes in size and hence can easily be stored in a host controller. 8.5. Application Failure Boot Message Each piece of applicati on code is specifically tailored for an individual part in the CS493XX family. Although it is possible to load a piece of code into the wrong chip and receive a BOOT_SUCCESS byte, the code will not initialize itself. In order to faci litate the debug of designs which can accept many members of the CS493XX family, an APPLICATION_FAILURE message is provided. As mentioned earlier, the host must wait for at least 5ms after download before sending configuration messages to the CS493XX. This provides time for the code to initialize itself. If the INTREQ pin is low after the download process has completed, the host should read from the CS493XX. The byte 0xF0 indicates APPLICATION_FAILURE. This byte informs the host that the application code was loaded into an incompatible DSP. Although most of the messages listed in Tables 9 and 10 are essentially ignored for autoboot, it should be noted that the APPLICATION_FAILURE message is applicable whether host boot or autoboot is used. 8.6. Resetting the CS493XX Resetting the CS493XX uses a combination of software and hardware. To reset the device, a previous application must have been downloaded. The flow diagram in Figure 39, "Performing a Reset" on page 62 shows the procedure for performing a reset. The following is a detailed description of a reset sequence to the CS493XX. All writes and reads with the CS493XX should follow the protocol given in Section 6, “Control” on page 32. 1) Reset begins when the host issues a hard reset and holds the mode pi ns appropriately (WR RD, and PSEL) as described in Section 6, “Control” on page 32 . It is assumed that the communication protocol is followed for

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are affected by a SOFT_RESET. Figure 39. Performing a Reset Notes: 1. RESET must be held LOW for trstl.

1. It should be noted that mode pins are used to configure
2. 5 ms is typical but this time is application code specific
3. Configuration messages determine both hardware and

128 Kbytes

256 Kbytes

8 N/A, No IBA

Table 12. Memory Requirements for Example 5.1, 6.1 and 7.1 Channel Systems

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responsible for all communication with the ROM. IBA application codes in each 32 Kilobyte page. channel system describe in Table 12 above. containing first code by driving uC15 to a low state. multiplexed on the same pin). should be inserted and the read should be repeated. Figure 40. Non-Paged Memory Figure 41. Example Contents of a Paged 32 Kilobytes

about how to control the GPIO pins of the DSP via messaging to the SPI or I2C port. 8.8. CDB49300-MEMA.0 The CDB49300-MEMA.0 is an external memory adapter card designed for use with the CDB4923/CDB4930 REV-A.0 Evaluation Board. The schematic for the CDB49300-MEMA.0 is shown in Figure 42. This board is an example of one possible external memory configuration. In addition to autobooting from external EPROM, certain application codes require real-time access to external SRAM, such as decoding of AAC Multichannel streams, which have a 5.1 channel output. These applications require that the DSP has real-time access to 70nS (or faster) 32 Kilobyte SRAM. The 128 Kilobyte SRAM on the CDB49300-MEMA.0 is made accessible by the DSP when the host drives uC18 high. The external

256 Kilobyte EPROM is accessible to the DSP

when the host controller drives uC18 low. The with uC15, uC16, and uC17 lines are used to page between the various code images.

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Figure 42. CDB49300-MEMA.0 Daughter Card for the CDB4923/30-REV-A.0

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the example SCLK must be greater than M * 6. SCLK Rate) not all modes have been presented. both compressed and PCM digital audio data input. Figure 43. I2S Format Figure 44. Left Justified Format (Rising Edge Valid SCLK) Figure 45. Multichannel Format Table 13. Digital Audio Input Port

audio/video synchronization purposes. used for both compressed and PCM data input. as a continuous stream with no word boundaries. deliver data through the byte wide parallel port. writes to address 11b (A1 and A0 are both high). of using either CMPREQ or the MFB bit. another block of compressed audio data. Table 14. Compressed Data Input Port

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FIFO threshold has been reached. until the block transfer is complete. on the transition of CMPCLK. configurable via hardware configuration. Table 15. Digital Audio Output Port

clock, where Fs is the output sample rate. the sampling frequency, Fs). AUDATA3 can both output two channels of data. left justified, I2S or right justified modes. Surround, Right Surround and Subwoofer). AUDATA1 and AUDATA2 to support 7.1 output. actual outputs when not in a multichannel mode. application code being used.

128 X X

Table 16. MCLK/SCLK Master Mode Ratios

0 Left AUDATA0

1 Right AUDATA0

2 Left AUDATA1

3 Right AUDATA1

4 Left AUDATA2

5 Right AUDATA2

6 Left AUDATA3

7 Right AUDATA3

Table 17. Output Channel Mapping

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1. HARDWARE CONFIGURATION After download or soft reset, and before kickstarting the applicati on (please see the Audio Manager in the Applicat ion Messaging Section of any application code user’s guide for more information on kickstarting), the host has the option of changing the default hardware configuration. Hardware configuration messages are used to physically reconfigure the hardware of the audio decoder, as in enabling or disabling address checking for the serial communication port. Hardware configuration messages are also used to initialize the data type (i.e., PCM or compressed) and format (e.g., I 2S, Left Justified, Parallel, or Serial Bursty) for digital data inputs, as well as the data format and clocking options for the digital output port. In general, the hardware configuration can only be changed immediately after download or after soft reset. However, some a pplications provide the capability to change the input ports without affecting other hardware configurations after sending a special Application Restart message (please see the Audio Manager in any Application Code User’s Guide to determine whether the Application Restart message is supported). Serial digital audio data bit placement and sample alignment is fully configurable in the CS493XX including left justified, right justified, delay bits or no delay bits, variable sample word sizes, variable output channel count, and programmable output channel pin assignments and clock edge polarity to integrate with most digital audio interfaces. If a mode is needed which is not presented, please consult your sales representative as to its availability. 11.1. Address Checking When using one of the serial communication modes, I 2C or SPI, as discussed in Section 6.1, “Serial Communication” on page 33, it is necessary to send a 7-bit address along with a read/write bit at the start of any serial transaction. By default, address checking is disabled in the CS493XX. See below for how to enable address checking. The following 4-word hex message configures the address checking circuitry of the CS493XX: It should be noted that this will allow the host to enable address checking and change the address of the device. If address checking disabled is acceptable, then these messages do not need to be sent. 0x800252 0x00FFFF 0x800152 0xHH0000 In the last word the following bits should replace HH: Bits 23:17 - New Address to use for checking (if enabling address checking) Bit 16 - 1 = Address checking on 0 = Address checking off 11.2. Input Data Hardware Configuration Both data format (I 2S, Left Justified, Parallel, or Serial Bursty) and data type (compressed or PCM) are required to fully define the input port’s hardware configuration. The DAI and the CDI are configured by the same group of messages since their configurations are interrelated. The naming convention of the input hardware configuration is as follows: INPUT A B C D where A, B, C and D are the parameters used to fully define the input port. The parameters are defined as follows: A - Data Type B - Data Format (This is a don’t care for parallel modes of data delivery)

as unused by the A parameter.

1 DAI - PCM and Compressed

2 DAI - Unused

4 DAI - Multichannel PCM

6 DAI - PCM

Table 18. Input Data Type Configuration

8 DAI - Not Used

10 DAI - Not Used

Table 19. Input Data Format Configuration

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1 PCM - Left Justified 24-bit

2 PCM - I2S 24-bit

22 PCM - I

24 PCM - I2S 24-bit

3 PCM - Left Justified 24-bit

32 PCM - Left Justified 24-bit

34 PCM - Left Justified 24-bit

7 PCM - I2S 24-bit

72 PCM - I2S 24-bit

74 PCM - I

8 PCM - Left Justified 24-bit

82 PCM - Left Justified 24-bit

84 PCM - Left Justified 24-bit

1 Data Clocked in on Falling

Table 20. Input SCLK Polarity Configuration

1 Compressed FIFO B Size -

2 PCM FIFO C Size - 6kbyte

Table 21. Input FIFO Setup Configuration

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should be sent per parameter.

2 MCLK - Master

Table 22. Output Clock Configuration

1 Left Justified 24-bit

2 Multichannel (6 channel)

Table 23. Output Data Format Configuration

22 Multichannel (2 channel)

24 Multichannel (4 channel)

3 Multichannel (6 channel)

32 Multichannel (2 channel)

34 Multichannel (4 channel)

Table 24. Output MCLK Configuration Table 25. Output SCLK Configuration

1 Data Valid on Falling Edge

Table 26. Output SCLK Polarity Configuration

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11.3.1. Output Configuration Considerations 1) All PCM output is 24-bit resolution 2) An SCLK frequency of at least 128Fs must be selected for the 20-bit multichannel (6 channel) mode. 3) An SCLK frequency of at least 128Fs must be selected for the 24-bit multichannel (4 channel) mode. 4) An SCLK frequency of at least 256Fs must be selected for the 24-bit multichannel (6 channel) mode. 5) If the clocks to the audio ports are known to be corrupted, such as when a S/PDIF receiver goes out of lock, the DSP should undergo an application restart (if a pplicable), soft reset or hard reset. All three actions will result in the input FIFO being reset. Failure to do so may result in corrupted data being latched into the input FIFO and may result in corrupted data being heard on the outputs. This is not an issue when compressed data is being delivered, as it has sync words embedded in the stream which the DSP can lock to, but only when PCM data is being delivered. Cert ain application codes that are capable of processing PCM may now have a special feature called “PCM Robustness” which does alleviate the above problem, however you should still follow the above recommendation. 11.4. Creating Hardware Configuration Messages The single hardware configuration message that must be sent to the CS493XX after download or soft reset should be a concatenation of the messages in the previous sections. The complete hardware configuration message should be created by taking a message for each parameter (where the default is not acceptable) and concatenating the messages together. No messages need to be sent if the default configuration for a particular parameter is acceptable. This example can be easily expanded to fit other system requirements. For example if the host system has the following configuration: Address Checking: Disabled The above configuration is default so no configuration message is required. DAI: Left Justified PCM and Compressed data CDI: Not used The above configuration corresponds to INPUT A1 B1 which corresponds to a configuration message of: 0x800210 0x3FBFC0 0x800110 0xC0002C 0x800217 0x8080FF 0x80021A 0x8080FF 0x800117 0x001000 0x80011A 0x001800 DAO: Left Justified slave mode (LRCLK, SCLK inputs) MCLK @ 256Fs SCLK @ 64Fs The above configuration corresponds to OUTPUT A0 B1 C0 D0 which has a configuration message of: 0x80027F 0xFC7FFF 0x80027C 0xF01F00 0x80027D 0xF01F00

Table 27. Example Values to be Sent to CS493XX After

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1. PIN DESCRIPTIONS V A—Analog Positive Supply: Pin 34 Analog positive supply for clock generator. Nominally +2.5 V . AGND—Analog Supply Ground: Pin 35 Analog ground for clock generator PLL. VD1, VD2, VD3—Digital Positive Supply: Pins 1, 12, 23 Digital positive supplies. Nominally +2.5 V . DGND1, DGND2, DGND3—Digital Supply Ground: Pins 2, 13, 24 Digital ground. FILT1—Phase-Locked Loop Filter: Pin 33 Connects to an external filter for the on-chip phase-locked loop. FILT2—Phase Locked Loop Filter: Pin 32 Connects to an external filter for the on-chip phase-locked loop. CLKIN—Master Clock Input: Pin 30 CS493XX clock input. When in internal clock mode (CLKSEL == DGND), this input is connected to the internal PLL from which all internal clocks are derived. When in external clock mode (CLKSEL == VD), this input is connected to the DSP clock. INPUT 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 4 44 34 24 14 0 CS493XX-CL 44-pin PLCC Top View VD2 DATA4,EMAD4,GPIO4 VA DATA5,EMAD5,GPIO5 DATA6,EMAD6,GPIO6 DATA7,EMAD7,GPIO7 A0, SCCLK A1, SCDIN RD,R/W,EMOE,GPIO11 WR,DS,EMWR,GPIO10 AUDATA3, XMT958 DGND1 VD1 SDATAN1 EXTMEM, GPIO8 ABOOT, INTREQ SCDIO, SCDOUT,PSEL,GPIO9 CS DATA0,EMAD0,GPIO0 DATA1,EMAD1,GPIO1 DATA2,EMAD2,GPIO2 DATA3,EMAD3,GPIO3 DGND2 RESET DD DC AUDATA2 AUDATA1 AUDATA0 LRCLK SCLK MCLK VD3 DGND3 SCLKN1, STCCLK2 LRCLKN1 CMPDAT, SDATAN2, RCV958 CMPCLK, SCLKN2 CMPREQ, LRCLKN2 CLKIN CLKSEL FILT2 FILT1 AGND

CLKSEL—DSP Clock Select: Pin 31 This pin selects the clock mode of the CS493 XX. When CLKSEL is low, CLKIN is connected to the internal PLL from which all internal clocks are derived. When CLKSEL is high CLKIN is connected to the DSP clock. INPUT DATA7, EMAD7, GPIO7—Pin 8 DATA6, EMAD6, GPIO6—Pin 9 DATA5, EMAD5, GPIO5—Pin 10 DATA4, EMAD4, GPIO4—Pin 11 DATA3, EMAD3, GPIO3—Pin 14 DATA2, EMAD2, GPIO2—Pin 15 DATA1, EMAD1, GPIO1—Pin 16 DATA0, EMAD0, GPIO0—Pin 17 In parallel host mode, these pins provide a bi directional data bus. If a serial host mode is selected, these pins can provide a multiplexed address and data bus for connecting an 8-bit external memory. Otherwise, in serial host m ode, these pins can act as general-purpose input or output pins that can be individually configured and controlled by the DSP. BIDIRECTIONAL - Default: INPUT A0, SCCLK—Host Parallel Address Bit Zero or Serial Control Port Clock: Pin 7 In parallel host mode, this pin serves as one of tw o address input pins used to select one of four parallel registers. In serial host mode, this pin serves as the serial control clock signal, specifically as the SPI clock input or the I 2C clock input. INPUT A1, SCDIN—Host Address Bit One or SPI Serial Control Data Input: Pin 6 In parallel host mode, this pin serves as one of tw o address input pins used to select one of four parallel registers. In SPI serial host m ode, this pin serves as the data input. INPUT RD, R/W, EMOE, GPIO11—Host Parallel Output Enable or Host Parallel R/W or External Memory Output Enable or General Purpose Input & Output Number 11: Pin 5 In Intel parallel host mode, this pin serves as the active-low data bus enable input. In Motorola parallel host mode, this pin serves as the read-h igh/write-low control input signal. In serial host mode, this pin can serve as the external memory active-low data-enable output signal. Also in serial host mode, this pin can serve as a general purpose input or output bit. BIDIRECTIONAL - Default: INPUT WR, DS, EMWR, GPIO10—Host Write Strobe or Host Data Strobe or External Memory Write Enable or General Purpose In put & Output Number 10: Pin 4 In Intel parallel host mode, this pin serves as the active-low data-write-input strobe. In Motorola parallel host mode, this pin serves as the active-low data-strobe-input signal. In serial host mode, this pin can serve as the extern al-memory active-low write-enable output signal. Also in serial host mode, this pin can serve as a general purpose input or output bit. BIDIRECTIONAL - Default: INPUT

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CS—Host Parallel Chip Select, Host Serial SPI Chip Select: Pin 18 In parallel host mode, this pin serves as the acti ve-low chip-select input signal. In serial host SPI mode, this pin is used as the active-low chip-select input signal. INPUT RESET—Master Reset Input: Pin 36 Asynchronous active-low master reset input. Reset should be low at power-up to initialize the CS493XX and to guarantee that the device is not active during initial power-on stabilization periods. At the rising edge of reset the host inte rface mode is selected c ontingent on the state of the RD , WR and PSEL pins. Additionally, an autoboot sequence can be initiated if a serial control mode is selected and ABOOT is held low. If reset is low all bidirectional pins are high impedance inputs. INPUT SCDIO, SCDOUT, PSEL, GPIO9—Serial Control Port Data Input and Output, Parallel Port Type Select: Pin 19 In I 2C mode, this pin serves as the open-drain bi directional data pin. In SPI mode this pin serves as the data output pin. In parallel host m ode, this pin is sampled at the rising edge of RESET to configure the parallel host mode as an Intel type bus or as a Motorola type bus. In parallel host mode, after the bus mode has been selected, the pin can function as a general- purpose input or output pin. BIDIRECTIONAL - Default: INPUT In I 2C mode this pin is an OPEN DRAIN I/O and requires a 4.7k Pull-Up EXTMEM, GPIO8—External Memory Chip Select or General Purpose Input & Output Number 8: Pin 21 In serial control port mode, this pin can serve as an output to provide the chip-select for an external byte-wide ROM. In parallel and serial host mode, this pin can also function as a general-purpose input or output pin. BIDIRECTIONAL - Default: INPUT INTREQ, ABOOT—Control Port Interrupt Request, Automatic Boot Enable: Pin 20 Open-drain interrupt-request output. This pin is driven low to indicate that the DSP has outgoing control data and should be serviced by th e host. Also in serial host mode, this signal initiates an automatic boot cycle from external me mory if it is held low through the rising edge of reset. OPEN DRAIN I/O - Requires 4.7k Ohm Pull-Up AUDATA2—Digital Audio Output 2: Pin 39 PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT AUDATA1—Digital Audio Output 1: Pin 40 PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT AUDATA0—Digital Audio Output 0: Pin 41 PCM multi-format digital-audio data output, cap able of two-, four-, or six-channel 20-bit output. This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT

MCLK—Audio Master Clock: Pin 44 Bidirectional master audio clock. MCLK can be an output from the CS493XX that provides an oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs. MCLK can be an input at 128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to derive SCLK and LRCLK when SCLK and LRCLK are driven by the CS493XX. BIDIRECTIONAL - Default: INPUT SCLK—Audio Output Bit Clock: Pin 43 Bidirectional digital-audio output bit clock. SCLK can be an output that is derived from MCLK to provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs, depending on the MCLK rate and the digital-output configuration. SCLK can also be an input and must be at least 48Fs or greater. As an input, SCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT LRCLK—Audio Output Sample Rate Clock: Pin 42 Bidirectional digital-audio output-sample-rate cl ock. LRCLK can be an output that is divided from MCLK to provide the output sample rate depending on the output configuration. LRCLK can also be an input. As an input LRCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT AUDATA3,XMT958—SPDIF Transmitter Output , Digital Audio Output 3: Pin 3 CMOS level output that contains a biphase-mark encoded (S/PDIF) or I 2S or Left Justified digital audio data which is capable of carrying two channels of PCM digital audio or an IEC61937 compressed-data interface. Note: Outputting of IEC61937 is only available for certain broadcast-based application codes which run on the CS4931X family or CS49330 device. This output typically connects to the input of an RS-422 transmitter or to the input of an optical transmitter. OUTPUT SCLKN1, STCCLK2—PCM Audio Input Bit Clock: Pin 25 Bidirectional digital-audio bit clock that is an output in master mode and an input in slave mode. In slave mode, SCLKN1 operates asynchronously from all other CS493XX clocks. In master mode, SCLKN1 is derived from the CS493XX internal clock generator. In either master or slave mode, the active edge of SCLKN1 can be programmed by the DSP. For applications supporting PES layer synchronization this pin can be used as STCCLK2, which provides a path to the internal STC 33 bit counter. BIDIRECTIONAL - Default: INPUT LRCLKN1—PCM Audio Input Sample Rate Clock: Pin 26 Bidirectional digital-audio frame clock that is an output in master mode and an input in slave mode. LRCLKN1 typically is run at the sampling frequency. In slave mode, LRCLKN1 operates asynchronously from all other CS493XX clocks. In master mode, LRCLKN1 is derived from the CS493XX internal clock genera tor. In either master or slave mode, the polarity of LRCLKN1 for a particular s ubframe can be programmed by the DSP. BIDIRECTIONAL - Default: INPUT

84 DS339PP4

SDATAN1—PCM Audio Data Input Number One: Pin 22 Digital-audio data input that can accept from one to six channels of compressed or PCM data. SDATAN1 can be sampled with either edge of SCLKN1, depending on how SCLKN1 has been configured. INPUT CMPCLK, SCLKN2—PCM Audio Input Bit Clock: Pin 28 Bidirectional digital-audio bit clock that is an output in master mode and an input in slave mode. In slave mode, SCLKN2 operates asynchronously from all other CS493XX clocks. In master mode, SCLKN2 is derived from the CS493XX internal clock generator. In either master or slave mode, the active edge of SCLKN2 can be programmed by the DSP. If the CDI is configured for bursty delivery, CMPCLK is an input used to sample CMPDAT. BIDIRECTIONAL - Default: INPUT CMPREQ, LRCLKN2—PCM Audio Input Sample Rate Clock: Pin 29 When the CDI is configured as a digital audio i nput, this pin serves as a bidirectional digital- audio frame clock that is an output in mast er mode and an input in slave mode. LRCLKN2 typically is run at the sampling frequency. In slave mode, LRCLKN2 operates asynchronously from all other CS493XX clocks. In master m ode, LRCLKN2 is derived from the CS493XX internal clock generator. In either master or slave mode, the polarity of LRCLKN2 for a particular subframe can be programmed by the DSP. When the CDI is configured for bursty delivery, or parallel audio data delivery is being used, CMPREQ is an output which serves as an internal FIFO monitor. CMPR EQ is an active low signal that indicates when another block of data can be accepted. BIDIRECTIONAL - Default: INPUT CMPDAT, SDATAN2—PCM Audio Data Input Number Two: Pin 27 Digital-audio data input that can accept from one to six channels of compressed or PCM data. SDATAN2 can be sampled with either edge of SCLKN2, depending on how SCLKN2 has been configured. Similarly CMPDAT is the compresse d data input pin when the CDI is configured for bursty delivery. When in this mode, the CS493XX internal PLL is driven by the clock recovered from the incoming data stream. INPUT DC—Reserved: Pin 38 This pin is reserved and should be pulled up with an external 4.7k resistor. DD—Reserved: Pin 37 This pin is reserved and should be pulled up with an external 4.7k resistor.

1. ORDERING INFORMATION CS493002-CL 44-Pin PLCC Temp Range 0-70º C CS493102-CL 44-Pin PLCC Temp Range 0-70º C CS493112-CL 44-Pin PLCC Temp Range 0-70º C CS493122-CL 44-Pin PLCC Temp Range 0-70º C CS493253-CL 44-Pin PLCC Temp Range 0-70º C CS493253-IL 44-Pin PLCC Temp Range -40-85º C CS493254-CL 44-Pin PLCC Temp Range 0-70º C CS493254-IL 44-Pin PLCC Temp Range -40-85º C CS493263-CL 44-Pin PLCC Temp Range 0-70º C CS493263-IL 44-Pin PLCC Temp Range -40-85º C CS493264-CL 44-Pin PLCC Temp Range 0-70º C CS493264-IL 44-Pin PLCC Temp Range -40-85º C CS493292-CL 44-Pin PLCC Temp Range 0-70º C CS493302-CL 44-Pin PLCC Temp Range 0-70º C CS493302-IL 44-Pin PLCC Temp Range -40-85º C 14. PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.165 0.180 4.191 4.572 A1 0.090 0.120 2.286 3.048 B 0.013 0.021 .330 0.533 D 0.685 0.695 17.399 17.653 D1 0.650 0.656 16.510 16.662 D2 0.590 0.630 14.986 16.002 E 0.685 0.695 17.399 17.653 E1 0.650 0.656 16.510 16.662 E2 0.590 0.630 14.986 16.002 e 0.040 0.060 .102 1.524 44L PLCC PACKAGE DRAWING D E1 E D2/E2 B e A