CS4927-CL

CS4923 CIRRUS | Alldatasheet

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Technical content

Preliminary Product InformationThis document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright ª Cirrus Logic, Inc. 1999 (All Rights Reserved)P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com CS4923/4/5/6/7/8/9 Multi-Channel Digital Audio Decoders lCS4923/4/5/6/7/8 features — Optional Virtual 3D Output — Simulated Surround and Programmable Effects — Real Time Autodetection of Dolby Digital ® , DTS ® , MPEG Multi-Channel and PCM — Flexible 6-channel master or slave output lCS4923/4/5/6/7/8/9 features — IEC60958/61937 transmitter for compressed- data or linear-PCM output — Dedicated 8 kilobyte input buffer — DAC clock via analog phase-locked loop — Dedicated byte wide or serial host interface — Multiple compressed data input modes — PES layer decode for A/V synchronization — 96-kHz-capable PCM I/O, master or slave — Optional external memory and auto-boot — +3.3-V CMOS low-power, 44-pin package lCS4923/4/5/6 features — Capable of Dolby Digital® Group A Performance — Dolby bass manager and crossover filters — Dolby Surround Pro Logic ® Decoding lCS4925/7: MPEG-2 Multi-Channel Decoder lCS4926/8: DTS Multi-Channel Decoder lCS4929: AAC 2-Channel (Low Complexity) and MPEG-2 Stereo Decoder

Description

The CS4923/4/5/6/7/8 is a family of multi-channel digital audio decoders, with the exception of the CS4929 as the only stereo digital audio decoder. The CS4923/4/5/6 are designed for Dolby Digital and MPEG-2 Stereo decoding. In addition the CS4925 adds MPEG-2 multi-channel decoding capability and the CS4926 provides DTS decoding. The CS4927 is an MPEG-2 multi-channel decoder and the CS4928 is a DTS multi-channel decoder. The CS4929 is an AAC 2-channel and MPEG-2 stereo decoder. Each one of the CS4923/4/5/6/7/8/9 provides a complete and flexible solution for multi-channel (or stereo in the case of the CS4929) audio decoding in home A/V receiver/amplifiers, DVD movie players, out-board decoders, laser-disc players, HDTV sets, head-end decoders, set-top boxes, and similar products. Cirrus Logic’s Crystal Audio Division provides a complete set of audio decoder and auxiliary audio DSP application programs for various applications. For all complementary analog and digital audio I/O, Crystal Audio also provides a complete set of high-quality audio peripherals including: multimedia CODECs, stereo A/D and D/A converters and IEC60958 interfaces. Of special note, the CS4226 is a complementary CODEC providing a digital receiver, stereo A/D converters, and six 20-bit DACs in one package.

ORDERING INFORMATION

CS4923xx-CL 44-pin PLCC (xx = ROM revision) CRD4923 Reference design with CS4226 CDB4923 Evaluation board AUG ‘99 DS262F2 DATA7:0, CS Parallel or Serial Host Interface CMPCLK, Compressed PLL FILT1 VA Framer DD DC MCLK SCLK LRCLK AUDATA[2.0] XMT958 CMPDAT, SCLKN2 CMPREQ, LRCLKN2 SCLKN1, STCCLK2 LRCLKN1 SDATAN1 Data Input Interface Digital Audio Input Interface FILT2 AGND Clock Manager CLKIN CLKSEL Shifter Input Buffer Controller RAM Input Buffer DGND[3:1] VD[3:1] 24-Bit DSP Processing RAM Program Memory RAM Data Memory ROM Program Memory ROM Data Memory STC EMAD7:0, GPIO7:0 R/W, EMOE, GPIO11 RD, DS, EMWR, GPIO10 WR, SCDOUT, PSEL, GPIO9 SCDIO, A0, SCCLK A1, SCDIN ABOOT, INTREQ EXTMEM, GPIO8 Output FormatterRAM Buffer Output RESET SDATAN2

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Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Dolby, Dolby Digital, and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corporation. Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductor. All other names are trademarks, registered trademarks, or service marks of their respective companies. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com.

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1. CHARACTERISTICS AND SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; all voltages with respect to 0 V) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; all voltages with respect to 0 V) DIGITAL D.C. CHARACTERISTICS (TA = 25°C; VA, VD[3:1] = 3.3 V– 5%; measurements performed under static conditions.) POWER SUPPLY CHARACTERISTICS (TA = 25°C; VA, VD[3:1] = 3.3 V– 5%; measurements performed under operating conditions) Parameter Symbol Min Max Unit DC power supplies: Positive digital Positive analog VD VA –0.3 –0.3 3.63 3.63 0.4 V V V Input current, any pin except supplies I in - – 10 mA Digital input voltage V IND –0.3 5.5 V Ambient operating temperature (power applied) T Amax –55 125 °C Storage temperature T stg –65 150 °C Parameter Symbol Min Typ Max Unit DC power supplies: Positive digital Positive analog VD VA 3.13 3.13 3.3 3.3 3.47 3.47 0.4 V V V Ambient operating temperature T A 0- 7 0 °C Parameter Symbol Min Typ Max Unit High-level input voltage V IH 2.0 - - V Low-level input voltage V IL --0 . 8V High-level output voltage at IO = –4.0 mA V OH VD · 0.9 - - V Low-level output voltage at IO = 4.0 mA V OL -- V D · 0.1 V Input leakage current I in --1 . 0 mA Parameter Symbol Min Typ Max Unit Power supply current: Digital operating: VD[3:1] Analog operating: VA 225 435 mA mA

Figure 1. RESET Timing

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Figure 2. Serial Compressed Data Timing

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SWITCHING CHARACTERISTICS—INTEL ® HOST MODE (TA = 25°C; VA, VD = 3.3 V– 5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can be defined as follows: External CLKIN Mode: DCLK == CLKIN/3 before and during boot DCLK == CLKIN after boot Internal Clock Mode: DCLK == 10MHz before and during boot, i.e. DCLK == 100ns DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see CS4923/4/5/6/7/8/9 Hardware User’s Guide for more information) 2. This specification is characterized but not production tested. Parameter Symbol Min Max Unit Address setup before CS and RD low or CS and WR low Tias 5- n s Address hold time after CS and RD low or CS and WR low Tiah 5- n s Delay between RD then CS low or CS then RD low Ticdr 0 ¥ ns Data valid after CS and RD low Tidd -2 0 n s CS and RD low for read (Note 1) Tirpw DCLK + 10 - ns Data hold time after CS or RD high Tidhr 5- n s Data high-Z after CS or RD high (Note 2) Tidis -1 5 n s CS or RD high to CS and RD low for next read (Note 1) Tird 2*DCLK + 10 - ns CS or RD high to CS and WR low for next write (Note 1) Tirdtw 2*DCLK + 10 - ns Delay between WR then CS low or CS then WR low Ticdw 0 ¥ ns Data setup before CS or WR high Tidsu 20 - ns CS and WR low for write (Note 1) Tiwpw DCLK + 10 - ns Data hold after CS or WR high Tidhw 5- n s CS or WR high to CS and RD low for next read (Note 1) Tiwtrd 2*DCLK + 10 - ns CS or WR high to CS and WR low for next write (Note 1) Tiwd 2*DCLK + 10 - ns

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SWITCHING CHARACTERISTICS—MOTOROLA ® HOST MODE (TA = 25°C; VA, VD = 3.3 V– 5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes: 3. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can be defined as follows: External CLKIN Mode: DCLK == CLKIN/3 before and during boot DCLK == CLKIN after boot Internal Clock Mode: DCLK == 10MHz before and during boot, i.e. DCLK == 100ns DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see CS4923/4/5/6/7/8/9 Hardware Users Guide for more information) 4. This specification is characterized but not production tested. Parameter Symbol Min Max Unit Address setup before CS and DS low Tmas 5- n s Address hold time after CS and DS low Tmah 5- n s Delay between DS then CS low or CS then DS low Tmcdr 0 ¥ ns Data valid after CS and DS low with R/W high Tmdd -2 0 n s CS and DS low for read (Note 3) Tmrpw DCLK + 10 - ns Data hold time after CS or DS high after read Tmdhr 5- n s Data high-Z after CS or DS high low after read (Note 4) Tmdis -1 5 n s CS or DS high to CS and DS low for next read (Note 3) Tmrd 2*DCLK + 10 - ns CS or DS high to CS and DS low for next write (Note 3) Tmrdtw 2*DCLK + 10 - ns Delay between DS then CS low or CS then DS low Tmcdw 0 ¥ ns Data setup before CS or DS high Tmdsu 20 - ns CS and DS low for write (Note 3) Tmwpw DCLK + 10 - ns R/W setup before CS or DS low Tmrwsu 5- n s R/W hold time after CS or DS high Tmrwhld 5- n s Data hold after CS or DS high Tmdhw 5- n s CS or DS high to CS and DS low with R/W high for next read (Note 3) Tmwtrd 2*DCLK + 10 - ns CS or DS high to CS and DS low for next write (Note 3) Tmwd 2*DCLK + 10 - ns

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SWITCHING CHARACTERISTICS—SPI CONTROL PORT (TA = 25°C; VA, VD = 3.3 V– 5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes: 5. The specification fsck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the software. The relevant application code user’s manual should be consulted for the software speed limitations. 6. Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK. 7. SCDOUT should not be sampled during this time period. 8. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the second-to-last bit of the last byte of data during a read operation as shown. 9. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat this condition as a new read transaction. Raise chip select to end the current read transaction and then drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start a new read transaction. 10. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time. 11. This time is by design and not tested. Parameter Symbol Min Max Units SCCLK clock frequency (Note 5) f sck -2 0 0 0 k H z CS falling to SCCLK rising t css 20 - ns Rise time of SCCLK line (Note 11) t r -5 0 n s Fall time of SCCLK lines (Note 11) t f -5 0 n s SCCLK low time t scl 150 - ns SCCLK high time t sch 150 - ns Setup time SCDIN to SCCLK rising t cdisu 50 - ns Hold time SCCLK rising to SCDIN (Note 6) t cdih 50 - ns Transition time from SCCLK to SCDOUT valid (Note 7) t scdov -4 0 n s Time from SCCLK rising to INTREQ rising (Note 8) t scrh -2 0 0 n s Rise time for INTREQ (Note 8) t rr -( N o t e 10) ns Hold time for INTREQ from SCCLK rising (Note 9, 11) t scrl 0- n s Time from SCCLK falling to CS rising t sccsh 20 - ns High time between active CS tcsht 200 - ns Time from CS rising to SCDOUT high-Z (Note 11) t cscdo 10 ns

Figure 9. SPI Control Port Timing

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SWITCHING CHARACTERISTICS— I 2C ® CONTROL PORT (TA = 25°C; VA, VD = 3.3 V– 5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes: 12. The specification fscl indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the software. The relevant application code user’s manual should be consulted for the software speed limitations. 13. Data must be held for sufficient time to bridge the 300-ns transition time of SCCLK. This hold time is by design and not tested. 14. This rise time is shorter than that recommended by the I 2C specifications. For more information, see the section on SCP communications. 15. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the last data bit of the last byte of data during a read operation as shown. 16. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat this condition as a new read transaction. Send a new start condition followed by the 7-bit address and the R/W bit (set to 1 for a read). This time is by design and is not tested. 17. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time. 18. This time is by design and not tested. Parameter Symbol Min Max Units SCCLK clock frequency (Note 12) f scl 400 kHz Bus free time between transmissions t buf 4.7 ms Start-condition hold time (prior to first clock pulse) t hdst 4.0 ms Clock low time t low 1.2 ms Clock high time t high 1.0 ms SCDIO setup time to SCCLK rising t sud 250 ns SCDIO hold time from SCCLK falling (Note 13) t hdd 0 ms Rise time of SCCLK (Note 14), (Note 18) t r 50 ns Fall time of SCCLK (Note 18) t f 300 ns Time from SCCLK falling to CS4923/4/5/6/7/8/9 ACK t sca 40 ns Time from SCCLK falling to SCDIO valid during read operation tscsdv 40 ns Time from SCCLK rising to INTREQ rising (Note 15) t scrh 200 ns Hold time for INTREQ from SCCLK rising (Note 16) t scrl 0n s Rise time for INTREQ trr (Note 17) ns Setup time for stop condition t susp 4.7 ms

Figure 10. I2C Control Port Timing

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SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT (TA = 25°C; VA, VD = 3.3 V– 5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF) Notes: 19. Master mode timing specifications are characterized, not production tested. 20. Master mode is defined as the CS4923 driving LRCLKN1(2) and SCLKN1(2). Master or Slave mode can be programmed. 21. This timing parameter is defined from the non-active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid. 22. This timing parameter is defined from the active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid. 23. Slave mode is defined as SCLKN1(2) and LRCLKN1(2) being driven by an external source. Parameter Symbol Min Max Unit SCLKN1(2) period for both Master and Slave mode (Note 19) T sclki 40 - ns SCLKN1(2) duty cycle for Master and Slave mode (Note 19) 45 55 % Master Mode (Note 19,20) LRCLKN1(2) delay after SCLKN1(2) transition (Note 21) T lrds -1 0 n s SDATAN1(2) setup to SCLKN1(2) transition (Note 22) T sdsum 10 - ns SDATAN1(2) hold time after SCLKN1(2) transition (Note 22) T sdhm 5- n s Slave Mode (Note 23) Time from active edge of SCLKN1(2) to LRCLKN1(2) transition T stlr 10 - ns Time from LRCLKN1(2) transition to SCLKN1(2) active edge T lrts 10 - ns SDATAN1(2) setup to SCLKN1(2) transition (Note 22) T sdsus 5- n s SDATAN1(2) hold time after SCLKN1(2) transition (Note 22) T sdhs 5- n s

Figure 11. Digital Audio Input, Data and Clock Timing

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SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT (TA = 25°C; VA, VD = 3.3 V– 5%; measurements performed under static conditions.) Notes: 24. MCLK can be an input or an output. These specifications apply for both cases. 25. Master mode timing specifications are characterized, not production tested. 26. Master mode is defined as the CS4923 driving both SCLK and LRCLK. When MCLK is an input, it is divided to produce SCLK and LRCLK. 27. This timing parameter is defined from the non-active edge of SCLK. The active edge of SCLK is the point at which the data is valid. 28. Slave mode is defined as SCLK and LRCLK being driven by an external source. 29. This specification is characterized, not production tested. Parameter Symbol Min Max Unit MCLK period (Note 24) T mclk 40 - ns MCLK duty cycle (Note 24) 40 60 % SCLK period for Master or Slave mode (Note 25) T sclk 40 - ns SCLK duty cycle for Master or Slave mode (Note 25) 45 55 % Master Mode (Note 25,26) SCLK delay from MCLK rising edge, MCLK as an input T sdmi 15 ns SCLK delay from MCLK rising edge, MCLK as an output T sdmo –5 10 ns LRCLK delay from SCLK transition (Note 27) T lrds 10 ns AUDATA2–0 delay from SCLK transition (Note 27) T adsm 10 ns Slave Mode (Note 28) Time from active edge of SCLKN1(2) to LRCLKN1(2) transition Tstlr 10 - ns Time from LRCLKN1(2) transition to SCLKN1(2) active edge Tlrts 10 - ns AUDATA2–0 delay from SCLK transition (Note 27,29) T adss 15 ns

Figure 12. Digital Audio Output, Data and Clock Timing

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the hardware designer and the system programmer. determined by referencing Table 1 below. depending on the input data type. to) set top box applications, DVDs and digital TVs. Table 1. Silicon Revisions

User’s Guide to determine which formats are sup- ported by a particular application. A brief descrip- tion of each format is presented below. Elementary - an elementary bitstream consists only of compressed audio data (e.g., strictly the Dolby Digital bitstream); used primarily in broadcast en- vironments. PES - a Packetized Elementary Stream (PES) bit- stream contains the elementary compressed audio stream and additional header information which can be used for A/V synchronization; used primari- ly in broadcast environments. IEC61937 - a method of packing compressed audio such that it can be delivered using a bi-phase en- coded signal (e.g., S/PDIF output signal from DVD player); used primarily for outboard decoders where A/V synchronization is not required.

2.1 Multi-channel Decoder Family of Parts

CS4923 - Dolby DigitalTM Audio Decoder. The CS4923 is the original member of the family and is intended to be used if only Dolby Digital decoding is required. For Dolby Digital, post processing includes bass management, delays and Dolby Pro Logic decoding. Separate downloads can also be used to support stereo to 5.1 channel effects processing and stereo MPEG decoding. CS4924 - Dolby Digital TM Source Product Decoder. The CS4924 is the stereo version of the CS4923 designed for source products such as DVD, HDTV, and set-top boxes. Separate downloads are available for stereo decode of Dolby Digital and MPEG audio. CS4925 - International Multi-Channel DVD Audio Decoder. The CS4925 supports both Dolby Digital and MPEG-2 multi-channel formats. For both Dolby Digital and MPEG-2 multi-channel, post processing includes bass management and Dolby Pro Logic decoding. Separate downloads are available for decode of Dolby Digital and MPEG audio. Another code load can be used to support stereo to 5.1 channel effects processing. CS4926 - DTS/Dolby ® Multi-Channel Audio Decoder. The CS4926 supports both Dolby Digital and DTS, or Digital Theater Surround. For Dolby Digital, post processing includes bass management and Dolby Pro Logic. The Dolby Digital code and DTS code take separate code downloads. Separate downloads can also be used to support stereo to 5.1 channel effects processing and stereo MPEG decoding. CS4927 - MPEG-2 Multi-Channel Decoder. The CS4927 supports MPEG-2 multi-channel decoding and should be used in applications where Dolby Digital decoding is not necessary. For MPEG-2 multi-channel decoding, post processing includes bass management and Dolby Pro Logic decoding. Another code load can be used to support stereo to 5.1 channel effects processing. CS4928 - DTS Multi-Channel Decoder. The CS4928 supports DTS multi-channel decoding and should be used in applications where Dolby Digital decoding is not necessary. For DTS multi-channel decoding, post processing includes bass management. Separate downloads can also be used to support stereo to 5.1 channel effects processing and stereo MPEG decoding. CS4929 - AAC 2-Channel, (Low Complexity) and MPEG-2 Stereo Decoder. The CS4929 is capable of decoding both 2-channel AAC and MPEG-2 audio. The CS4929 supports elementary and PES formats.

2.2 Document Strategy

Multiple documents are needed to fully define, understand and implement the functionality of the CS4923/4/5/6/7/8/9. They can be split up into two basic groups: hardware and application code documentation. It should be noted that hardware and application code are co-dependent and one can not successfully use the device without an

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understanding of both. The ‘ANXXX’ notation denotes the application note number under which the respective user’s guide was released.

2.2.1 Hardware Documentation

CS4923/4/5/6/7/8/9 Family Data Sheet - This document describes the electrical characteristics of the device from timing to base functionality. This is the hardware designers tool to learn the part’s electrical and systems requirements. AN115 - CS4923/4/5/6/7/8/9 Hardware User’s Guide - describes the functional aspects of the device. An in depth description of communication, boot procedure, external memory and hardware configuration are given in this document. This document will be valuable to both the hardware designer and the system programmer.

2.2.2 CS4923/4/5/6/7/8/9 Application Code

User’s Guides The following application notes describe the application codes used with the CS4923/4/5/6/7/8/9. Whenever an application code user’s guide is referred to, it should be assumed that one or more of the below documents are being referenced. The following list covers currently released application notes. This list will grow with each new application released. For a current list of released user’s guides please see www.crystal.com and search for the part number. AN120 - Dolby Digital User’s Guide for the CS4923/4/5/6. This document covers the features available in the Dolby Digital code including delays, pink noise, bass management, Pro Logic, PCM pass through and Dolby Digital processing features. Optional appendices are available that document code for Dolby Virtual, Q-Surround and VMAx. AN121 - MPEG User’s Guide for the CS4925. This document covers the features available in the MPEG Multi-Channel code including delays, bass management, Pro Logic, and MPEG processing features. AN122 - DTS User’s Guide for the CS4926, CS4928 . This document covers the features available in the DTS code including bass management and DTS processing features. AN123 - Surround User’s Guide for the CS4923/4/5/6/7/8. This code covers the different Stereo PCM to surround effects processing code. Optional appendices are available that document Crystal Original Surround, Circle Surround and Logic 7. AN140 - Broadcast Systems Guide for the CS4923/4/5/6/7/8/9. This guide describes all application code (e.g. Dolby Digital, MPEG, AAC) designed for broadcast systems such as HDTV and set-top box receivers. This document also provides a discussion of broadcast system considerations and dependencies such as A/V synchronization and channel change procedures.

2.3 Using the CS4923/4/5/6/7/8/9

No matter what application is being used on the chip, the following four steps are always followed to use the CS4923/4/5/6/7/8/9 in system. 1) Reset and/or Download Code - Detailed information in AN115 2) Hardware Configuration - Detailed information in AN115 3) Application configuration - Detailed information in the appropriate Application Code User’s guide 4) Kickstart - This is the “Go” command to the CS492X once the system is properly configured. Information can be found in the appropriate Application Code User’s guide.

1. TYPICAL CONNECTION DIAGRAMS Six typical connection diagrams have been presented to illustrate using the device with the different communication modes available. They are as follows: Figure 13: I 2C Control Figure 14: I2C Control with External Memory Figure 15: SPI Control Figure 16: SPI Control with External Memory Figure 17: Intel Parallel Control Mode Figure 18: Motorola Parallel Control Mode The following should be noted when viewing the typical connection diagrams: The pins are grouped functionally in each of the typical connection diagrams. Please be aware that the CS4923/4/5/6/7/8/9 symbol may appear differently in each diagram. The external memory interface is only supported when a serial communication mode has been chosen. The typical connection diagrams demonstrate the PLL being used (CLKSEL is pulled low). To enable external CLKIN, CLKSEL should be pulled high. The system designer must be aware that certain software features may not be available if external CLKIN is used as the DSP must run slower when external CLKIN is used. The system designer should also be aware of additional duty cycle requirements when using external CLKIN mode. It is highly suggested that the system designer take advantage of the PLL and pull CLKSEL low.

3.1 Multiplexed Pins

The CS4923/4/5/6/7/8/9 family of digital signal processors (DSPs) incorporate a large amount of flexibility into a 44 pin package. Because of the high degree of integration, many of these pins are internally multiplexed to serve multiple purposes. Some pins are designed to operate in one mode at power up, and serve a different purpose when the DSP is running. Other pins have functionality which can be controlled by the application running on the DSP. In order to better explain the behavior of the part, the pins which are multiplexed have been given multiple names. Each name is specific to the pin’s operation in a particular mode. An example of this would be the use of pin 20 in one of the serial control modes. During the boot period of the CS492X, pin 20 is called ABOOT ABOOT is sampled on the rising edge of RESET. If ABOOT is high the host must download code to the DSP. If ABOOT is low when sampled, the CS492X goes into autoboot mode and loads itself with code by generating addresses and reading data on EMAD[7:0]. When the device has been loaded with code and is running an application, however, pin 20 is called INTREQ . INTREQ is an open drain output used to inform the host that the DSP has an outgoing message which should be read. In this document, pins will be referred to by their functionality. The section “Pin Descriptions” on page 49 describes each pin of the CS492X and lists all of its names. Please refer to the Pin Descriptions section when exact pin numbers are in question. The device has 12 general purpose input and output (GPIO[11:0]) pins that all have multiple functionality. While in one of the parallel communication modes (see section 6.2), these pins are used to implement the parallel host communication interface. While in one of the serial host modes these pins are used to implement an external memory interface. Alternatively while in one of the serial host modes these pins could be used for another general purpose if the application code has been programmed to support the special purpose. In this document the pins are referenced by the name corresponding to their particular use. Sometimes GPIO[11:0], or some subset thereof, is used when referring to the pins in a general sense.

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3.2 Termination Requirements

The CS4923/4/5/6/7/8/9 incorporates open drain pins which must be pulled high for proper operation. INTREQ (pin 20) is always an open drain pin which requires a pull-up for proper operation. When in the I 2C serial communication mode, the SCDIO signal (pin 19) is open drain and thus requires a pull-up for proper operation. Due to the internal, multiplexed design of the pins, certain signals may or may not require termination depending on the mode being used. If a parallel host communication mode is not being used, GPIO[11:0] must be terminated or driven as these pins will come up as high impedance inputs and will be prone to oscillation if they are left floating. The specific termination requirements may vary since the state of some of the GPIO pins will determine the communication mode at the rising edge of reset (please see section 6 for more information). For the explicit termination requirements of each communication mode please see the typical connection diagrams. Generally a 4.7k Ohm resistor is recommended for open drain pins while a 10k Ohm resistor is sufficient for the GPIO pins and unused inputs.

3.3 Phase Locked Loop Filter

The internal phase locked loop (PLL) of the CS4923/4/5/6/7/8/9 requires an external filter for successful operation. The topology of this filter and component values are shown in the typical connection diagrams. Care should be taken when laying out the filter circuitry to minimize trace lengths and to avoid any close routing of high frequency signals. Any noise coupled on to the filter circuit will be directly coupled into the PLL, which could affect performance.

Figure 13. I2C Control NOTE: A capacitor pair (1 u F and 0.1 uF) must be supplied for each power pin.

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NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. Figure 14. I2C Control with External Memory

Figure 15. SPI Control NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin.

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Figure 16. SPI Control with External Memory NOTE: A capacitor pair (1 u F and 0.1 uF) must be supplied for each power pin.

Figure 17. Intel Parallel Control Mode NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin.

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Figure 18. Motorola Parallel Control Mode NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin.

1. POWER The CS492X requires a 3.3V digital power supply for the digital logic within the DSP and a 3.3V analog power supply for the internal PLL. There are three digital power pins, VD1, VD2 and VD3, along with three digital grounds, DGND1, DGND2 and DGND3. There is one analog power pin, VA and one analog ground, AGND. The DSP will perform at its best when noise has been eliminated from the power supply. The recommendations given below for decoupling and power conditioning of the CS492X will help to ensure reliable performance.

4.1 Decoupling

It is good practice to decouple noise from the power supply by placing capacitors directly between the power and ground of the CS492X. Each pair of power pins (VD1/DGND, VD2/DGND, VD3/DGND, VA/AGND) should have its own decoupling capacitors. The recommended procedure is to place both a 0.1uF and a 1uF capacitor as close as physically possible to each power pin. The 0.1uF capacitor should be closest to the device (typically 5mm or closer).

4.2 Analog Power Conditioning

In order to obtain the best performance from the CS4923/4/5/6/7/8/9’s internal PLL, the analog power supply (VA) must be as clean as possible. A ferrite bead should be used to filter the 3.3V power supply for the analog portion of the CS492X. This power scheme is shown in the typical connection diagrams.

4.3 Pads

Revision D and all subsequent revisions incorporate 5V tolerant pads. This means that while the CS492X power supplies require 3.3 volts, 5 volt signals can be applied to the inputs without damaging the part. The I/O pads for Revision B of the CS4923/4/5/6 are not 5 volt tolerant. Input levels for revision B of the CS4923/4/5/6 should be no greater than 3.3

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1. CLOCKING incorporates a programmable phase locked loop (PLL) clock synthesizer. The PLL takes an input reference clock and produces all the internal clocks required to run the internal DSP and to provide master mode timing to the audio input/output peripherals. The clock manager also includes a 33-bit system time clock (STC) to support audio and video synchronization in broadcast applications. The PLL can be internally bypassed by connecting the CLKSEL pin to VD. This connection multiplexes the CLKIN pin directly to the DSP clock. Care should be taken to note the minimum CLKIN requirements when bypassing the PLL. The PLL reference clock has three possible sources that are routed through a multiplexer controlled by the DSP: SCLKN2, SCLKN1, and CLKIN. Typically, in audio/video environments like set-top boxes, the CLKIN pin is connected to 27 MHz. In other scenarios such as an A/V receiver design, the PLL can be clocked through the CLKIN pin with even multiples of the desired sampling rate or with an already available clock source. CLKIN is typically a multiple of a standard sampling frequency in this scenario (e.g. 11.2896 MHz). The clock manager is controlled by the DSP application software. Please refer to the Hardware User’s Guide for the CS4923/4/5/6/7/8/9 (AN115) and all relevant application code user’s guides for information on supported CLKIN frequencies and how to set up and control the internal PLL.

the DTS tables is available from the factory.

6.1 Boot and Control Mode Overview

• Parallel Download through the parallel host in- terface
• Serial download through either the SPI or I interface
• Autoboot with external memory when using a serial communication mode. Once again the CS4923/4/5/6/7/8/9 Hardware User’s Guide should be consulted for a complete description of the boot and download procedure including the necessary communication handshaking. Hardware configuration is also RD (Pin 5) WR (Pin 4) PSEL (Pin 19) Host Interface Mode 1 1 1 8-bit Motorola 1 1 0 8-bit Intel

01 X Serial I

Table 2. Host Modes

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6.2 Parallel Host Interface

CS4923/4/5/6/7/8/9 Hardware User’s Guide.

6.2.1 Intel Parallel Host Mode

WR have no effect when CS is held high. satisfy the hold time as given in the timing section. byte in the HOSTMSG register is read by the DSP. effect and DATA[7:0] are high impedance. Table 3. Host Memory Map Table 4. Intel Parallel Host Mode Pin Assignments

Reserved Always write a 0 for future compatibility. holds the port in reset. Writing zero enables the port. This bit must be low for normal operation. Reserved Always write a 0 for future compatibility. Table 5. Parallel Input/Output Registers

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6.2.2 Motorola Parallel Host Mode

number of each signal on the CS4923/4/5/6/7/8/9. low data strobe, DS, and a R/W control signal. is high and DS and CS are both low. written and DATA[7:0] carry the data to be written. satisfy the hold time as given in the timing section.

6.3 SPI Serial Host Interface

CS492X when there is data to be read out. Table 6. Motorola Parallel Host Mode Pin Assignments Table 7. SPI Serial Mode Pin Assignments

6.3.1 SPI Write

When writing to the device in SPI, the same protocol can be used for sending a byte, a word or an entire download image as long as transfers occur on byte boundaries. Figure 19 illustrates the relative timing necessary for a three byte transfer to the CS492X. The host initiates an SPI write by driving CS low, followed by a 7-bit address and the read/write bit set low to indicate a write. The CS4923/4/5/6/7/8/9 internal 7-bit address is initially assigned to 000 0000b following a reset. The 7-bit address sent to the CS492X must match its internal address or the incoming data will be ignored. Address checking can be changed (either disabled or an actual address change) if desired. Address checking configuration is documented in the hardware configuration section of the CS4923/4/5/6/7/8/9 Hardware User’s guide. Data should be shifted into the CS492X most significant bit first with data being valid at the rising edge of SCCLK. It should be noted that data is internally transferred to the DSP on the falling edge of the eighth SCCLK after the eighth data bit of a byte. For this reason SCCLK must transition from high to low on the last bit of each byte or a loss of data will occur. If this final transfer of SCCLK does not occur the final byte will be lost and successful communication will not be possible.

6.3.2 SPI Read

The CS4923/4/5/6/7/8/9 will always indicate that it has data to be read by asserting the INTREQ line low. The host must recognize the request and start a read transaction with the CS492X. The same protocol will be used whether reading a byte or multiple bytes. Figure 19 also illustrates the relative timing of a three byte SPI read. The host initiates an SPI read by driving CS low, followed by a 7-bit address and the read/write bit set high to indicate a read. The CS492X internal 7- bit address is initially assigned to 000 0000b following a reset. The 7-bit address sent to the CS492X must match its internal address or the incoming data will be ignored. Address checking can be disabled or the actual address can be changed if desired. Address checking configuration is documented in the hardware configuration section of the CS4923/4/5/6/7/8/9 Hardware User’s guide. After the address byte the host should clock data out of the device one byte at a time until INTREQ is no longer low. The host shifts data using the rising edge of SCCLK. The data is valid on the rising edge of SCCLK and transitions occur on the falling edge. In SPI mode, the INTREQ pin is deasserted immediately following the rising edge of the second-to-last data bit of the current byte being transferred if there is no more data to be read. The INTREQ pin is guaranteed to stay deasserted (high) until the rising edge of SCCLK for the last data bit. If there is more data to be read from the DSP before the rising edge of SCCLK for the second-to-last data bit, then INTREQ remains asserted low. Immediately following the falling edge of SCCLK for the last data bit of the current byte, the next data byte loads into the internal serial shift register. The host should continue to read this new byte. It is important to note that once the data is in the shift register, clocks on the SCCLK line shift the data bits out of the shift register as long as CS is low. For a thorough look at SPI communication and critical additional comments on INTREQ behavior reference the CS4923/4/5/6/7/8/9 Hardware User’s Guide.

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Figure 19. SPI Timing

1. INTREQ is guaranteed to stay high until the next rising edge of SCCLK at which point it may

6.4 I2C Serial Host Interface

met as stated in the timing portion of this data sheet.

6.4.1 I2C Write

the actual address can be changed if desired. the CS492X for one SCCLK period after each byte. the rising edge of SCDIO while SCCLK is held high.

6.4.2 I2C Read

of the CS4923/4/5/6/7/8/9 Hardware User’s guide. Table 8. I2C Serial Mode Pin Assignments

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Figure 20. I2C Timing Notes: 1. The ACK for the address byte is driven by the CS4923/4/5/6/7/8/9.

1. The ACK s for the data bytes being read from the CS4923/4/5/6/7/8/9 should be driven by the
2. INTREQ is guaranteed to stay low until the rising edge of SCCLK for last bit of the last byte to
3. A NOACK should be sent by the host after the last byte read to indicate the end of the read
4. INTREQ is guaranteed to stay high until the next rising edge of SCCLK (for the ACK/NACK

followed by an address byte should be sent.

an acknowledge from the part. edge of SCCLK for the acknowledge bit.

6.5 External Memory

memory is required for external DTS tables. real time access as well as ROM speed requirements. timing of a run-time memory access . Table 9. Memory Interface Pins

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8 BIT

Only one of R1 and R2 should be stuffed. Only one of R3 and R4 shou ld be stuffed. Figure 21. External Memory Interface Figure 22. Run-Time Memory Access

incorporates a 2 latch memory architecture. run time memory access uses only 2 address cycles.

6.5.1 External Memory and Autoboot

leaves the reset state enables an automatic boot. shows an autoboot functional timing example. autoboot, the most significant byte is always zero. CS4923/4/5/7/9 but it is not necessary. Figure 23. Autoboot Timing Diagram

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1. DIGITAL INPUT & OUTPUT The CS4923/4/5/6/7/8/9 supports a wide variety of data input and output mechanisms through various input and output ports. Hardware availability is entirely dependent on whether the software application code being used supports the required mode. This data sheet presents most of the modes available with the CS4923/4/5/6/7/8/9 hardware. This does not mean that all of the modes are available with any particular piece of application code. Both the CS4923/4/5/6/7/8/9 Hardware User’s Guide and the application code user’s guide for the particular code being used should be referenced to determine if a particular mode is supported.

7.1 Digital Audio Formats

This subsection will describe some common audio formats that the CS4923/4/5/6/7/8/9 supports. It should be noted that the input ports use up to 24-bit PCM resolution and 16-bit compressed data word lengths. The output port of the CS492X provides up to 20-bit PCM resolution. I 2S: Figure 24 shows the I2S format. For I2S, data is presented most significant bit first, one SCLK delay after the transition of LRCLK and is valid on the rising edge of SCLK. For the I 2S format, the left subframe is presented when LRCLK is low and the right subframe is presented when LRCLK is high. SCLK is required to run at a frequency of 48Fs or greater on the input ports. Left Justified: Figure 25 shows the left justified format with a rising edge SCCLK. Data is presented most significant bit first on the first SCLK after an LRCLK transition and is valid on the rising edge of SCLK. For the left justified format, the left subframe is presented when LRCLK is high and the right subframe is presented when LRCLK is low. The left justified format can also be programmed for data to be valid on the falling edge of SCLK. SCLK is required to run at a frequency of 48Fs or greater on the input ports. Right Justified: Figure 26 shows the right justified format. The right justified format is similar to the left justified format except the least significant bit is right justified to be valid on the last transition of SCLK before an LRCLK transition. Data is still presented most significant bit first. For the right justified format, the left subframe is presented when LRCLK is high and the right subframe is presented when LRCLK is low. The right justified format can also be programmed for data being valid on the falling edge of SCLK. SCLK is required to run at a frequency of 48Fs or greater on the input ports. Multi-Channel: Figure 27 shows the multi- channel format. In this format up to 6 channels of audio are presented on one data line with 20 bits per channel. Channels 0, 2, and 4 are presented while the LR-CLK is high and channels 1, 3, 5 are presented while the LRCLK is low. Data is valid on the rising edge of SCLK and is presented most significant bit first. Because each of the ports is fully configurable, there may be modes that can be supported which are not presented.

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7.2 Digital Audio Input Port

both compressed and PCM digital audio data input. audio/video synchronization purposes.

7.3 Compressed Data Input Port

used for both compressed and PCM data input. i.e. in a system such as a set-top box or HDTV.

7.4 Parallel Digital Audio Data Input

deliver data through the byte wide parallel port. the default level may differ between applications. with hand-feeding the compressed data. Table 10. Digital Audio Input Port Table 11. Compressed Data Input Port

the first write to the byte-wide PCMDATA port. two writes to the right channel.

7.5 Digital Audio Output Port

supported by the download code being used. clock, where Fs is the output sample rate. inputs (Slave mode) or outputs (Master mode). Surround and Subwoofer) are provided. Table 12. Digital Audio Output Port

128 X X

256 X X X X

Table 13. MCLK/SCLK Master Mode Ratios

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guides to determine which modes are supported by the download code being used. Serial digital audio data bit placement and sample alignment is fully configurable in the CS4923/4/5/6/7/8/9 including left justified, right justified, delay bits or no delay bits, variable sample word sizes, variable output channel count, and programmable output channel pin assignments and clock edge polarity to integrate with most digital audio interfaces. If a mode is needed which is not supported, please consult your Crystal Representative as to its availability.

7.5.1 IEC60958 Output

The XMT958 output provides a CMOS level bi phase encoded output. The XMT958 function can be internally clocked from the PLL or from an MCLK input if MCLK is 256Fs or 512Fs. All channel status information can be used when using software which supports this functionality. This output can be used for either 2 channel PCM output or compressed data output in accordance with IEC61937. To be fully IEC60958 compliant this output would need to be buffered through an RS422 device or an optocoupler as its outputs are only CMOS. Please consult the CS4923/4/5/6/7/8/9 Hardware User’s Guide and an application code user’s guide to determine if this pin is supported by the download code being used.

1. PIN DESCRIPTIONS V A—Analog Positive Supply: Pin 34 Analog positive supply for clock generator. Nominally +3.3 V . AGND—Analog Supply Ground: Pin 35 Analog ground for clock generator PLL. VD1, VD2, VD3—Digital Positive Supply: Pins 1, 12, 23 Digital positive supplies. Nominally +3.3 V . DGND1, DGND2, DGND3—Digital Supply Ground: Pins 2, 13, 24 Digital ground. FILT1—Phase-Locked Loop Filter: Pin 33 Connects to an external filter for the on-chip phase-locked loop. This pin does not meet Cirrus Logic’s ESD tolerance of 2000 V using the human body model. This pin will tolerate ESD of 1000 V using the human body model. 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 CS4923-CL 44-pin PLCC Top View VD2 DATA4,EMAD4,GPIO4 VA DATA5,EMAD5,GPIO5 DATA6,EMAD6,GPIO6 DATA7,EMAD7,GPIO7 A0, SCCLK A1, SCDIN RD,R/W,EMOE,GPIO11 WR,DS,EMWR,GPIO10 XMT958 DGND1 VD1 SDATAN1 EXTMEM, GPIO8 ABOOT, INTREQ SCDIO, SCDOUT,PSEL,GPIO9 CS DATA0,EMAD0,GPIO0 DATA1,EMAD1,GPIO1 DATA2,EMAD2,GPIO2 DATA3,EMAD3,GPIO3 DGND2 RESET DD DC AUDATA2 AUDATA1 AUDATA0 LRCLK SCLK MCLK VD3 DGND3 SCLKN1, STCCLK2 LRCLKN1 CMPDAT, SDATAN2 CMPCLK, SCLKN2 CMPREQ, LRCLKN2 CLKIN CLKSEL FILT2 FILT1 AGND

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FILT2—Phase Locked Loop Filter: Pin 32 Connects to an external filter for the on-chip phase-locked loop. This pin does not meet Cirrus Logic’s ESD tolerance of 2000 V using the human body model. This pin will tolerate ESD of 1000 V using the human body model. CLKIN—Master Clock Input: Pin 30 CS4923/4/5/6/7/8/9 clock input. When in internal clock mode (CLKSEL == DGND), this input is connected to the internal PLL from which all internal clocks are derived. When in external clock mode (CLKSEL == VD), this input is connected to the DSP clock. INPUT CLKSEL—DSP Clock Select: Pin 31 This pin selects the clock mode of the CS4923/4/5/6/7/8/9. When CLKSEL is low, CLKIN is connected to the internal PLL from which all internal clocks are derived. When CLKSEL is high CLKIN is connected to the DSP clock. INPUT DATA7, EMAD7, GPIO7—Pin 8 DATA6, EMAD6, GPIO6—Pin 9 DATA5, EMAD5, GPIO5—Pin 10 DATA4, EMAD4, GPIO4—Pin 11 DATA3, EMAD3, GPIO3—Pin 14 DATA2, EMAD2, GPIO2—Pin 15 DATA1, EMAD1, GPIO1—Pin 16 DATA0, EMAD0, GPIO0—Pin 17 In parallel host mode, these pins provide a bidirectional data bus. If a serial host mode is selected, these pins can provide a multiplexed address and data bus for connecting an 8-bit external memory. Otherwise, in serial host mode, these pins can act as general-purpose input or output pins that can be individually configured and controlled by the DSP. BIDIRECTIONAL - Default: INPUT A0, SCCLK—Host Parallel Address Bit Zero or Serial Control Port Clock: Pin 7 In parallel host mode, this pin serves as one of two address input pins used to select one of four parallel registers. In serial host mode, this pin serves as the serial control clock signal, specifically as the SPI clock input or the I 2C clock input. INPUT A1, SCDIN—Host Parallel Address Bit One or SPI Serial Control Data Input: Pin 6 In parallel host mode, this pin serves as one of two address input pins used to select one of four parallel registers. In SPI serial host mode, this pin serves as the data input. INPUT RD , R/W, EMOE , GPIO11—Host Parallel Output Enable or Host Parallel R/W or External Memory Output Enable or General Purpose Input & Output Number 11: Pin 5 In Intel parallel host mode, this pin serves as the active-low data bus enable input. In Motorola parallel host mode, this pin serves as the read-high/write-low control input signal. In serial host mode, this pin can serve as the external memory active-low data-enable output signal. Also in serial host mode, this pin can serve as a general purpose input or output bit. BIDIRECTIONAL - Default: INPUT

WR , DS, EMWR , GPIO10—Host Write Strobe or Host Data Strobe or External Memory Write Enable or General Purpose Input & Output Number 10: Pin 4 In Intel parallel host mode, this pin serves as the active-low data-write-input strobe. In Motorola parallel host mode, this pin serves as the active-low data-strobe-input signal. In serial host mode, this pin can serve as the external-memory active-low write-enable output signal. Also in serial host mode, this pin can serve as a general purpose input or output bit. BIDIRECTIONAL - Default: INPUT CS —Host Parallel Chip Select, Host Serial SPI Chip Select: Pin 18 In parallel host mode, this pin serves as the active-low chip-select input signal. In serial host SPI mode, this pin is used as the active-low chip-select input signal. INPUT RESET —Master Reset Input: Pin 36 Asynchronous active-low master reset input. Reset should be low at power-up to initialize the CS4923/4/5/6/7/8/9 and to guarantee that the device is not active during initial power-on stabilization periods. At the rising edge of reset the host interface mode is selected contingent on the state of the RD , WR and PSEL pins. Additionally, an autoboot sequence can be initiated if a serial control mode is selected and ABOOT is held low. If reset is low all bidirectional pins are high impedance inputs. INPUT SCDIO, SCDOUT, PSEL, GPIO9—Serial Control Port Data Input and Output, Parallel Port Type Select: Pin 19 In I2C mode, this pin serves as the open-drain bidirectional data pin. In SPI mode this pin serves as the data output pin. In parallel host mode, this pin is sampled at the rising edge of RESET to configure the parallel host mode as an Intel type bus or as a Motorola type bus. In parallel host mode, after the bus mode has been selected, the pin can function as a general- purpose input or output pin. BIDIRECTIONAL - Default: INPUT In I 2C mode this pin is an OPEN DRAIN I/O and requires a 4.7k Pull-Up EXTMEM , GPIO8—External Memory Chip Select or General Purpose Input & Output Number 8: Pin 21 In serial control port mode, this pin can serve as an output to provide the chip-select for an external byte-wide ROM. In parallel and serial host mode, this pin can also function as a general-purpose input or output pin. BIDIRECTIONAL - Default: INPUT INTREQ , ABOOT —Control Port Interrupt Request, Automatic Boot Enable: Pin 20 Open-drain interrupt-request output. This pin is driven low to indicate that the DSP has outgoing control data and should be serviced by the host. Also in serial host mode, this signal initiates an automatic boot cycle from external memory if it is held low through the rising edge of reset. OPEN DRAIN I/O - Requires 4.7k Ohm Pull-Up AUDATA2—Digital Audio Output 2: Pin 39 PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT

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AUDATA1—Digital Audio Output 1: Pin 40 PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT AUDATA0—Digital Audio Output 0: Pin 41 PCM multi-format digital-audio data output, capable of two-, four-, or six-channel 20-bit output. This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT MCLK—Audio Master Clock: Pin 44 Bidirectional master audio clock. MCLK can be an output from the CS4923/4/5/6/7/8/9 that provides an oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs. MCLK can be an input at 128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to derive SCLK and LRCLK when SCLK and LRCLK are driven by the CS492X. BIDIRECTIONAL - Default: INPUT SCLK—Audio Output Bit Clock: Pin 43 Bidirectional digital-audio output bit clock. SCLK can be an output that is derived from MCLK to provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs, depending on the MCLK rate and the digital-output configuration. SCLK can also be an input and must be at least 48Fs or greater. As an input, SCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT LRCLK—Audio Output Sample Rate Clock: Pin 42 Bidirectional digital-audio output-sample-rate clock. LRCLK can be an output that is divided from MCLK to provide the output sample rate depending on the output configuration. LRCLK can also be an input. As an input LRCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT XMT958—SPDIF Transmitter Output: Pin 3 CMOS level output that contains a biphase-encoded clock for synchronously providing two channels of PCM digital audio or a IEC61937 compressed-data interface or both. This output typically connects to the input of an RS-422 transmitter or to the input of an optical transmitter. OUTPUT SCLKN1, STCCLK2—PCM Audio Input Bit Clock: Pin 25 Bidirectional digital-audio bit clock that is an output in master mode and an input in slave mode. In slave mode, SCLKN1 operates asynchronously from all other CS492X clocks. In master mode, SCLKN1 is derived from the CS492X internal clock generator. In either master or slave mode, the active edge of SCLKN1 can be programmed by the DSP. For applications supporting PES layer synchronization this pin can be used as STCCLK2, which provides a path to the internal STC 33 bit counter. BIDIRECTIONAL - Default: INPUT

LRCLKN1—PCM Audio Input Sample Rate Clock: Pin 26 Bidirectional digital-audio frame clock that is an output in master mode and an input in slave mode. LRCLKN1 typically is run at the sampling frequency. In slave mode, LRCLKN1 operates asynchronously from all other CS492X clocks. In master mode, LRCLKN1 is derived from the CS492X internal clock generator. In either master or slave mode, the polarity of LRCLKN1 for a particular subframe can be programmed by the DSP. BIDIRECTIONAL - Default: INPUT SDATAN1—PCM Audio Data Input Number One: Pin 22 Digital-audio data input that can accept from one to six channels of compressed or PCM data. SDATAN1 can be sampled with either edge of SCLKN1, depending on how SCLKN1 has been configured. INPUT CMPCLK, SCLKN2—PCM Audio Input Bit Clock: Pin 28 Bidirectional digital-audio bit clock that is an output in master mode and an input in slave mode. In slave mode, SCLKN2 operates asynchronously from all other CS492X clocks. In master mode, SCLKN2 is derived from the CS492X internal clock generator. In either master or slave mode, the active edge of SCLKN2 can be programmed by the DSP. If the CDI is configured for bursty delivery, CMPCLK is an input used to sample CMPDAT. BIDIRECTIONAL - Default: INPUT CMPREQ, LRCLKN2—PCM Audio Input Sample Rate Clock: Pin 29 When the CDI is configured as a digital audio input, this pin serves as a bidirectional digital- audio frame clock that is an output in master mode and an input in slave mode. LRCLKN2 typically is run at the sampling frequency. In slave mode, LRCLKN2 operates asynchronously from all other CS492X clocks. In master mode, LRCLKN2 is derived from the CS492X internal clock generator. In either master or slave mode, the polarity of LRCLKN2 for a particular subframe can be programmed by the DSP. When the CDI is configured for bursty delivery, or parallel audio data delivery is being used, CMPREQ is an output which serves as an internal FIFO monitor. CMPREQ is an active low signal that indicates when another block of data can be accepted. BIDIRECTIONAL - Default: INPUT CMPDAT, SDATAN2—PCM Audio Data Input Number Two: Pin 27 Digital-audio data input that can accept from one to six channels of compressed or PCM data. SDATAN2 can be sampled with either edge of SCLKN2, depending on how SCLKN2 has been configured. Similarly CMPDAT is the compressed data input pin when the CDI is configured for bursty delivery. When in this mode, the CS4923/4/5/6/7/8/9 internal PLL is driven by the clock recovered from the incoming data stream. INPUT DC—Reserved: Pin 38 This pin is reserved and should be pulled up with an external 4.7k resistor. DD—Reserved: Pin 37 This pin is reserved and should be pulled up with an external 4.7k resistor.

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1. PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.165 0.180 4.043 4.572 A1 0.090 0.120 2.205 3.048 B 0.013 0.021 0.319 0.533 D 0.685 0.695 16.783 17.653 D1 0.650 0.656 15.925 16.662 D2 0.590 0.630 14.455 16.002 E 0.685 0.695 16.783 17.653 E1 0.650 0.656 15.925 16.662 E2 0.590 0.630 14.455 16.002 e 0.040 0.060 0.980 1.524 44L PLCC PACKAGE DRAWING D E1 E D2/E2 B e A

• Notes •