CS4922 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
lDSP Optimized for Audio Decode, 24-bit Fixed Point w/48-bit Accumulator lOn-Chip Functional Blocks Include: - DSP with RAM and ROM Memories - CD Quality Stereo DAC with Output Filtering - Mono Output & Digital Volume Control - S/PDIF Transmitter, Bidirectional PCM Audio Port - Internal Phase Locked Loop for Clocking - Dedicated Compressed Serial Input Interface lMPEG-1 & MPEG-2 Layers 1 & 2 With All Sample/Bit Rates and Ancillary Data Support. lMPEG-1 & MPEG-2 Packetized Audio Stream and Elementary Stream Input lG.729A Audio Decode lPCM Synthesis for Auxiliary Audio lPin Compatibility with CS4920A and Primary Feature/Firmware Compatible l+5 Volt Only CMOS, 44 pin PLCC
Description
The CS4922 is a complete audio decompression sub- system implemented in a single high integration mixed signal CMOS chip. The CS4922 has been widely used in direct broadcast system set-top boxes and proprietary embedded systems which pull compressed audio from local system memory. The CS4922 is tailored to include the necessary hard- ware and firmware to ensure proper audio/video synchronization for MPEG-2 audio decompression. In addition to audio decoding this programmable DSP solu- tion provides robust error concealment and feature implementations like ancillary data support and PCM synthesis. The CS4922 can also support the decode of other com- pression standards such as G.729A with a separate download image. The flexible architecture of the CS4922 provides the ability to mix compressed audio with data from the auxiliary PCM port.
ORDERING INFORMATION
VD1 VD4 SCK/SCL SDA/CDOUT CDIN CS REQ VA+ Serial Control Port (SPI or I2C)AUXLR AUXIN AUXOUT AUXCLK FSYNC SCLK SDATA Auxiliary Serial Audio Port Serial Audio Port RESET 90_CLK BOOT 33 bit Counter DGND1 DGND4 DSP FLT CLKIN EXTCK ALTCLK CLKOUT PLL Clock Manager Stereo DAC AOUTM AOUTL AOUTR AES/EBU - S/PDIF TXTransmitter Programmable IO/ Pins PIO XF1 XF2 XF3 XF4 AGND1 AGND2 JUL ‘99 DS227PP2
SWITCHING CHARACTERISTICS - CONTROL PORT (I 4.7.1 I Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ I2C is a registered trademark of Philips Semiconductor. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com.
1 CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V; CLKIN = 27 MHz; Full-Scale Output Sinewave, 1.125 kHz; Word Clock = 48 kHz (PLL in use); Logic 0 = GND, Logic 1 = VD+; Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in "Typical Connection Diagram"; SPI mode, I2S audio data; unless otherwise specified.) Notes: 1. 10 kW , 100pF load for each analog signal (Left, Right). 30 kW , 100pF load for analog Mono signal. D/A INTERPOLATION FILTER CHARACTERISTICS (See Figures 20 through 23) * Refer to Parameter Definitions on page 31 of this data sheet. Specifications are subject to change without notice. Parameter* Symbol Min Typ Max Units Dynamic Performance DAC Resolution 16 - - Bits DAC Differential Nonlinearity DNL - - –0.9 LSB Total Harmonic Distortion AOUTL, AOUTR (Note 1) AOUTM THD - 0.01 0.02 0.015 0.03 Instantaneous Dynamic Range AOUTL, AOUTR (Note 1) (DAC not muted, A weighted) AOUTM IDR 85 -d B Interchannel Isolation (Note 1) - 85 - dB Interchannel Gain Mismatch - - 0.2 dB Frequency Response -3.0 - +0.2 dB Full Scale output Voltage AOUTL, AOUTR (Note 1) AOUTM 2.66 2.7 2.88 3.0 3.2 3.3 Vpp Gain Drift - 100 - ppm/°C Deviation from Linear Phase - - 5 Deg Out of Band Energy (Fs/2 to 2Fs) - -60 - dB Analog Output Load Resistance: Capacitance: 100 kW pF Power Supply Power Supply Rejection (1 kHz) - 40 - dB Power Supply Consumption VA+ VD+ 100 140 mA mA Parameter Symbol Min Typ Max Units Passband (to -3 dB corner) (Fs is conversion freq.). 0 - 0.476Fs Hz Passband Ripple. - - –0.1 dB Transition Band. 0.442Fs - 0.567Fs Hz Stop Band. ‡0.567Fs - - Hz Stop Band Rejection. 50 - - dB Stop Band Rejection with Ext. 2Fs RC filter. 57 - - dB Group Delay. - 12/Fs - s
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to ground.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V; all voltages with respect to ground.) DIGITAL CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V– 10%; measurements performed under static conditions.) Notes: 2. Not Valid for pin numbers 9, 12, 13, and 30 which are configured with on-chip pull-down resistors. Not valid for pin number 29 which is a static input signal and should be tied to either VD+ or DGND. Parameter Symbol Min Max Units DC Power Supplies: Positive Digital Positive Analog VD+ VA+ -0.3 -0.3 6.0 6.0 0.4 V V V Input Current, Any Pin Except Supplies I in - –10 mA Digital Input Voltage VIND -0.3 (VD+) + 0.4 V Ambient Operating Temperature (power applied) TAmax -55 125 °C Storage Temperature Tstg -65 150 °C Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital Positive Analog VD+ VA+ 4.50 4.50 5.0 5.0 5.50 5.50 0.4 V V V Ambient Operating Temperature T A 0- 7 0° C Parameter Symbol Min Typ Max Units High-Level Input Voltage VIH TBD 2.25 - V Low-Level Input Voltage VIL -- 0 . 8 V High-Level Output Voltage at Io = -2.0 mA VOH VD x 0.9 - - V Low-Level Output Voltage at Io = 2.0 mA VOL -- V D x 0 . 1 V Input Leakage Current (Note 2) Iin -- 1 . 0 mA
SWITCHING CHARACTERISTICS - CLOCKS (TA = 25 °C; VA+, VD+ = 5V; Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20pF) SWITCHING CHARACTERISTICS - EXTERNAL FLAGS (TA = 25 °C; VA+, VD+ = 5V; Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20pF) Notes: 3. Assumes 2kW pull-up to 5V supply on XF1-XF4 pins. SWITCHING CHARACTERISTICS - PROGRAMMABLE INPUT/OUTPUT (TA = 25°C; VA+, VD+ = 5V; Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20pF) Parameter Symbol Min Typ Max Units Master Clock Frequency CLKIN 27 MHz Master Clock Duty Cycle CYCK 40 50 60 % Clock Output CLKOUT - - 256 Fs MHz Parameter Symbol Min Typ Max Units Rise time of XF1-XF4 (Note 3) trxf 200 ns Fall time of XF1-XF4 tfxf 100 ns Parameter Symbol Min Typ Max Units I_O = 0 Input Frequency fpio 350 kHz Risetime of PIO trpio 200 ns Fall time of PIO tfpio 200 ns I_O = 1 Rise time of PIO trpo 200 ns Fall time of PIO tfpo 200 ns
Notes: 4. The mode of the Serial Control Port is selected by CS. CS = 1 is I2C â . CS = 0 is SPI mode.
- This delay is necessary after any rising edge of RESET to allow time for the part to initialize and for
the on-board PLL to stabilize. Figure 1. Boot Timing
SWITCHING CHARACTERISTICS - CONTROL PORT (SPI MODE) (TA = 25 °C; VA+, VD+ = 5V; Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20pF) Notes: 6. Data must be held for sufficient time to bridge 300(50) ns transition time of SCK/SCL. 7. CDOUT should NOT be sampled during this time period. 8. REQ will only go HIGH if there is no data in SCPOUT at the rising edge of SCL/SCK during a READ operation as shown. DSP frequency is 20 MHz. Pull-up resistor is 2 kW . CL = 20 pF. 9. If REQ went HIGH as indicated in note 7, then REQ will hold high at least until the next rising edge of SCK/SCL. If data is in SCPOUT at this time REQ will go active LOW again. This condition should be treated as a new READ process. Address and R/W bit should be sent again. Parameter Symbol Min Max Units SPI Mode (CS = 0) SCK/SCL Clock Frequency (slow mode) (fast mode) fsck fsck 350 2000 kHz CS Falling to SCK/SCL Rising (slow mode) tcss 20 - ns Rise Time of Both CDIN and SCK/SCL Lines (slow mode) tr -5 0 n s Fall Time of Both CDIN and SCK/SCL Lines (slow mode) (fast mode) tf tf 300 ns ns SCK/SCL Low Time (slow mode) (fast mode) tscl tscl 1100 150 ns ns SCK/SCL High Time (slow mode) (fast mode) tsch tsch 1100 150 ns ns Setup Time CDIN to SCK/SCL Rising (slow mode) (fast mode) tcdisu 250 ns ns Hold Time SCK/SCL Rising to CDIN (Note 6) tcdih 50 - ns Transition Time from SCK/SCL to CDOUT Valid (Note 7) tscdov -4 0 n s Time from SCK/SCL Rising to REQ Rising (Note 7) tscrh -2 0 0 n s Rise Time for REQ (Note 8) trr -5 0 n s Fall Time for REQ (Note 9) trf -2 0 n s Hold Time for REQ from SCK/SCL Rising (Note 9) tscrl 0- n s Time from SCK/SCL Falling to CS Rising tsccsh 20 - ns High Time Between Active CS tcsht 200 - ns
Figure 2. SPI Control Port Timing
SWITCHING CHARACTERISTICS - CONTROL PORT (I 2C MODE) (TA = 25 °C; VA+, VD+ = 5V; Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20pF) Notes: 10. Use of I2C â bus compatible interface requires a license from Philips. 11. Data must be held for sufficient time to bridge the 300ns transition time of SCK/SCL. 12. This rise time is shorter than the I 2C specifications recommend, please refer to the section on SCP communications for more information. 13. REQ will only go HIGH if there is no data in the SCPOUT register at the rising edge of SCL/SCK during a READ operation as shown. DSP frequency is 20 MHz. Pull-up resistor is 2 kW CL = 20pF. 14. if REQ went HIGH as indicated in Note 13 then REQ will hold HIGH at least until the next rising edge of SCK/SCL. If data is in the SCPOUT register at this time REQ will go active LOW again. This condition should be treated as a new READ process. The address and R/W should be sent again following a new START condition. Parameter Symbol Min Max Units I2C â Mode (CS=1) (Note 10) SCK/SCL Clock Frequency (slow mode) (fast mode) fscl 100 400 kHz Bus Free Time Between Transmissions tbuf 4.7 ms Start Condition Hold Time (prior to first clock pulse) thdst 4.0 ms Clock Low Time slow fast tlow 4.7 1.2 ms Clock High Time slow fast thigh 4.0 1.0 ms SDA Setup Time to SCK/SCL Rising tsud 250 ns SDA Hold Time from SCK/SCL Falling (Note 11) thdd 0 ms Rise Time of Both SDA and SCK/SCL (Note 12) tr 50 ns Fall Time of Both SDA and SCK/SCL tf 300 ns Time from SCK/SCL Falling to CS4920 ACK tsca 40 ns Time from SCK/SCL Falling to SDA Valid During READ Operation tscsdv 40 ns Time from SCK/SCL Rising to REQ Rising (Note 13) tscrh 200 ns Hold Time for REQ from SCK/SCL Rising (Note 14) tscrl 0n s Rise Time for REQ (Note 13) trr 50 ns Fall Time for REQ (Note 14) trf 20 ns Setup Time for Stop Condition tsusp 4.7 ms
Figure 3. I2C ® Control Port Timing
edge is selectable in setting the EDG bit in the ASICN register. The diagram is for EDG = 1. Figure 4. Serial Audio Port Timing
Notes: 16. Fs determined by clock input rate and configuration of on-chip PLL.
- AUXCLK frequency selectable @ 32, 64, or 128 Fs via AUXCN register bits 1:0.
Figure 5. Auxiliary Audio Port Timing
2 TYPICAL CONNECTION DIAGRAM
27 MHz
Figure 6. Typical Connection Diagram
3 THEORY OF OPERATION
3.1 Introduction
The CS4922 is a complete audio subsystem on a chip. It consists of a general-purpose Digital Signal Processor (DSP), and a number of supplementary analog and digital blocks. These supplementary blocks include a PLL clock multiplier, a serial au- dio input port, an auxiliary serial audio port, a CD quality stereo Digital-to-Analog Converter (DAC), an AES/EBU - S/PDIF compatible digital audio transmitter, and a serial control port. Figure 6 shows a typical connection diagram for the CS4922 in which a micro controller is used for loading the program code. The CS4922 is RAM based audio decoder that can be used to process compressed digital audio sig- nals. Serial audio data broadcast on networks such as cable TV, direct broadcast satellite TV, or the telephone system can be decompressed and con- verted to standard analog and digital signals. A wide variety of standard and proprietary decom- pression algorithms can be supported. CS4922 application code is available which per- forms industry standard MPEG 1 and 2, layers I and II. Application code is also available for G.729A decode. The DSP has a 24-bit fixed point data path, 5K words of program RAM, and 3K words of data RAM. The execution unit includes a 48-bit accu- mulator. The DSP can provide up to 12 MIPS. Either compressed digital audio data or PCM data can be delivered. For analog reproduction of the digital input, a ste- reo DAC using delta-sigma architecture is built-in. Switched-capacitor filters perform most of the re- construction process. Only a simple external pas- sive filter is needed to complete reconstruction. In addition to the analog output, an AES/EBU - S/PDIF compatible output is provided. This allows the designer the flexibility of transmitting the audio data in a standard digital format to an external sys- tem. To facilitate the downloading of DSP code to the CS4922, a serial control port, communicating in ei- ther I 2C â or SPI format, is used. This port may also be used during run time to issue control commands to the DSP.
4 PERIPHERALS
Six on-chip peripherals make the audio decoder ideal for decoding broadcast digital audio signals. It has a PLL clock manager, a CD quality DAC, a digital audio transmitter, a three pin serial port for audio data input, a serial bi-directional auxiliary port for digital audio data, and an SPI/I 2C port for serial control information. Each peripheral has I/O mapped data, control, and status registers. Many peripherals can also generate interrupts.
4.1 Clock Manager
The clock manager is primarily a clock multiplier circuit that takes a reference frequency of 27 MHz on CLKIN which is used for deriving internal clocking. At the heart of the clock manager circuit is a PLL (Phase-Locked Loop) circuit. The PLL is configured by software to produce the appropriate DSP Clock for the desired sample rate. All other in- ternal clocks required for the DAC and other pe- ripherals are derived from this root clock. The PLL’s internal VCO requires a capacitor to be connected to the FLT pin (pin 31). The typical val- ue of the FLT capacitor is 0.47 µf, which is suffi- cient for all allowable CLKIN input frequencies. It must be stressed that the best analog performance can only be achieved by placing the capacitor as close as possible to the FLT pin and that the proper layout precautions be taken to avoid noise coupling onto the FLT pin. The CLKOUT pin is a divided version of the DSP clock. A diagram of the CLKOUT generation cir- cuit is shown in Figure 7.
most compressed bit rate clocks.
4.3 Digital to Analog Converter
is attenuated by more than 60 dB. (192Fs) is more than 50 dB below full scale power. Figure 7. CLKOUT Generation Circuit Figure 8. DAC
4.4 Digital Audio Transmitter
available from Crystal’s application note library.
4.5 Audio Serial Input Port
consisting of FSYNC, SCLK, and SDATA. compressed audio data should tie FSYNC to +5V.
4.6 Auxiliary Digital Audio Port
are always configured to operate in the same mode. rising edge of AUXCLK samples AUXIN.
4.7 Serial Control Port
Figure 9. Auxiliary Data Input Formats Figure 10. Auxiliary Data Output Formats
13 shows a block diagram of the port.
4.7.1 I2C Mode
nected to the digital supply. device. SDA is the serial data Input/Output signal. port output SCPOUT register. the section on Rise Time of SCL/SCK. address and a read/write bit (set low for a write). dress bits and read/write bit are still required. Figure 11. Multi-channel Auxiliary Data Formats
other bus activity or the data will be lost. eration is required to read this byte.
4.7.2 Rise Time on SCL/SCK
hold SCL/SCK low while accepting data.
4.7.3 SPI mode
reset is issued to ensure the mode remains SPI. Figure 14. Control Port Timing, I2C ® Read
that the transfer is complete. de-asserted SCK/SCL will not shift the data out. the data out of the register. on the falling edge of SCL/SCK for the last data bit.
4.8 External Flag Pins
The CS4922 has four external flag pins: XF1-XF4. Figure 17. Control Port Timing, SPI Read
host should hold off data delivery until XF1 falls low once again. Please see the documentation for the application code being used in your system for a complete de- scription.
5 BOOT PROCEDURE
The CS4922 is a RAM based audio decoder. Con- sequently, program and data RAM must be loaded from external memory after power up or any other time a new program needs to be downloaded. Dur- ing the loading procedure (boot), data is transferred through the serial control port to program and data memory. This procedure is controlled by a pro- gram stored internally in ROM. The boot procedure is initiated by a low to high transition of the reset (RESET ) pin with the BOOT pin high. This initializes the program counter to lo- cation 1000 H , the first location in ROM which pre- pares the CS4922 for download. After the ROM program transfers data from the control port to memory, it internally issues a software reset. The software reset clears all registers and transfers con- trol to the application now resident in RAM. A hardware reset (RESET pin toggled low) with the BOOT pin low has the same effect as a software reset. The CS4922 will boot from a micro controller us- ing the serial control port. When booting, it can communicate in an I 2C or SPI format. If the CS (chip select) pin is high when boot is initiated, the port will communicate in I 2C format. If the CS pin is low when boot is initiated, the port will commu- nicate in SPI. Please refer to the timing require- ments found at the beginning of this document. Nodes in an I 2C network have unique network ad- dresses. A message in an I2C network consists of the address of the node receiving the message fol- lowed by the message data. When the control port is configured for I 2C format, it normally compares the address to an address stored in an internal reg- ister. During the boot procedure, the control port is programmed to ignore the address. The SCP sec- tion on I 2C operation explains the mechanics of writing to the CS4922. The boot program in internal ROM expects data transferred through the control port to adhere to a proprietary download image format. The download image always concludes with two bytes containing FF and three bytes containing a check sum. The check sum is generated by summing all the previ- ous data, address, and length bytes and truncating to 24 bits. During download, the CS4922 generates a check- sum on the download image as it is received. This check sum is compared to the value found at the tail of the download image. If they do not match, the REQ (request) pin is pulled low and the processor does not issue the software reset. It stays in a loop until boot is initiated again. If the download image format is corrupted to the point that the CS4922 does not know which bytes represent the check sum, then REQ will not drop to indicate download failure. This should never hap- pen in a stable system. During initial system testing we recommend down- loading an image that has only the check sum cor- rupted (the final 3 bytes). If REQ drops after the complete application code image has been trans- ferred, then the download procedure is functioning properly. If REQ does not drop, then there is a problem with the download procedure.
6 POWER SUPPLY AND GROUNDING
ground plane as illustrated in Figures 18 and 19. tion across the ground split as shown in Figure 18. A separate power plane for the chip is preferable. face-mount socket and surface mount capacitors. device which, in this case, is the socket boundary. Figure 18. CS4922 Suggested Layout
Figure 19. CS4922 Surface Mount Decoupling Layout
7 DAC FILTER RESPONSE PLOTS
frequency. Fs is also the FSYNC frequency. Figure 20. DAC Frequency Response Figure 21. DAC Phase Response Figure 22. DAC Transition Band Figure 23. DAC Passband Ripple
8 PIN DESCRIPTIONS
VD1, VD2, VD3, VD4 - Positive Digital Power Supply, PINS 7, 17, 25, 43. The +5V supply is connected to these pins to power the various digital subcircuits on the chip. See decoupling section in this data sheet for decoupling recommendations. DGND1, DGND2, DGND3, DGND4 - Digital Ground, PINS 6, 18, 26, 42. Digital power supply ground. V A+ - Positive Analog Power Supply, PIN 34. The analog +5V supply for the analog-to-digital converter and the PLL. Analog performance is highly dependent on the quality of this supply. See decoupling section in this data sheet for decoupling recommendations. AGND1, AGND2 - Analog Ground, PIN 33, 36. Analog power supply ground. top view 18 20 22 24 26 28 12464 0 4244 17 29 CDIN CSSCK/SCL REQ SDA/CDOUT TX DGND1 VD1 AUXOUT AUXIN AUXLR AUXCLK DBCLK DBDA XF4 XF3 XF2 VD2 DGND2 90_CLK XF1 SDATA SCLK VD4 DGND4 RESET BOOT AOUTR AOUTL AOUTM AGND2 NC VA+ AGND1 NC FLT PIO EXTCK ALTCLK CLKIN DGND3 VD3 CLKOUT FSYNC CS4922
Digital-to-Analog Converter AOUTL, AOUTR - Analog Outputs, Left and Right Channels, PINS 38, 39. These DAC outputs are centered at approximately 2.2V . An external filter is required to diminish out-of-band noise. See Typical Connection Diagram, Figure 1. AOUTM - Mono Analog Output, PIN 37. Mono is the summation of AOUTL and AOUTR. Mono output is 180° out-of-phase with the sum of AOUTL and AOUTR. Mono is centered at approximately 2.2V . An external filter is required to diminish out-of-band noise. See Typical Connection Diagram, Figure 1. Serial Audio Port FSYNC - Frame Synchronization Clock Input, PIN 23. When SCLK and SDATA are used for delivering compressed data to the CS4922 (e.g. the MPEG application code), the FSYNC pin should be tied to the +5V supply. When SCLK and SDATA are used for delivering PCM data (e.g. the G .729A application code), FSYNC transitions delineate left and right audio data, or the start of a data frame. SCLK - Serial Clock Input, PIN 22. SCLK is used to clock the serial audio data on SDATA into the device. The active edge of SCLK is determined by the application code running on the CS4922. SDATA - Serial Audio Data Input, PIN 21. SDATA is an audio data input pin for the CS4922. The data is clocked in on the active edge of SCLK. Digital Audio Transmitter TX - Transmitter Output, PIN 5. Biphase mark encoded data is output at logic levels from the TX pin. This output typically connects to the input of an RS-422 or optical transmitter. With additional external circuitry, the port can support either AES/EBU or S/PDIF formats. Clock Manager CLKOUT - Clock Output, PIN 24. CLKOUT can be used to synchronize peripheral devices such as a micro controller or an audio source. The clock frequency is determined by a divide by Q in the clock manager. The maximum CLKOUT frequency is the maximum DSP frequency divided by 2. ALTCLK - Clock Input, PIN 28. When EXTCK is high, ALTCLK is an input for an externally generated clock. This clock directly becomes the DSP clock and the clock frequency should be 512Fs or 768Fs.
EXTCK - External Clock Select, PIN 29. Setting EXTCK high allows ALTCLK to be used as an input for an external VCO. Setting EXTCK low disables ALTCLK. Note that EXTCK should be tied directly to either digital power or ground for proper operation. FLT - PLL Filter, PIN 31. A capacitor (typically 0.47 mF) connected to this pin filters the control voltage for the on-chip VCO. Trace length should be minimized to the pin. CLKIN - Clock Input, PIN 27. The 27 MHz clock input to the CLKIN is used to synchronize the PLL' s. It is typical for SCLK for the audio data and CLKIN to be derived from the same clock source to avoid asynchronous noise between the audio source and the DSP. 90_CLK - Optional SCR/PCR 33-Bit Counter Clock, PIN 19 The 90_CLK pin is an input clock signal (typically 90 kHz) which is used to clock the internal 33-bit counter. The 33-bit counter' s clock source is set to 90_CLK when DIV = 0 in the CM0 register. Otherwise when DIV = 1, the 33-bit counter will be clocked by CLKIN ‚ 300. Control DBCLK, DBDA - Debug Port, PINS 12, 13. It is required that a pull-up be used (typically 2.2 kW ) on pin 13. RESET - PIN 41. The CS4922 enters a reset state while RESET is low. When in reset condition, all internal registers are set to 0, the digital audio transmitter, serial control port, and ALTCLK pin are disabled, and the stereo DAC is muted. Normal operation is resumed one internal clock cycle after the rising edge of RESET BOOT - PIN 40. Boot enable pin. Pin must be set high to initiate the download of a program. While BOOT is high, RESET must be toggled high. This starts the internal boot program. XF1, XF2, XF3, XF4 - External Flags, PINS 20, 16, 15, 14. The XF pins are software controllable outputs via the LINT register. These pins are open drain so an external pullup is required (typically 2.2 kW ) for proper operation of the pins. PIO - PIN 30. This pin should be grounded through a 10 kW resistor in normal operation.
REQ - Request Output, PIN 3. This pin is driven low when the DSP needs servicing from an external device. A write to the SCPOUT will cause the REQ to go low. A pull-up resistor is required for proper operation (2.2kW is typical). CS - Chip Select Input, PIN 44. In SPI format, all communication between the host and the CS4922 is initiated when the host drives the CS pin low. This pin also serves as the communication format select during a reset or power up. When CS is high during a reset or power up the SCP will be configured in I2C ® mode. When low, it is configured in SPI mode. The mode is selectable in software by setting the M0 bit in the SCPCN. SCK/SCL - Serial Clock Input, PIN 2. SCK/SCL clocks data into or out of the serial control port. This is always driven by an external device because the CS4922 always operates in slave mode. SDA/CDOUT - Serial Data I/O / Control Data Output, PIN 4. In SPI mode, CDOUT is a data output for the serial control data. In I 2C interface mode, SDA is a bi-directional data I/O. It is required that a pull-up be used (2.2 kW is typical in I2C mode). CDIN - Control Data Input, PIN 1. In SPI mode, CDIN is the data input for the serial control port. It has no function in I2C mode. The pin should be connected to either digital power or ground when the CS4922 is used in I2C systems. Auxiliary Digital Audio Port AUXLR - Auxiliary Sample Clock, PIN 10. This output signal determines which channel is currently being input on the AUXIN pin or output on the AUXOUT pin. It is also the sample clock, Fs. AUXIN - Auxiliary Data Input, PIN 9. Two’s complement MSB first serial data is input on this pin. The data is clocked by AUXCLK and the channnel is determined by AUXLR. AUXOUT - Auxiliary Data Output, PIN 8. Two’s complement MSB first serial data is output on this pin. The data is clocked by AUXCLK and the channel is determined by AUXLR. AUXCLK - Auxiliary Serial Clock Output, PIN 11. This is the auxiliary audio port serial clock output. This output is used to clock data in on the AUXIN pin and shift data out on the AUXOUT pin. Its frequency is selectable in software.
9 PARAMETER DEFINITIONS
The number of bits in the input words to the DACs. Differential Nonlinearity The worst case deviation from the ideal codewidth; expressed in LSBs. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. Instantaneous Dynamic Range The Signal-to-(Noise + Distortion) ratio (S/(N+D)) with a 1 kHz, -60 dB from full scale DAC input signal, with 60 dB added to compensate for the small signal. Use of a small signal reduces the harmonic distortion components of the noise to insignificant levels. Units are in dB. Interchannel Isolation The amount of 1kHz signal present on the output of the grounded input channel with 1 kHz, 0dB signal present on the other channel. Units are in dB. Interchannel Gain Mismatch The difference in output voltages for each channel with a full scale digital input. Units are in dB. Frequency Response Worst case variation in output signal level versus frequency over 10 Hz to 20 kHz. Units in dB. Out of Band Energy The ratio of the rms sum of the energy from 0.46·Fs to 2.1·Fs compared to the rms full-scale signal value. Tested with 48 kHz Fs giving a out-of-band energy range of 22 kHz to 100 kHz.
10 PACKAGE DIMENSIONS
A 0.165 0.180 4.043 4.572 A1 0.090 0.120 2.205 3.048 B 0.013 0.021 0.319 0.533 D 0.685 0.695 16.783 17.653 D1 0.650 0.656 15.925 16.662 D2 0.590 0.630 14.455 16.002 E 0.685 0.695 16.783 17.653 E1 0.650 0.656 15.925 16.662 E2 0.590 0.630 14.455 16.002 e 0.040 0.060 0.980 1.524 JEDEC # : MS-018 44L PLCC PACKAGE DRAWING D E1 E D2/E2 B e A
- Notes •