CS48AU2B

CS48AU2B CIRRUS | Alldatasheet

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Copyright 2009 Cirrus Logic MAY ’09 CONFIDENTIAL DS876F3http://www.cirrus.com CS48AU2B Data Sheet CONFIDENTI AL DRA FT DELPHI

FEATURES

‰ World’s first cost-effective, high-performance 32-bit DSP that is solely dedicated to enable Audyssey Laboratories audio processing technologies for today’s high-volume consumer electronic products ‰ Features: Audyssey Dynamic VolumeTM, Audyssey Dynamic EQTM, Audyssey EQTM & Audyssey BassXTTM/BassXT-TVTM ‰ Audyssey Dynamic Volume eliminates the need for constant volume adjustments ‰ Audyssey Dynamic EQ enables a reference playback experience at any desired playback level ‰ Audyssey EQ removes much of the distortion caused by speaker enclosures and the typical room environment producing greatly improved sound compared to similar products without correction ‰ Audyssey BassXT and BassXT-TV are specifically calibrated to enhance the physical bass response of each product model ‰ Configurable Serial Audio Inputs/Outputs — Maximum 32-bit @ 192 kHz (Note: Audyssey Laboratories algorithms support 48 kHz, 44.1 kHz and 32 kHz) — Integrated 192 kHz capable S/PDIF transmitter ‰ Integrated Clock Manager/PLL — Can operate from ex ternal crystal, external oscillator ‰ Input Fs Auto Detection & Coefficient Loading ‰ Host Control & Boot via Serial Interface ‰ Support for Master (Self) Boot via Serial EEPROM for single Fs applications (i.e. 48 kHz only via ADC input) ‰ Configurable GPIOs and External Interrupt Input ‰ 1.8V Core and a 3.3V I/O that is tolerant to 5V input ‰ Low-power Mode —“ Energy Star® Ready” via low-power mode, 268 µW in standby 32-bit DSP D M A P X Y Serial Control 1 Multichannel Audio Out GPIO Debug Watchdog TMR1 TMR2 PLL S/PDIF Multichannel Audio In The brand new CS48AU2B device is still based on the same high-performance 32-bit fixed point Digital Signal Processor core but instead is equipped with much less memory, tailoring it for more cost-effective applications which feature Audyssey Laboratories audio processing technologies. Target applications are: — Digital Televisions —i P o d ® Docking Stations — Automotive Head Units (OEM and Aftermarket) — Automotive Outboard Amplifiers (OEM and Aftermarket) —B l u - r a y ® Disc Receivers — Soundbars / Sound Projectors The following Audyssey Laboratories algorithms are currently supported on the CS48AU2B and more are in development: While the individual Audyssey processing algorithms have already been implemented on this DSP, the CS48AU2B is programmed using the Cirrus proprietary DSP Composer ™ GUI development tool. Processing chains combining both standard signal processing blocks (Tone Control, Bass Management, etc.) in combination with any combination of Audyssey Laboratories technology algorithm blocks may be designed using a simple drag-and-drop interface to create a custom signal flow specific to your product model. The end result of this is a software image that is down-loaded to the DSP via serial host 2C® or SPITM ) or via a serial master (self) boot. Support for loading of the various Audyssey Laboratories algorithm coefficient files supplied by Audyssey Laboratories is easily supported via DSP Composer, enabling the OEM/ODM to quickly be able to generate the necessary files for the system microcontroller which have been custom tailored for each specific model based on the measurement and analysis performed by Audyssey Laboratories. Ordering Information: See page 21 for ordering information

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Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the info rmation contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVO LVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVER E PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Audyssey, the Audyssey stylized logo and font, Audyssey Dynamic Volume, Audyssey Dynamic EQ, Audyssey EQ, and Audyssey BassXT ( implementations for both HTIB and TV) are either trademarks or registered trademarks of Aud yssey Laboratories. Sale of the CS48AU2B is only authorized to licensees of Audysse y Laboratories deemed to be in good standing. SPI is a trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductor. iPod is a registered trademark of Apple Computer, Inc. Blu-ray and Blu-ray Disc are trademarks of SONY KABUSHIKI KAISHA CORPORATION. Energy Star is a registered trademark of the Environmental Protection Agency, a federal agency of the United States government.

Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology DS876F3 Copyright 2009 Cirrus Logic 3 CONFIDENTIAL CONFIDENTI AL DRA FT DELP HI Table of Contents

5.11 Switching Characteristics — Serial Control Port - I

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programmer, and the quality control engineer. applications for this device.

2.1 Licensing

Table 1. CS48AU2B Related Documentation API information for the operating system. information for the GUI development tool.

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1. Code Overlays The suite of software available for the CS48AU2B consists of an operating system (OS) and a library of overlays. The overlays have been divided into three main groups called Matrix-processors, Virtualizer-processors, and Post-processors. All software components are defined below: 1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, error concealment, etc. 2. Matrix-processor- Any Module that performs a matrix decode on PCM data to produce more output channels than input channels (2Ön channels). Generally speaking, these modules increase the number of valid channels in the audio I/O buffer. 3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input channels (nÖ2 channels) with the effect of providing “phantom” speakers to represent the physical audio channels that were eliminated. Generally speaking, these modules reduce the number of valid channels in the audio I/O buffer. 4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the matrix- or virtualizer-processors. Examples are bass management, audio manager, tone control, Audyssey Dynamic Volume, Audyssey Dynamic EQ, Audyssey EQ, Audyssey BassXT, delay, & customer-specific effects, etc. The certified DSP firmware or application codes provided by Cirrus Logic (under a licensed to you from Audyssey Laboratories) may enable some or all of the Audyssey Laboratories algorithms. These licensed processing blocks can be used in combination with a host standard post-processing signal blocks (tone control, Bass Management, delays, etc.) or lower level primitives such as a filter or math function. A product-specific signal flow is generated by the designer using DSP Composer. Once all of the custom coefficient files supplied by Audyssey Laboratories have been loaded and the signal flow has been set, the user can perform a “generate deliverables” inside DSP Composer. This generates a collection of files that can be easily converted to .c or .h files by the designer for storage inside the host controller OR can be converted into a small image that can either be stored in an external serial FLASH/EEPROM, or downloaded via a host controller through the SPI™ /I2C® serial port. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not need to be reloaded — only the new matrix-processor (the same is true for the other overlays). Table 2 below lists the firmware available based on device selection. Please refer to AN298, CS485xx Firmware User’s Manual for the latest listing of application codes and Cirrus Framework modules available.

1. Hardware Functional Description

4.1 DSP Core

The CS48AU2B DSP is a single-core DSP with separate X and Y data and P code memory spaces. has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers. the CS48AU2B from a host controller or external serial FLASH/EEPROM. from the DSPs on-board ROM, or custom firmware can be downloaded through the SCP .

4.1.1 DSP Memory

memory for post-processing applications. equal in size, or more memory can be allocated for Y-RAM in 2kword blocks.

4.1.2 DMA Controller

each DMA channel, as well as up to 6 interrupt events, are programmable. Table 2. Device and Firmware Selection Guide

8 Channel Car Audio

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4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz. Up to 32-bit word lengths are supported. The DAI also supports a time division multiplexed (TDM) one-line data mode, that packs PCM audio on a single data line the total number possible depends on the ratio of SCLK to LRCLK. The CS48AU2B supports up to 8. The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, off-loading the task of monitoring the SPDIF receiver from the host. A time- stamping feature allows the input data to be sample-rate converted via software.

4.2.2 Digital Audio Output Port (DAO)

DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP , or as a clock slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can be re-configured as a SPDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with embedded clock on a single line). The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple channels of PCM audio on a single data line.

4.2.3 Serial Control Port (I

2C® or SPI™ ) The on-chip serial control port is capable of operating as master or slave in either SPI™ or I 2C® modes. Master/Slave operation is chosen by mode select pins when the CS48AU2B comes out of Reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be ≤ (Fdclk/2)). The CS48AU2B serial control port also includes a pin for flow control of the communications interface (SCP_BSY) and a pin to indicate when the DSP has a message for the host (SCP_IRQ).

4.2.4 GPIO

Many of the CS48AU2B peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.

4.2.5 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS48AU2B defaults to running from the external reference frequency and is switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.

4.2.6 Hardware Watchdog Timer

The CS48AU2B has an integrated watchdog timer that acts as a “health” monitor for the DSP . The watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS48AU2B will reset itself in the event of a temporary system failure. In stand-alone mode (that is, no host MCU), the DSP will reboot from external FLASH. In slave mode

Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology DS876F3 Copyright 2009 Cirrus Logic 9 CONFIDENTIAL CONFIDENTI AL DRA FT DELP HI (that is, host MCU present) a GPIO will be used to signal the host that the watchdog has expired and the DSP should be rebooted and re-configured.

4.3 DSP I/O Description

4.3.1 Multiplexed Pins

Many of the CS48AU2B pins are multi-functional. For details on pin functionality please refer to the CS485xx Hardware User’s Manual.

4.3.2 Termination Requirements

Open-drain pins on the CS48AU2B must be pulled high for proper operation. Please refer to the CS485xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins in the CS48AU2B are used to select the boot mode upon the rising edge from reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS485xx Hardware User’s Manual.

4.3.3 Pads

The CS48AU2B I/Os operate from the 3.3 V supply and are 5 V tolerant.

4.4 Application Code Security

The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. Please contact your local Cirrus representative for details.

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1. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C, CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.

5.1 Absolute Maximum Ratings

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V) Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

5.2 Recommended Operating Conditions

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V) Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.

5.3 Digital DC Characteristics

(Measurements performed under static conditions.) Parameter Symbol Min Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDDIO| VDD VDDA VDDIO -0.3 -0.3 -0.3 2.0 3.6 3.6 0.3 V V V V Input pin current, any pin except supplies I in -+ / - 1 0 m A Input voltage on PLL_REF_RES V filt -0.3 3.6 V Input voltage on I/O pins V inio -0.3 5.0 V Storage temperature T stg -65 150 °C Parameter Symbol Min Typ Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDDIO| VDD VDDA VDDIO 1.71 3.13 3.13 1.8 3.3 3.3 1.89 3.46 3.46 V V V V Ambient operating temperature - CQZ - DQZ T A -40 +70 +85 Parameter Symbol Min Typ Max Unit High-level input voltage V IH 2.0 - - V Low-level input voltage, except XTI V IL -- 0 . 8V Low-level input voltage, XTI V ILXTI -- 0 . 6V Input Hysteresis V hys 0.4 V High-level output voltage (IO = -2mA), except XTI V OH VDDIO * 0.9 - - V Low-level output voltage (IO = 2mA), except XTI V OL - - VDDIO * 0.1 V Input leakage XTI I LXTI --5 μA Input leakage current (all digital pins with internal pull-up resistors enabled) ILEAK -- 7 0 μA

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5.4 Power Supply Characteristics

(Measurements performed under operating conditions)

5.5 Thermal Data (48-Pin LQFP)

1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm th ick FR-4 material with 1-oz. copper covering 20 % of the top & bottom layers. 2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top & bottom layers and 0.5-oz. copper covering 90 % of the internal power plane & ground plane layers. 3. To calculate the die temperature for a given power dissipation Tj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ] 4. To calculate the case temperature for a given power dissipation Tc = Tj - [ (Power Dissipation in Watts) * ψjt ] Parameter Min Typ Max Unit Operational Power Supply Current: VDD: Core and I/O operating1 VDDA: PLL operating VDDIO: With most ports operating Total Operational Power Dissipation: Standby Power Supply Current: VDD: Core and I/O not clocked VDDA: PLL halted VDDIO: All connected I/O pins 3-stated by other ICs in system Total Standby Power Dissipation: 1. Dependent on application firmware and DSP clock speed. 203 480 100 348 mA mA mA mW μA μA μA μW Parameter Symbol Min Typ Max Unit Junction Temperature T j - - 125 °C Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 θja - 63.5 °C / Watt Thermal Resistance (Junction to Top of Package) Two-layer Board3 Four-layer Board4 ψjt - 0.70 0.64 °C / Watt

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5.6 Switching Characteristics— RESET

Figure 1. RESET Timing

5.7 Switching Characteristics — XTI

Figure 2. XTI Timing

1. C L refers to the total load capacitance as specified by the crystal manufacturer. Crystals that require a CL outside this range should

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5.8 Switching Characteristics — Internal Clock

Parameter Symbol Min Max Unit Internal DCLK frequency1 CS48AU2B-CQZ 1. After initial power-on reset, F dclk = Fxtal. After initial kickstart commands, the PLL is locked to max F dclk and remains locked until the next power-on reset. Fdclk - Fxtal 150 MHz Internal DCLK period1 CS48AU2B-CQZ DCLKP - 6.7 1/F xtal ns

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5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode . Figure 3. Serial Control Port - SPI Slave Mode Timing

1. The specification f spisck indicates the maximum speed of the hardware. The system designer should be aware that the actual

should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is F xtal/3.

5.10 Switching Characteristics — Se rial Control Port - SPI Master Mode

Figure 4. Serial Control Port - SPI Master Mode Timing

1. The specification f spisck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application.

1. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter

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5.11 Switching Characteristics — Serial Control Port - I 2C Slave Mode

Figure 5. Serial Control Port - I2C Slave Mode Timing

1. The specification f iicck indicates the maximum speed of the hardware. The system designer should be aware that the actual

should be implemented to prevent overflow of the input data buffer.

5.12 Switching Characteristics — Serial Control Port - I 2C Master Mode

Figure 6. Serial Control Port - I2C Master Mode Timing

1. The specification f iicck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application.

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5.13 Switching Characteristics — Digital Audio Slave Input Port

Figure 7. Digital Audio Input (DAI) Port Timing Diagram

5.14 Switching Characteristics — DSD Slave Input Port

Figure 8. Direct Stream Digital - Serial Audio Input Timing

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5.15 Switching Characteristics — Digital Audio Output Port

Parameter Symbol Min Max Unit DAO_MCLK period T daomclk 40 - ns DAO_MCLK duty cycle - 45 55 % DAO_SCLK period for Master or Slave mode 1. Master mode timing specifications ar e characterized, not production tested. Tdaosclk 40 - ns DAO_SCLK duty cycle for Master or Slave mode1 -4 06 0 % Master Mode (Output A1 Mode)1,2 2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_LRCLK. DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input tdaomsck -1 9 n s DAO_LRCLK delay from DAO_SCLK transition, respectively3 3. This timing parameter is defined from the non-active edge of DAO_ SCLK. The active edge of DAO_SCLK is the point at which the data is valid. tdaomstlr -8 n s DAO_SCLK delay from DAO_LRCLK transition, respectively3 tdaomlrts -8 n s DAO1_DATA[3..0], DAO2_DATA[1..0] delay from DAO_SCLK transition3 tdaomdv -1 0 n s Slave Mode (Output A0 Mode)4 4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source. DAO1_DATA[3..0], DAO2_DATA[1..0] delay from DAO_SCLK transition3 tdaosdv -1 5 n s DAO_LRCLK delay from DAO_SCLK transition, respectively3 tdaosstlr -3 0 n s DAO_SCLK delay from DAO_LRCLK transition, respectively3 tdaoslrts -1 5 n s DAO_MCLK DAO_SCLK DAO_LRCLK DAOn_DATAn tdaomlclk tdaomsck tdaomdv tdaomlrts DAO_MCLK DAO_SCLK DAO_LRCLK DAOn_DATAn tdaomclk tdaomsck tdaomstlr Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK

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Figure 9. Digital Audio Output Port Timing, Master Mode Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)

NOTE: Please contact the factory for availability of the -D (automotive grade) package. Table 3. Ordering Information

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1. Environmental, Manufacturing, & Handling Information

• MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Table 4. Environmental, Manufacturing, & Handling Information

8.1 CS48AU2B, 48-pin LQFP Pinout Diagram

Figure 11. CS48AU2B, 48-Pin LQFP Pinout

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1. Package Mechanical Drawings

Figure 12. 48-Pin LQFP Package Drawing 2) All dimensions are in millimeters and controlling dimension is in millimeters. 4) Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.

Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology DS876F3 Copyright 2009 Cirrus Logic 25 CONFIDENTIAL CONFIDENTI AL DRA FT DELP HI 10. Revision History Revision Date Changes F1 December 2, 2008 Initial Release F2 February 16, 2009 Updated Section 5.5, adding Junction Temperature specification. F3 May 27, 2009 Updated Note 1 in Section 5.7.

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