CS48520-CQZ

CS485XX CIRRUS | Alldatasheet

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Copyright 2009 Cirrus Logic, Inc. FEB ’09 CONFIDENTIAL DS734F3http://www.cirrus.com CS485xx Family Data Sheet CONFIDENTI AL DRA FT DELPHI

FEATURES

‰ Cost-effective, High-performance 32-bit DSP — 300,000,000 MAC/S (multiply accumulates per second) — Dual MAC cycles per clock — 72-bit accumulators are the most accurate in the industry — 24k x 32 SRAM, 2k blocks - assignable to data or program — Internal ROM contains a variety of configurable sound enhancement feature sets — 8-channel internal DMA — Internal watch-dog DSP lock-up prevention ‰ DSP Tool Set w/ Private Keys for Protecting Customer IP ‰ Configurable Serial Audio Inputs/Outputs — Configurable for all input/output types — Maximum 32-bit @ 192 kHz — Supports 32-bit audio sample I/O between DSP chips — TDM input modes (multiple channels on same line) — 192 kHz SPDIF transmitter — Multi-channel DSD direct stream digital SACD input ‰ Supports Two Different Input Fs Sample Rates — Output can be master or slave — Dual processing path capability — Input supports dual domain slave clocking — Hardware assist time sampling for sample rate conversion ‰ Integrated Clock Manager/PLL — Can operate from ex ternal crystal, external oscillator ‰ Input Fs Auto Detection ‰ Host & Boot via Serial Interface ‰ Configurable GPIOs and External Interrupt Input ‰ 1.8V Core and a 3.3V I/O that is tolerant to 5V input ‰ Low-power Mode — “Energy Star ® Ready” in low-power mode, 268 µW in standby 32-bit DSP D M A P X Y Serial Control 1

12 Ch PCM

12 Ch. Audio In / 6 Ch. SACD In Differentiating from the legacy Cirrus multi-standard, multi- channel decoders, this new CS485xx family is still based on the same high-performance 32-bit fixed point Digital Signal Processor core but instead is equipped with much less memory, tailoring it for more cost-effective applications associated with multi-channel and virtual-channel sound enhancements. Target applications are: — Digital Televisions — Multimedia Peripherals —i P o d ® Docking Stations — Automotive Head Units — Automotive Outboard Amplifiers — HD-DVD & Blu-ray Disc DVD Receivers — PC Speakers There are are also a wide variety of licensable DSP codes available today as seen by the following examples: Cirrus also has developed, or is developing their own royalty- free versions of popular features sets like Cirrus Bass Manager, Cirrus Dynamic Volume Leveler, Cirrus Original Multichannel Surround, Cirrus Virtual Speaker & Cirrus 3D- Audio. The CS485xx family is programmed using the Cirrus proprietary DSP Composer ™ GUI development tool. Processing chains may be designed using a drag-and-drop interface to place/utilize functional macro audio DSP primitives. The end result is a software image that is down- loaded to the DSP via serial host or serial boot modes. Ordering Information: See page 20 for ordering information

32-bit Audio Decoder DSP Family 2 Copyright 2009 Cirrus Logic, Inc. DS734F3 CONFIDENTIAL CONFIDENTI AL DRA FT DELPHI Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant infor- mation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPER- TY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT- NESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEM- NIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Dolby, Dolby Digital, Dolby Headphone, Dolby Virtual Speaker, Dolby Headphone, and Pro Logic are registered trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Lab- oratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Lab- oratories. DTS is a registered trademark of the Digital Theater Systems, Inc. DTS Neo:6 is a trademark of Digital Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final product. SRS, Circle Surround and Trusurround XT are registered trademarks of SRS Labs, Inc. Circle Surround II is a trademark of SRS Labs, Inc. The CIRCLE SURROUND TECHNOLOGY rights incorporated in the Cirrus Logic chip are owned by SRS Labs, Inc. and by Valence Technology Ltd., and licensed to Cirrus Logic, Inc. Users of any Cirrus Logic chip containing enabled CIRCLE SURROUND TECHNOLOGY® (i.e., CIRCLE SURROUND® LICENSEES) must first sign a license to pur- chase production quantities for consumer electronics applications which may be granted upon submission of a preproduction sample to, and the satisfactory passing of performance verification tests performed by SRS Labs, Inc., or Valence Technology Ltd. E-mail requests for performance specifications and testing rate schedule may be made to cslicense@srslabs.com. SRS Labs, Inc. and Valence Technology, Ltd., reserve the right to decline a use license for any submission that does not pass performance specifications or is not in the consumer electronics classification. All equipment manufactured using any Cirrus Logic chip containing enabled CIRCLE SURROUND® TECHNOLOGY must carry the Circle Surround® logo on the front panel in a manner approved in writing by SRS Labs, Inc., or Valence Technology Ltd. If the Circle Surround® logo is printed in users manuals, service manuals or advertisements, it must appear in a form approved in writing by SRS Labs, Inc., or Valence Technology, Ltd. The rear panel of Circle Surround® products, users manuals, service manuals, and all advertising must all carry the legends as described in LICENSOR'S most current version of the CIRCLE SURROUND Trademark Usage Manual. SPI is a trademark of Motorola, Inc. I2C is a registered trademark of Philips Semiconductor. iPod is a registered trademark of Apple Computer, Inc. Energy Star is a registered trademark of the Environmental Protection Agency, a federal agency of the United States government.

32-bit Audio Decoder DSP Family DS734F3 Copyright 2009 Cirrus Logic, Inc. 3 CONFIDENTIAL CONFIDENTI AL DRA FT DELP HI Table of Contents

5.11 Switching Characteristics — Serial Control Port - I

The CS485xx Family Data Sheet describes the CS485xx family of multichannel audio processors. designing a system around the CS485xx family of processors. programmer, and the quality control engineer. refer to Table 2 on page 7 for the input, output, firmware features of each device.

2.1 Licensing

contact your local Cirrus Logic Sales representative for more information. Table 1. CS485xx Family Related Documentation information for the GUI development tool.

32-bit Audio Decoder DSP Family 6 Copyright 2009 Cirrus Logic, Inc. DS734F3 CONFIDENTIAL CONFIDENTI AL DRA FT DELPHI 3. Code Overlays The suite of software available for the CS485xx family consists of an operating system (OS) and a library of overlays. The overlays have been divided into three main groups called Matrix-processors, Virtualizer-processors, and Post-processors. All software components are defined below: 1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, error concealment, etc. 2. Matrix-processor- Any Module that performs a matrix decode on PCM data to produce more output channels than input channels (2Ön channels). Examples are Dolby ProLogic IIx and DTS Neo:6. Generally speaking, these modules increase the number of valid channels in the audio I/O buffer. 3. Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input channels (nÖ2 channels) with the effect of providing “phantom” speakers to represent the physical audio channels that were eliminated. Examples are Dolby Headphone ® and Dolby Virtual Speaker®. Generally speaking, these modules reduce the number of valid channels in the audio I/O buffer. 4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the matrix- or virtualizer-processors. Examples are bass management, audio manager, tone control, EQ, delay, customer-specific effects, etc. The bulk of each overlay is stored in ROM within the CS485xx, but a small image is required to configure the overlays and boot the DSP . This small image can either be stored in an external serial FLASH/EEPROM, or downloaded via a host controller through the SPI™ /I2C® serial port. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new matrix-processor is selected, the OS, virtualizer-, and post-processors do not need to be reloaded — only the new matrix-processor (the same is true for the other overlays). Table 2 below lists the firmware available based on device selection. Please refer AN298, CS485xx Firmware User’s Manual for the latest listing of application codes and Cirrus Framework ™ modules available.

1. Hardware Functional Description

4.1 DSP Core

has eight 72-bit accumulators, four X- and four Y-data registers, and 12 index registers. downloaded to the CS485xx from a host controller or external serial FLASH/EEPROM. from the DSPs on-board ROM, or custom firmware can be downloaded through the SCP . head-ends, automotive amplifiers, and boom boxes.

4.1.1 DSP Memory

memory for post-processing applications. equal in size, or more memory can be allocated for Y-RAM in 2kword blocks. Table 2. Device and Firmware Selection Guide

8 Channel Car Audio

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4.1.2 DMA Controller

The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter: X, Y , and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment controls. The service intervals for each DMA channel, as well as up to 6 interrupt events, are programmable.

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

Each version of the CS485xx supports a different number of input channels. Refer to Table 2 on page 7 for more details. The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz. The port is capable of accepting PCM or DSD formats. Up to 32-bit word lengths are supported. DSD is supported and internally converted to PCM before processing. The DAI also supports a time division multiplexed (TDM) one-line data mode, that packs PCM audio on a single data line (the total number possible depends on the ratio of SCLK to LRCLK and the version of chip. For example on the CS48520 only 4 ch of PCM are supported in one line mode and on the CS48560 up to 8 channels are supported.). The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, off-loading the task of monitoring the SPDIF receiver from the host. A time- stamping feature allows the input data to be sample-rate converted via software.

4.2.2 Digital Audio Output Port (DAO)

Each version of the CS485xx supports a different number of output channels. Refer to Table 2 on page 7 for more details. DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP , or as a clock slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can be re-configured as a SPDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with embedded clock on a single line). The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple channels of PCM audio on a single data line.

4.2.3 Serial Control Port (I

2C® or SPI™ ) The on-chip serial control port is capable of operating as master or slave in either SPI™ or I 2C® modes. Master/Slave operation is chosen by mode select pins when the CS485xx comes out of Reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be ≤ (Fdclk/2)). The CS485xx serial control port also includes a pin for flow control of the communications interface (SCP_BSY ) and a pin to indicate when the DSP has a message for the host (SCP_IRQ).

4.2.4 GPIO

Many of the CS485xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.

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4.2.5 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS485xx defaults to running from the external reference frequency and is switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.

4.2.6 Hardware Watchdog Timer

The CS485xx has an integrated watchdog timer that acts as a “health” monitor for the DSP . The watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS485xx will reset itself in the event of a temporary system failure. In stand-alone mode (that is, no host MCU), the DSP will reboot from external FLASH. In slave mode (that is, host MCU present) a GPIO will be used to signal the host that the watchdog has expired and the DSP should be rebooted and re-configured.

4.3 DSP I/O Description

4.3.1 Multiplexed Pins

Many of the CS485xx family pins are multi-functional. For details on pin functionality please refer to the CS485xx Hardware User’s Manual.

4.3.2 Termination Requirements

Open-drain pins on the CS485xx must be pulled high for proper operation. Please refer to the CS485xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. Mode select pins in the CS485xx family are used to select the boot mode upon the rising edge from reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS485xx Hardware User’s Manual.

4.3.3 Pads

The CS485xx I/Os operate from the 3.3 V supply and are 5 V tolerant.

4.4 Application Code Security

The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. Please contact your local Cirrus representative for details.

32-bit Audio Decoder DSP Family 10 Copyright 2009 Cirrus Logic, Inc. DS734F3 CONFIDENTIAL CONFIDENTI AL DRA FT DELPHI 5. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C, CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.

5.1 Absolute Maximum Ratings

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V) Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

5.2 Recommended Operating Conditions

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0V) Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.

5.3 Digital DC Characteristics

(Measurements performed under static conditions.) Parameter Symbol Min Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDDIO| VDD VDDA VDDIO –0.3 –0.3 –0.3 2.0 3.6 3.6 0.3 V V V V Input pin current, any pin except supplies I in -+ / - 1 0 m A Input voltage on PLL_REF_RES V filt -0.3 3.6 V Input voltage on I/O pins V inio -0.3 5.0 V Storage temperature T stg –65 150 °C Parameter Symbol Min Typ Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDDIO| VDD VDDA VDDIO 1.71 3.13 3.13 1.8 3.3 3.3 1.89 3.46 3.46 V V V V Ambient operating temperature - CQZ - DQZ T A - 40 + 70 + 85 Parameter Symbol Min Typ Max Unit High-level input voltage V IH 2.0 - - V Low-level input voltage, except XTI V IL -- 0 . 8V Low-level input voltage, XTI V ILXTI -- 0 . 6V Input Hysteresis V hys 0.4 V High-level output voltage (IO = -2mA), except XTI V OH VDDIO * 0.9 - - V Low-level output voltage (IO = 2mA), except XTI V OL - - VDDIO * 0.1 V Input leakage XTI I LXTI --5 μA Input leakage current (all digital pins with internal pull-up resistors enabled) ILEAK -- 7 0 μA

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5.4 Power Supply Characteristics

(Measurements performed under operating conditions)

5.5 Thermal Data (48-Pin LQFP)

1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm th ick FR-4 material with 1-oz. copper covering 20 % of the top & bottom layers. 2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20 % of the top & bottom layers and 0.5-oz. copper covering 90 % of the internal power plane & ground plane layers. 3. To calculate the die temperature for a given power dissipation Tj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ] 4. To calculate the case temperature for a given power dissipation Tc = Tj - [ (Power Dissipation in Watts) * ψjt ] Parameter Min Typ Max Unit Operational Power Supply Current: VDD: Core and I/O operating1 VDDA: PLL operating VDDIO: With most ports operating Total Operational Power Dissipation: Standby Power Supply Current: VDD: Core and I/O not clocked VDDA: PLL halted VDDIO: All connected I/O pins 3-stated by other ICs in system Total Standby Power Dissipation: 1. Dependent on application firmware and DSP clock speed. 203 480 100 348 mA mA mA mW μA μA μA μW Parameter Symbol Min Typ Max Unit Junction Temperature T j - - 125 °C Thermal Resistance (Junction to Ambient) Two-layer Board1 Four-layer Board2 θja - 63.5 °C / Watt Thermal Resistance (Junction to Top of Package) Two-layer Board3 Four-layer Board4 ψjt - 0.70 0.64 °C / Watt

5.6 Switching Characteristics— RESET

Figure 1. RESET Timing

5.7 Switching Characteristics — XTI

Figure 2. XTI Timing

1. C L refers to the total load capacitance as specified by the crystal manufacturer. Crystals that require a CL outside this range should

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5.8 Switching Characteristics — Internal Clock

5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode . Parameter Symbol Min Max Unit Internal DCLK frequency1 CS4852x-CQZ CS4854x-CQZ CS4856x-CQZ CS4854x-DQZ CS4856x-DQZ 1. After initial power-on reset, F dclk = Fxtal. After initial kickstart commands, the PLL is locked to max F dclk and remains locked until the next power-on reset. Fdclk - Fxtal Fxtal Fxtal Fxtal Fxtal 150 150 150 150 150 MHz Internal DCLK period CS4852x-CQZ CS4854x-CQZ CS4856x-CQZ CS4854x-DQZ CS4856x-DQZ DCLKP - 6.7 6.7 6.7 6.7 6.7 1/F xtal 1/Fxtal 1/Fxtal 1/Fxtal 1/Fxtal ns Parameter Symbol Min Typical Max Units SCP_CLK frequency1 1. The specification f spisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is F xtal/3. fspisck -2 5 M H z SCP_CS# falling to SCP_CLK rising t spicss 24 - ns SCP_CLK low time t spickl 20 - ns SCP_CLK high time t spickh 20 - ns Setup time SCP_MOSI input t spidsu 5- n s Hold time SCP_MOSI input t spidh 5- n s SCP_CLK low to SCP_MISO output valid t spidov -1 1 n s SCP_CLK falling to SCP_IRQ# rising t spiirqh -2 0 n s SCP_CS# rising to SCP_IRQ# falling t spiirql 0n s SCP_CLK low to SCP_CS# rising t spicsh 24 - ns SCP_CS# rising to SCP_MISO output high-Z t spicsdz -2 0 n s SCP_CLK rising to SCP_BSY# falling t spicbsyl -3 *DCLKP+20 ns

Figure 3. Serial Control Port - SPI Slave Mode Timing

5.10 Switching Characteristics — Se rial Control Port - SPI Master Mode

1. The specification f spisck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application.

1. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter

Figure 4. Serial Control Port - SPI Master Mode Timing

5.11 Switching Characteristics — Serial Control Port - I 2C Slave Mode

1. The specification f iicck indicates the maximum speed of the hardware. The system designer should be aware that the actual

should be implemented to prevent overflow of the input data buffer.

Figure 5. Serial Control Port - I2C Slave Mode Timing

5.12 Switching Characteristics — Serial Control Port - I 2C Master Mode

1. The specification f iicck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application.

Figure 6. Serial Control Port - I2C Master Mode Timing

5.13 Switching Characteristics — Digital Audio Slave Input Port

Figure 7. Digital Audio Input (DAI) Port Timing Diagram

5.14 Switching Characteristics — DSD Slave Input Port

Figure 8. Direct Stream Digital - Serial Audio Input Timing

5.15 Switching Characteristics — Digital Audio Output Port

1. Master mode timing specifications ar e characterized, not production tested.
2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce
3. This timing parameter is defined from the non-active edge of DAO_ SCLK. The active edge of DAO_SCLK is the point at which the
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

NOTE: Please contact the factory for availability of the -D (automotive grade) package. Table 3. Ordering Information

1. Environmental, Manufacturing, & Handling Information

• MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Table 4. Environmental, Manufacturing, & Handling Information

8.1 CS48520, 48-pin LQFP Pinout Diagram

Figure 11. CS48520, 48-Pin LQFP Pinout

8.2 CS48540, 48-pin LQFP Pinout Diagram

Figure 12. CS48540, 48-Pin LQFP Pinout

8.3 CS48560,48-pin LQFP Pinout Diagram

Figure 13. CS48560, 48-Pin LQFP Pinout

1. Package Mechanical Drawings

Figure 14. 48-Pin LQFP Package Drawing 2) All dimensions are in millimeters and controlling dimension is in millimeters. 4) Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.

32-bit Audio Decoder DSP Family 26 Copyright 2009 Cirrus Logic, Inc. DS734F3 CONFIDENTIAL CONFIDENTI AL DRA FT DELPHI 10. Revision History Revision Date Changes A1 JUL 2006 Advance release. A2 JUL 2006 Updated pinout definition for pins 26 and 27. Updated typical power numbers. A3 DEC 5 2006 Updated sections 2.0, 4.2.1, 5.8, Table 3, Table 4, to show new device PP1 MAR 12 2007 Preliminary Release PP2 December 18, 2007 Changed title of data sheet from CS48500 Data Sheet to CS485xx Fam- ily Data Sheet to cover all CS485xx family products. Updated Standby Power specification in Section . Updated DAO timing specifications and timing diagrams in Section 5.15. F1 April 21, 2007 Removed DSD Phase Modulation Mode from Section 5.14. Removed reference to MCLK in Section 5.14. Redefined Master mode clock speed for SCP_CLK in Section 5.10. Redefined DC leakage character- ization data in Section 5.3. Added typical crystal frequency values in Table Footnote 1 under Section 5.7. Modified Footnote 1 under Section 5.9. Modified power supply characteristics in Section 5.4, F2 July 14, 2008 Added reference to support for time division multiplexed (TDM) one-line data mode for DAO port in Section 4.2.2. F3 February 16, 2009 Updated Section 5.5, adding Junction Temperature specification.