CS4811 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
lAudio Processor for embedded reverb/effects applications – Proprietary 24-bit Audio Processing Engine – On-chip RAM (No external RAM required) – On-chip 24-bit ΔΣ ADC with 100 dB Dyn. Range – On-chip 24-bit ΔΣ DAC with 100 dB Dyn. Range – Automatically boots firmware from external serial EEPROM lFirmware available for Guitar Effects or Mixer Effects applications lSingle +5 V Supply l100-pin Metric Quad Flat Pack (MQFP)
Description
The CS4811 is a complete audio effects processing system on a chip. This device integrates a proprietary 24- bit audio processing engine, large on-chip RAM memories, and a high performance 24-bit audio codec. A serial control port allows the device to boot firmware from a compact and low cost SPI or I 2C serial EEPROM. Other features such as single +5 V operation simplify system design. Firmware for the CS4811 is provided by Cirrus Logic. There are two different firmware codes available; one for guitar effects and one for audio mixers. The guitar effects firmware provides a host of electric guitar effects includ- ing spring reverb, delay, chorus, flange and tremolo. The mixer effects firmware provides a suite of effects such as digital reverb, delay and chorus which are suit- able for use in audio mixers, karaoke and acoustic instrument amplifiers. The CDB4811GTR and CDB4811MXR evaluation boards allow easy evaluation of the CS4811 device and the associated firmware. ORDERING INFO CS4811-KM -10 to +70°C 100-pin MQFP CDB4811GTR-01 Guitar Effects Evaluation Board CDB4811MXR-01 Mixer Effects Evaluation Board I CMOUT CMFILT+ CMFILT- AIN+ AIN- XTO XTI CLOCK MANAGER AOUT+ 24-BIT AUDIO VOLTAGE REFERENCE PIO3PIO2PIO1PIO0 DIGITAL FILTER DAC ANALOG LPF AND OUTPUT STAGE DIGITAL HPF SERIAL CONTROL PORT (SPI or I2C) ADC SPI/I2C SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS RST OVL AOUT- PROCESSING ENGINE RAM SEP ‘00 DS486PP2
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SWITCHING CHARACTERISTICS - CONTROL PORT - I 3.5.2 I Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com.
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- CHARACTERISTICS AND SPECIFICATIONS ADC CHARACTERISTICS (TA = 25° C; VA, VD = + 5 V; -1 dB Full Scale Input Sine wave, 997 Hz; Fs = 48 kHz; XTI = 12.2880 MHz; Measurement Bandwidth is 20 Hz to 20 kHz) Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms). 2. Bench tested only. 3. Filter characteristics scale with output sample rate. 4. Measured using differential analog input circuit, see Figure 6. 5. Filter response is not tested but is guaranteed by design. Parameters Symbol Min Typ Max Units Analog Input Characteristics ADC Conversion Stereo Audio channels 16 - 24 Bits Dynamic Range (A weighted, Note 4) (unweighted, Note 4) 100 dB dB Total Harmonic Distortion + Noise (Note 1,4) THD+N - -92 -87 dB Offset Error (with internal high pass filter enabled) (Note 5) - - 0 LSB Full Scale Input Voltage (Differential) 1.9 2.0 2.1 V rms Gain Drift (Note 2) - 100 - ppm/°C Input Resistance 10 - - k Ω Input Capacitance - - 15 pF CMOUT Output Voltage - 2.3 - V Common Mode Rejection Ratio (Note 2) CMRR 60 dB High Pass Filter Characteristics Frequency Response -3dB (Note 3) -0.14dB (Note 3) 3.7 Hz Hz Phase Deviation @ 20 Hz (Note 3) - 10 - Degree Passband Ripple - - 0 dB
DAC CHARACTERISTICS (TA = 25° C; VA, VD = + 5 V; Full Scale Output Sine wave, 997 Hz; Fs = 48 kHz; XTI = 12.288 MHz; Measurement Bandwidth is 20 Hz to 20 kHz) Notes: 6. Measured with DAC calibration disabled. 7. Measured with XTI clock disabled. Specifications are subject to change without notice. Parameters Symbol Min Typ Max Units Analog Output Characteristics - Minimum Attenuation, 10 kΩ , 100 pF load; unless otherwise specified. DAC Resolution 16 - 24 Bits Dynamic Range (DAC not muted, A weighted) 95 100 - dB Total Harmonic Distortion + Noise THD+N - -90 -85 dB Offset Voltage (differential) (Note 6) - -20±5 - mV Offset Voltage (V+/V- relative to CMOUT) (Note 6) - -45/-28 - mV Full Scale Output Voltage (Differential) 1.9 2.0 2.1 V rms Gain Drift (Note 2) - 100 - ppm/°C Out of Band Energy (Fs/2 to 2Fs, Note 2) - -60 - dBFS Analog Output Load Resistance Capacitance 100 kΩ pF Analog Loopback Performance Signal-to-Noise Ratio (CCIR-2K weighted, -20 dB input) CCIR-2K - 74 - dB Power Supply Power Supply Current Operating Power Down (Note 7) 200 mA mA Power Supply Rejection (1 kHz, 10 mV rms,, Note 2) - 50 - dB
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SWITCHING CHARACTERISTICS (TA = 25° C; VA, VD = +5 V, outputs loaded with 30 pF) Notes: 8. Guaranteed by characterization but not tested. 9. On power-up, the CS4811 RST pin should be asserted until the power supplies have reached steady state. Parameters Symbol Min Typ Max Units ADC & DAC Sample Rate Fs 30 - 50 kHz XTI Frequency XTI = 256Fs 7.68 - 12.8 MHz XTI Duty Cycle XTI =256Fs (Note 8) 40 - 60 % XTI Jitter Tolerance - 500 - ps RST Low Time (Note 9) 500 - - ns
Notes: 10. Measured with a 2.2 kΩ pullup resistor to VD. Figure 1. SPI Control Port Timing
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- Data must be held for sufficient time to bridge the worst case fall time of 300 ns for CCLK/SCL.
- For both SDA transmitting and receiving.
Figure 2. I2C Control Port Timing
ABSOLUTE MAXIMUM RATINGS (All voltages with respect to AGND = DGND = 0 V.) Notes: 14.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 15. The maximum over or under voltage is limited by the input current. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (All voltages with respect to AGND = DGND = 0V . ) DIGITAL CHARACTERISTICS (TA = 25° C; VA, VD = 5 V) SWITCHING CHARACTERISTICS - PROGRAMMABLE I/O (TA = 25° C; VA, VD = 5 V ±5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30 pF) Parameters Symbol Min Typ Max Units Power Supplies Digital Analog VD VA -0.3 -0.3 6.0 6.0 V V Input Current (Note 14) - - ±10.0 mA Analog Input Voltage (Note 15) -0.7 - (VA)+0.7 V Digital Input Voltage (Note 15) -0.7 - (VD)+0.7 V Ambient Temperature (Power Applied) -55 - +125 °C Storage Temperature -65 - +150 °C Parameters Symbol Min Typ Max Units Power Supplies Digital |VA - VD| < 0.4V Analog VD VA 4.75 4.75 5.0 5.0 5.25 5.25 V V Operating Ambient Temperature T A -10 25 70 °C Parameters Symbol Min Typ Max Units High-level Input Voltage (except XTI) V IH 2.8 - (VD)+0.3 V Low-level Input Voltage (except XTI) V IL -0.3 - 0.8 V High-level Output Voltage at I0 = -2.0 mA (except XTO) V OH (VD)-1.0 - - V Low-level Output Voltage at I0 = 2.0 mA (except XTO) V OL -- 0 . 4 V High-level Input Voltage (XTI) V IH 2.8 - - V Low-level Input Voltage (XTI) V IL -- 2 . 3 V Input Leakage Current (Digital Inputs) - - 10 µA Output Leakage Current (High-Z Digital Outputs) - - 10 µA Parameters Symbol Min Typ Max Units Output Rise Time t rpo -2 0 0 -n s Output Fall Time t fpo -2 0 0 -n s
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- TYPICAL CONNECTION DIAGRAMS
37 PIO2
35 PIO3
69 SPI/I2CMode/Reset
39 OVL
Figure 3. Typical Connection Diagram, Single-ended Input
69 SPI/I2C
Figure 4. Typical Connection Diagram, I2C Mode Figure 5. Typical Connection Diagram, SPI Mode
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3.1 Overview
a single channel 24-bit audio codec. with an external non-volatile memory.
3.2 Analog Inputs
3.2.1 Line Level Inputs
3.2.2 Digital High Pass Filter
that at a sample rate of 48 kHz. Figure 6. Optional Line Input Buffer
3.3 Analog Outputs
3.3.1 Line Level Outputs
0.75 Fs can be used if greater out of band noise fil-
ommended mute circuit referenced in Figure 7.
3.4 Clock Generation
3.4.1 Clock Source
fundamental mode and designed for 20 pF loading. from an external CMOS clock input to the XTI pin. Figure 7. Butterworth Output Filters Figure 8. Output Mute Circuit
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3.5 Serial Control Port
pled during de-assertion of the RST pin.
3.5.1 SPI Bus
port bit clock, is used to clock individual data bits. and clocked out on the falling edge.
3.5.1.1 SPI Mode
eration during self-booting from a serial EEPROM. lowed by a pre-defined 16-bit start address. comes inactive and cannot be accessed.
3.5.2 I 2C Bus
serial clock, is used to clock individual data bits. device address and should be tied to ground.
3.5.2.1 I2C Mode
eration during self-booting from a serial EEPROM. Figure 9. Control Port Timing, SPI Master Mode Self-Boot
3.6 Resets
- The CODEC resynchronizes.
- The DAC outputs unmute. 0 1 2 3 16 17 18 19 25 26 27 28 29 CHIP ADDRESS (WRITE) CHIP ADDRESS (READ)MEMORY ADDRESS DATA DATA +n START ACK NO START STOP ACK ACKACK ACK 1 0 1 0 A2 A1 A0 0 0 0 0 0 0 0 1 0 1 0 A2 A1 A0 1 7 0 7 0 SCL SDA 34 35 36 3730 31 32 338 9 104 5 6 7
Figure 10. Control Port Timing, I2C Master Mode Self-Boot
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- POWER SUPPLY AND GROUNDING
verely degrade overall system performance. flowing through sensitive analog circuit areas. wide as possible to maintain low impedance. formance and enhances reliability. Figure 11. CS4811 Suggested Layout
Figure 12. Pin Assignments
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Power: analog supply, +5 V. AGND - Analog Ground Ground: analog ground. VD - Digital Power Power: digital supply, +5 V. DGND - Digital Ground Ground: digital ground. Analog Input AIN+/- - Differential Audio Input Inputs: These pins accept differential analog input signals and are biased to the internal reference voltage of approximately 2.3 V. The + and - input signals should be 180° out of phase resulting in a nominal differential input voltage of twice the input pin voltage. A single-ended signal may also be directly applied to either the + or - input with the other input AC coupled to ground through a capacitor. In general, differential input signals provide better performance. However, singled-ended inputs may result in reduced cost. Inputs may be AC or DC coupled. DC coupled input signals must be biased at 2.3 V. Any remaining DC offset is removed by an internal digital HPF. For best performance, a passive anti-aliasing filter is required. The typical connection diagram in Figure 3. shows the recommended single-ended input circuit. Figure 6 shows the recommended differential input circuit. OVL - ADC Overload Indicator Output: This pin is asserted when the ADC is clipping. The pin does not latch and de-asserts when clipping stops. Analog Output AOUT+/- - Differential Audio Output Outputs: These pins output differential analog signals which are biased to the internal reference voltage of approximately 2.3 V. The + and - output signals are 180° out of phase resulting in a nominal differential output voltage of twice the output pin voltage. For best performance, an anti-imaging filter is required. Figure 7 shows the recommended second and third order Butterworth differential-to-single- ended output buffer circuits.
CMOUT - Common Mode Output Output: This pin provides an internally generated reference of 2.3 V to be used for biasing external analog circuitry. The load on CMOUT must be DC only, with an impedance of not less than 50 kilohms. CMFILT+,CMFILT- - Common Mode Filter Connections Inputs: These pins are connections for external filter components required by the internal common mode reference circuit. See the typical connection diagram in Figure 3. for details. Serial Control Port SPI/I2C - Serial Control Port Format Select Input: This pin configures the control port for I2C format if tied to VD or SPI format if tied to DGND. SCL/CCLK - Serial Control Port Clock Output: This pin clocks serial control port data into and out of SDA in I2C mode. In SPI mode, it clocks control port data into CDIN and out of CDOUT. AD0/CS - I2C Address Bit 0 / SPI Chip Select Input/Output: In I2C ® mode, AD0 is an input and must be tied to ground. In SPI mode, CS is an output and is used to select the boot EEPROM. AD1/CDIN - I2C Address Bit 1 / SPI Data Input Input: In I2C ® mode, AD1 is an input and must be tied to ground. In SPI mode, CDIN is the serial control port data input and is clocked in on the rising edge of CCLK. SDA/CDOUT - I2C Data / SPI Data Output Bidirectional/Output: In I2C ® mode, SDA is the bidirectional data I/O line. In SPI mode, CDOUT is the serial control port data output and is clocked out on the falling edge of CCLK. Clock and Crystal XTI, XTO - Crystal Oscillator Connections (Master Clock) Input, Output: These pins provide connections for an external parallel resonant quartz crystal. Alternately, an external clock source may be applied to XTI. The clock frequency must be 256xFs.
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PIO0:3 - General Purpose Inputs/Outputs Bidirectional: These pins are general-purpose digital I/O pins. The Default state is input. The functionality of these pins after boot-up is determined by the application firmware. RST - Reset Input: This pin causes the device to enter a low power mode and forces all control port and I/O registers to be reset to their default values. The control port can not be accessed when reset is low. NC - No Connect Input: These pins are not internally connected and should be tied to ground for optimal performance. RES-NC - Reserved, No Connect These pins are reserved and must be left unconnected for normal operation. RES-VD - Reserved, Connect to VD These pins are reserved and must be tied to VD for normal operation. RES-DGND - Reserved, Connect to DGND These pins are reserved and must be tied to digital ground for normal operation. RES-AGND - Reserved, Connect to AGND These pins are reserved and must be tied to analog ground for normal operation.
- PARAMETER DEFINITIONS Dynamic Range The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbFs signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels. ADCs are measured at -1 dBFs as suggested in AES 17-1991 Annex A. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the RMS analog output level with 1 kHz full scale digital input to the RMS analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of the test signal. Units in decibels. Interchannel Isolation A measure of crosstalk between channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in decibels. Gain Error The deviation from the nominal full scale output for a full scale input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSB's of the output from mid-scale with the selected input grounded. For the DAC's, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units are in volts.
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- PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX * Nominal pin pitch is 0.65 mm = 0.65 BSC Controlling dimension is mm. JEDEC Designation: MS022 ASE/SPIL 100L MQFP PACKAGE DRAWING E D1D e L B A
- Notes •