CS47014-CVZR

CS4970X4_09 CIRRUS | Alldatasheet

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Copyright 2009 Cirrus Logic Nov ‘09 DS752PP8 High Definition Audio Decoder DSP Family with Dual 32-bit DSP Engine Technology CS4970x4 Data Sheet http://www.cirrus.com

FEATURES

‰ Multi-standard 32-bit High Definition Audio Decoding plus Post-Processing ‰ Supports high-definition audio formats including: — Dolby Digital ® Plus —D o l b y® TrueHD —D T S - H D® High Resolution Audio —D T S - H D® Master Audio — DTS Express ™ ‰ Additional Applications Library — Dolby Digital ® EX, Dolby® Pro Logic® IIz, Dolby Headphone 2®, Dolby® Virtual Speaker 2®, Audistry® — DTS-ES 96/24 ™ Discrete 7.1, DTS-ES™ Discrete 7.1, DTS- ES™ Matrix 6.1, DTS Neo:6®, DTS Neural Surround™ —D S D ® — MPEG-2 AAC ™ LC 5.1 —S R S ® CS2®, SRS TruV olume™ , SRS® TruSurround HD4™ , WOW HD™ , —T H X ® Ultra2™ , THX® ReEQ™ — Thomson MP3 Surround — Audyssey 2EQ ™ Module ‰ Cirrus Logic’s Applications Library — Cirrus Original Multi-Channel Surround 2 (COMS2), Cirrus Band Xpander™ , Cirrus Virtualization Technology, Cirrus Intelligent Room Calibration 2 (IRC2) — Crossbar Mixer, Signal Generator — Advanced Post-Processors including: 7.1 Bass Manager, Tone Control, 11- Band Parametric EQ, Delay, 2:1/4:1 Decimator, 1:2/1:4 Upsampler ‰ Up to 12 Channels of 32-bit Serial Audio Input ‰ Customer Software Security Keys ‰ 16 Ch x 32-bit PCM Out with Dual 192 kHz SPDIF Tx ‰ Two SPI™ /I2C™ ports ‰ One Parallel Port (144-pin LQFP package only) ‰ Large On-chip X, Y , and Program RAM & ROM ‰ SDRAM and Serial Flash Memory Support The CS4970x4 DSP family is an enhanced version of the CS4953x DSP family with higher overall performance. In addition to all the mainstream audio processing codes in on- chip ROM that the CS4953x DSP offers, the CS4970x4 device family also supports the decoding of major high-definition audio formats. Additionally, the CS4970x4, a dual-core device, performs the high-definition audio decoding on the first core, leaving the second core available for audio post-processing and audio enhancement. The CS4970x4 device supports the most demanding audio post processing requirements. It provides an easy upgrade path to systems currently using the CS495xx or CS4953x device with minor hardware and software changes.

Ordering Information

See page 28 for ordering information. Coyote 32-bit DSP A D M A Coyote 32-bit DSP B Ext. Memory Controller P S/PDIF X Y P X Y Serial Control 1

16 Ch PCM

12 Ch. Audio In / 6 Ch. SACD In Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

2 Copyright 2009 Cirrus Logic DS752PP8

32-bit High Definition Audio Decoder DSP Family Table of Contents

4 Copyright 2009 Cirrus Logic DS752PP8

The scope of the CS4970x4 Data Sheet is primarily the hardware specifications of the CS4970x4 family of devices. This includes hardware functionality, characteristic data, pinout, and packaging information. array of digital interface products and audio converters to meet your audio system-level design requirements. product family are a superset of audio features available in the CS4953xx product family. Please refer to Table 2 on page 5 for the speed and firmware features of CS4970x4 product family. Table 1. CS4970x4 Related Documentation

Table 2. Device and Firmware Selection Guide

1. Processing may be restricted and dependent on firmware selected. Contact your Cirrus Logic FAE for concurrency matrix.

300 MIPS

1. Downsampling and Upsampling functionality is located in the operating system. The Cirrus Decimator (Down-Sampler) is also available as

a separate post-processing module that is described in the application note, AN288PPI.

6 Copyright 2009 Cirrus Logic DS752PP8

32-bit High Definition Audio Decoder DSP Family

2.1 Migrating from the CS495xx(2) to the CS4970x4

The CS4970x4 was designed to provide an easy upgrade path from the CS495xx & CS4953x. Although 144-pin versions of the two devices are virtually identical with respect to external system connection, there are some small differences the hardware designer should be aware of:  The PLL supply voltage on the CS4970x4 is 3.3V vs. 1.8V on the CS495xx.  The PLL filter topology is simpler when using the CS4970x4 rather than the CS495xx.  The CS4970x4 adds support for 6-channel DSD input.  The CS4970x4 adds support for TDM mode on both audio input and output ports.  The CS4970x4 does not support external SRAM operation.  The CS4970x4 external SDRAM bus speed is fixed at 150 MHz vs. the 120 MHz max bus speed for the CS495xx. Some firmware modules also support a 75 MHz CS4970x4 SDRAM bus speed. Please refer to AN304 for details.  The CS4970x4 CLKOUT pin can output XTALI or XTALI/2. The CS495xx can only output XTALI.

2.2 Licensing

Licenses are required for all of the third party audio decoding/processing algorithms listed below, including the application notes. Please contact your local Cirrus Sales representative for more information. 3. Code Overlays The suite of software available for the CS4970x4 family consists of operating systems (OS) and a library of overlays. The overlays have been divided into three main groups called Decoders, Matrix-processors, and Post- processors. All software components are defined in the following list:  OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-processing subroutines, auto-detection, error concealment, etc.  Decoders - Any Module that initially writes data into the audio I/O buffers, e.g. AC-3 ™ , DTS, PCM, etc. All the decoding/processing algorithms listed require delivery of PCM or IEC61937-packed, compressed data via I2S- or LJ-formatted digital audio to the CS4970x4 from A/D converters, SPDIF Rx, HDMI Rx, etc.  Matrix-processors - Any module that processes audio I/O buffer PCM data in-place before the Post- processors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer through processes like Virtualization (nÖ2 channels) or Matrix Decoding (2Ön channels). Examples are Dolby ProLogic IIx and DTS Neo:6.

• Virtualizer-processor - Any module that encodes PCM data into fewer output channels than input channels (nÖ2 channels) with the effect of providing “phantom” speakers to represent the physical audio channels that were eliminated. Examples are Dolby Headphone® 2 and Dolby Virtual Speaker® 2. Generally speaking, these modules reduce the number of valid channels in the audio I/O buffer.  Post-processors - Any module that processes audio I/O buffer PCM data in-place after the Matrix-Processors. Examples are Bass Management, Audio Manager, Tone Control, EQ, Delay, Customer-specific Effects, Dolby Headphone/Virtual Speaker, etc. The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each overlay can be reloaded independently without disturbing the other overlays. For example, when a new decoder is selected, the OS, matrix-, and post-processors do not need to be reloaded — only the new decoder (the same is true for the other overlays).

1. Hardware Functional Description

4.1 Coyote DSP Core

registers, and 12 index registers. more MIPS available for signal processing instructions. post-processor modules which are available from Cirrus Logic. Digital Broadcast Decoder applications.

4.1.1 DSP Memory

SDRAM will be needed to support Dolby TrueHD and DTS-HD Master Audio. The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.

4.1.2 DMA Controller

controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable.

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

the DAI from an HDMI receiver. Table 3. CS4970x4 DSP Memory Sizes

8 Copyright 2009 Cirrus Logic DS752PP8

32-bit High Definition Audio Decoder DSP Family The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock domain. The sample rate of the input clock domains can be determined automatically by the DSP , which off-loads the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted via software.

4.2.2 Digital Audio Output Port (DAO)

There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a 192 kHz SPDIF transmitter (data with embedded clock on a single line).

4.2.3 Serial Control Port 1 & 2 (I

2C™ or SPI™ ) There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or SPI modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external clock up to 50 MHz in SPI mode. This high clock speed enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for audio sub-system control.

4.2.4 Parallel Control Port

The CS4970x4 parallel port supports both Motorola ® and Intel® interfaces. It can be used for both control and data delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin package.

4.2.5 External Memory Interface

The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus.

4.2.6 GPIO

Many of the CS4970x4 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.

4.2.7 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving audio converters. The CS4970x4 defaults to running from the external reference frequency and can be switched to use the PLL output after overlays have been loaded and configured, either through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.

4.3 DSP I/O Description

4.3.1 Multiplexed Pins

Many of the CS4970x4 pins are multi-functional. For details on pin functionality please refer to the CS4970x4 System Designer’ s Guide.

4.3.2 Termination Requirements

Open-drain pins on the CS4970x4 must be pulled high for proper operation. Please refer to the CS4970x4 System Designer’ s Guide to identify which pins are open-drain and what value of pull-up resistor is required for proper operation.

DS752PP8 Copyright 2009 Cirrus Logic 9 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family Mode select pins on the CS4970x4 are used to select the boot mode upon the rising edge of reset. A detailed explanation of termination requirements for each communication mode select pin can be found in the CS4970x4 System Designer’ s Guide.

4.3.3 Pads

The CS4970x4 I/O operate from the 3.3 V supply and are 5 V tolerant.

4.4 Application Code Security

The external program code may be encrypted by the programmer to protect any intellectual property it may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the device.

10 Copyright 2009 Cirrus Logic DS752PP8

32-bit High Definition Audio Decoder DSP Family 5. Characteristics and Specifications Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C, CL = 20 pF, VDD = 1.8 V , VDDA = VDDIO = 3.3 V , GNDD = GNDIO = GNDA = 0 V .

5.1 Absolute Maximum Ratings

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

5.2 Recommended Operating Conditions

(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V) Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.

5.3 Digital DC Characteristics

(Measurements performed under static conditions.) Parameter Symbol Min Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDDIO| VDD VDDA VDDIO –0.3 –0.3 –0.3 2.0 3.6 3.6 0.3 V V V V Input pin current, any pin except supplies I in -+ / - 1 0 m A Input voltage on PLL_REF_RES V filt -0.3 3.6 V Input voltage on I/O pins V inio -0.3 5.0 V Storage temperature T stg –65 150 °C Parameter Symbol Min Typ Max Unit DC power supplies: Core supply PLL supply I/O supply |VDDA – VDDIO| VDD VDDA VDDIO 1.71 3.13 3.13 1.8 3.3 3.3 1.89 3.46 3.46 V V V V Ambient operating temperature Commercial Grade (CQZ/CVZ) T A 0 +25 + 70 Parameter Symbol Min Typ Max Unit High-level input voltage V IH 2.0 - - V Low-level input voltage, except XTI V IL -- 0 . 8V Low-level input voltage, XTI V ILXTI -- 0 . 6V Input Hysteresis V hys 0.4 V High-level output voltage (IO = -4mA), except XTI, SDRAM pins VOH VDDIO * 0.9 - - V Low-level output voltage (IO = 4mA), except XTI, SDRAM pins VOL - - VDDIO * 0.1 V SDRAM High-level output voltage (IO = -8mA) V OH VDDIO * 0.9 - - V SDRAM Low-level output voltage (IO = 8mA) V OL - - VDDIO * 0.1 V Input leakage current (all digital pins with internal pull- up resistors disabled) IIN --5 μA

DS752PP8 Copyright 2009 Cirrus Logic 11 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family

5.4 Power Supply Characteristics

(Measurements performed under operating conditions.)

5.5 Thermal Data (144-Pin LQFP)

5.6 Thermal Data (128-pin LQFP)

Notes: 1.Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20% of the top and bottom layers. 2.Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20% of the top and bottom layers and 0.5-oz copper covering 90% of the internal power plane and ground plane layers. 3.To calculate the die temperature for a given power dissipation Τj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ] 4.To calculate the case temperature for a given power dissipation Τc = Τj - [ (Power Dissipation in Watts) * ψ jt ] Input leakage current (all digital pins with internal pull- up resistors enabled, and XTI) IIN-PU -- 7 0 μA Parameter Min Typ Max Unit Power supply current: Core and I/O operating: VDD1 PLL operating: VDDA With external memory and most ports operating: VDDIO 1.Dependent on application firmware and DSP clock speed. 500 3.5 120 mA mA mA Parameter Symbol Min Typ Max Unit Thermal Resistance (Junction to Ambient) Two-layer Board Four-layer Board2 θja °C / Watt Thermal Resistance (Junction to Top of Package) Two-layer Board Four-layer Board2 ψjt .39 .33 °C / Watt Parameter Symbol Min Typ Max Unit Thermal Resistance (Junction to Ambient) Two-layer Board Four-layer Board2 θja °C / Watt Thermal Resistance (Junction to Top of Package) Two-layer Board1 Four-layer Board2 ψjt .45 .39 °C / Watt Parameter Symbol Min Typ Max Unit

12 Copyright 2009 Cirrus Logic DS752PP8

5.7 Switching Characteristics— RESET#

Figure 1. RESET# Timing

5.8 Switching Characteristics — XTI

Figure 2. XTI Timing

1. Part characterized with the following crysta l frequency values: 12.288 and 24.576 MHz.
2. C L refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside

recommendation for load capacitor selection.

DS752PP8 Copyright 2009 Cirrus Logic 13 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family

5.9 Switching Characteristics — Internal Clock

5.10 Switching Characteristics — Se rial Control Port - SPI Slave Mode

Parameter Symbol Min Max Unit Internal DCLK frequency1 CS497004-CQZ CS497004-CQZR CS497024-CVZ CS497024-CVZR CS497024-CVZ CS497024-CVZR 1.After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until the next power-on reset. Fdclk Fxtal 150 MHz Internal DCLK period1 CS497004-CQZ CS497004-CQZR CS497024-CVZ CS497024-CVZR CS497024-CVZ CS497024-CVZR DCLKP 6.7 1/F xtal ns Parameter Symbol Min Typical Max Units SCP_CLK frequency1 1. The specification f spisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer.At boot the maximum speed is Fxtal/3. f spisck -2 5 M H z SCP_CS# falling to SCP_CLK rising t spicss 24 - ns SCP_CLK low time t spickl 20 - ns SCP_CLK high time t spickh 20 - ns Setup time SCP_MOSI input t spidsu 5- n s Hold time SCP_MOSI input t spidh 5- n s SCP_CLK low to SCP_MISO output valid t spidov -1 1 n s SCP_CLK falling to SCP_IRQ# rising t spiirqh -2 0 n s SCP_CS# rising to SCP_IRQ# falling t spiirql 0n s SCP_CLK low to SCP_CS# rising t spicsh 24 - ns SCP_CS# rising to SCP_MISO output high-Z t spicsdz -2 0 n s SCP_CLK rising to SCP_BSY# falling t spicbsyl -3 *DCLKP+20 ns

14 Copyright 2009 Cirrus Logic DS752PP8

Figure 3. Serial Control Port - SPI Slave Mode Timing

5.11 Switching Characteristics — Se rial Control Port - SPI Master Mode

1. The specification f spisck indicates the maximum speed of the hardware. The system designer should be aware that the

actual maximum speed of the communication port may be limited by the firmware application.

1. SCP_CLK PERIOD refers to the period of SCP_CLK as being us ed in a given application. It does not refer to a tested

Figure 4. Serial Control Port - SPI Master Mode Timing

5.12 Switching Characteristics — Serial Control Port - I 2C Slave Mode

1. The specification f iicck indicates the maximum speed of the hardware. The system designer should be aware that

using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer.

16 Copyright 2009 Cirrus Logic DS752PP8

Figure 5. Serial Control Port - I2C Slave Mode Timing

5.13 Switching Characteristics — Serial Control Port - I 2C Master Mode

1. The specification f iicck indicates the maximum speed of the hardware. The system designer should be aware that

the actual maximum speed of the communication port may be limited by the firmware application.

Figure 6. Serial Control Port - I2C Master Mode Timing

5.14 Switching Characteristics — Parallel Control Port - Intel ® Slave Mode

18 Copyright 2009 Cirrus Logic DS752PP8

Figure 7. Parallel Control Port - Intel® Slave Mode Read Cycle Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle

1. The system designer should be aware that the actua l maximum speed of the communication port may be limited

DS752PP8 Copyright 2009 Cirrus Logic 19 CS4970x4 Data Sheet 32-bit High Definition Audio Decoder DSP Family

5.15 Switching Characteristics — Parallel Control Port - Motorola ® Slave Mode

Parameter Symbol Min Max Unit Address setup before PCP_CS# and PCP_DS# low t mas 5- n s Address hold time after PCP_CS# and PCP_DS# low t mah 5- n s Read Delay between PCP_DS# then PCP_CS# low or PCP_CS# then PCP_DS# low tmcdr 0- n s Data valid after PCP_CS# and PCP_DS# low with PCP_R/W# high tmdd -1 9 n s PCP_CS# and PCP_DS# low for read t mrpw 24 - ns Data hold time after PCP_CS# or PCP_DS# high after read t mdhr 8- n s Data high-Z after PCP_CS# or PCP_DS# high after read t mdis -1 8 n s PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next read1 1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent overflowing the input data buffer. CS4953x4/CS4970x4 System Designer’ s Guide should be consulted for the firmware speed limitations. t mrd 30 - ns PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next write1 tmrdtw 30 - ns PCP_RW# rising to PCP_IRQ# falling tmrwirqh -1 2 n s Write Delay between PCP_DS# then PCP_CS# low or PCP_CS# then PCP_DS# low tmcdw 0- n s Data setup before PCP_CS# or PCP_DS# high t mdsu 8- n s PCP_CS# and PCP_DS# low for write t mwpw 24 - ns PCP_R/W# setup before PCP_CS# AND PCP_DS# low t mrwsu 24 - ns PCP_R/W# hold time after PCP_CS# or PCP_DS# high t mrwhld 8- n s Data hold after PCP_CS# or PCP_DS# high t mdhw 8- n s PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low with PCP_R/W# high for next read1 tmwtrd 30 - ns PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for next write1 tmwd 30 - ns PCP_RW# rising to PCP_BSY# falling tmrwbsyl - 2*DCLKP + 20 - ns

20 Copyright 2009 Cirrus Logic DS752PP8

Figure 9. Parallel Control Port - Motorola® Slave Mode Read Cycle Timing Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing

5.16 Switching Characteristics — Digital Audio Slave Input Port

Figure 11. Digital Audio Input (DAI) Port Timing Diagram

22 Copyright 2009 Cirrus Logic DS752PP8

5.17 Switching Characteristics — DSD ® Serial Input Port

Figure 12. DSD Serial Audio Input Timing

5.18 Switching Characteristics — Digital Audio Output Port

Figure 13. Digital Audio Port Output Timing Master Mode

1. Master mode timing specifications ar e characterized, not production tested.
2. Master mode is defined as the CS4970x4 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is

divided to produce DAO_SCLK, DAO_LRCLK.

1. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the

point at which the data is valid.

1. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

24 Copyright 2009 Cirrus Logic DS752PP8

Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)

5.19 Switching Characteristics — SDRAM Interface

Refer to Figure 15 through Figure 18.

26 Copyright 2009 Cirrus Logic DS752PP8

Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle

Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle

28 Copyright 2009 Cirrus Logic DS752PP8

Note: Please contact the factory for availability of the -D (automotive grade) package.

1. Environmental, Manufacturing, and Handling Information

• MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Table 4. Ordering Information Table 5. Environmental, Manufacturing, & Handling Information

Figure 19. 128-Pin LQFP Pin-Out Diagram

30 Copyright 2009 Cirrus Logic DS752PP8

Figure 20. 144-Pin LQFP Pin-Out Diagram

1. Package Mechanical Drawings

Figure 21. 128-Pin LQFP Package Drawing Table 6. 128-Pin LQFP Package Characteristics

32 Copyright 2009 Cirrus Logic DS752PP8

Figure 22. 144-Pin LQFP Package Drawing Controlling dimension is millimeter. Table 7. 144-Pin LQFP Package Characteristics

A1 FEB 2007 Advance Release. PP2 JULY 2007 Added notice about status of DTS-HD license on page 1 and 7. version PP2. The license for the DTS-HD decoder is now in place. from Pin 7 and adding EE_CS to Pin 25. Section 6.and Section 7. Added device and firmware selection guide in Table 2. “Switching Characteristics — Internal Clock” on page 13 . PP7 September 30, 2008 Removed references to External Parallel Flash / SRAM Interface. same section. Added Section 5.6 “Thermal Data (128-pin LQFP)” on page 11. Figure 16. In Section 5.3, the parameter, “Input leakage current (all digital pins CS497014 to Section 6. “Ordering Information” on page 28 and to Section 7. Table 2, “Device and Firmware Selection Guide,” on page 5.

34 Copyright 2009 Cirrus Logic DS752PP8

32-bit High Definition Audio Decoder DSP Family Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com. IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its sub- sidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowl- edgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, includ- ing use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the informa- tion only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPER- TY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT- NESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEM- NIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Dolby, Dolby Digital, Dolby Headphone, Dolby Virtual Speaker, Dolby Headphone, Pro Logic, AC-3, Audistry, and Surround EX are registered trademarks of Dolby Laboratories, Inc. AAC is a trademark of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. DTS and DTS Digital Surround are registered trademarks of the Digital Theater Systems, Inc. DTS Neo:6, DTS-ES 96/24, DTS-ES, DTS 6.1, DTS 96/24, DTS Neural Surround, and DTS Express are trademarks of Digital Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of DTS in any finished end-user or ready-to-use final product. THX Technology by Lucasarts Entertainment Company Corporation. THX is a registered trademark of Lucasarts Entertainment Company Corporation. Re-equaliza- tion and Ultra 2 are trademarks of Lucasfilm Ltd. SRS, Circle Surround and Trusurround XT are registered trademarks of SRS Labs, Inc. Circle Surround II, TruSurround HD4, and WOW HD are trademarks of SRS Labs, Inc. The CIRCLE SURROUND TECHNOLOGY rights incorporated in the Cirrus Logic chip are owned by SRS Labs, Inc. and by Valence Technology Ltd., and licensed to Cirrus Logic, Inc. Users of any Cirrus Logic chip containing enabled CIRCLE SURROUND® TECHNOLOGY (i.e., CIRCLE SURROUND® LICENSEES) must first sign a license to pur- chase production quantities for consumer electronics applications which may be granted upon submission of a preproduction sample to, and the satisfactory passing of performance verification tests performed by SRS Labs, Inc., or Valence Technology Ltd. E-mail requests for performance specifications and testing rate schedule may be made to cslicense@srslabs.com. SRS Labs, Inc. and Valence Technology, Ltd., reserve the right to decline a use license for any submission that does not pass performance specifications or is not in the consumer electronics classification. All equipment manufactured using any Cirrus Logic chip containing enabled CIRCLE SURROUND® TECHNOLOGY must carry the Circle Surround® logo on the front panel in a manner approved in writing by SRS Labs, Inc., or Val ence Technology Ltd. If the Circle Surround logo is printed in u sers manuals, service manuals or advertisements, it must appear in a form approved in writing by SR S Labs, Inc., or Valence Technology, Ltd. The rear panel of C ircle Surround® products, users manuals, service manuals, and all advertising must all carry the legends as described in LICENSOR'S most current version of the CIRCLE SURROUND Trademark Usage Manual. Microsoft and Windows Media are registered trademarks of Microsoft Corporation. The product includes technology owned by Microsoft Corporation and cannot be used or distributed without a license from Microsoft Licensing, Inc. , HDCD, High Definition Compatible Digital and Pacific Microsonics Inc. are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. HDCD technology provided under license from Microsoft Corporation. The product's design (and/or software) is covered by one or more of the following: 5,479,168; 5,638,074; 5,640,161; 5,808,574; 5,838,274; 5,854,600; 5,864,311; 5,872,531 with other patents pending. Supply of this product does not convey a license under the relevant intellectual property of Thomson multimedia and/or Fraunhofer Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. An independent license for such use is required. For details, please visit http://www.mp3licensing.com. Motorola and SPI are trademarks of Motorola, Inc. Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Semiconductor. DSD, and Direct Stream Digital are registered trademarks of SONY KABUSHIKI KAISHA CORPORATION.