CS4610 CIRRUS | Alldatasheet
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Technical content
Copyright Cirrus Logic, Inc. 1998 (All Rights Reserved) CS4610/11 Advanced Product Databook CrystalClear™ SoundFusion™ PCI Audio Accelerator
FEATURES
■ High Performance PCI Audio Accelerator — Powerful RAM-based SLIMD™ DSP core provides high task concurrency and maximum flexibility — Efficient bus mastering PCI interface minimizes host loading — DMA engine with hardware scatter-gather manages up to 96 simultaneous audio/data streams ■ Flexible Digital Audio Interface Design — Direct Connection to CS423x Codec — Simple expansion to 6 audio output channels — Direct Connection to CS4297 AC’97 Codec ■ Complete Solution including DSP Software and Windows 95 ® drivers — Acceleration of DirectSound® , DirectSound3D® , Direct- Input™, and DirectShow™ APIs — High Quality HRTF-Based 3D Positional Sound — General MIDI Wavetable Synthesis with Reverb and Chorus —D o l b y ® AC-3® (5.1 channel) and MPEG-2 Audio Decod- ing (CS4610 only) with speaker virtualization
DESCRIPTION
The CS4610/11 is a high performance audio accel- erator for the PCI bus. This device, combined with application and driver software, provides a com- plete system solution for hardware acceleration of Windows 95 DirectSound, DirectSound3D, Direct- Input, DirectShow, and Wavetable Synthesis. The CS4610/11 is based on the Cirrus Logic, Crys- talClear Stream Processor (SP) DSP core. The SP core is optimized for digital audio processing, and is powerful enough to handle complex signal pro- cessing tasks such as Dolby AC-3 decoding (CS4610 only) with ease. The SP core is supported by a bus mastering PCI interface and a built-in ded- icated DMA engine with hardware scatter-gather support. These support functions ensure extremely efficient transfer of audio data streams to and from host-based memory buffers, providing a system solution with maximum performance and minimal host CPU loading. The all-digital CS4610/11 supports a variety of au- dio I/O configurations, including direct connection to the CrystalClear CS423x Codecs via a bi-direc- tional serial data link, or direct connection to an AC’97 Codec such as the CrystalClear CS4297.
ORDERING INFORMATION
CS4610-CM 100-pin MQFP 20x14x3.07 mm CS4610C-CQ 128-pin TQFP 20x14x1.60 mm CS4611-CM 100-pin MQFP 20x14x3.07 mm 96-Stream DMA Controller with Hardware Scatter/Gather MPU-401 MIDI Interface AC '97 Interface GPIO Interrupt Controller 423x Interface and Dual I S Output Sample RAM Program RAM Coefficient ROM Parameter RAM PLL Clock Generator PCI Interface Joystick Interface SLIMD SP Core DS241PP5 MAR ‘98
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CrystalClear™ SoundFusion™ PCI Audio Accelerator ABSOLUTE MAXIMUM RATINGS (PCIGND = CGND = CRYGND = 0 V, all voltages with respect to 0 V) Notes: 1. Includes all power generated by AC and/or DC output loading. 2. The power supply pins are at recommended maximum values. XTALI & XTALO are at 3.6 V maximum. 3. At ambient temperatures above 70° C, total power dissipation must be limited to less than 0.4 Watts. WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (PCIGND = CGND = CRYGND = 0 V, all voltages with respect to 0 V) Specifications are subject to change without notice. Parameter Symbol Min Typ Max Unit Power Supplies PCIVDD CVDD CRYVDD VDD5REF 4.6 4.6 4.6 5.5 V V V V Total Power Dissipation (Note 1) - - 1.5 W Input Current per Pin, DC (Except supply pins) - - 10 mA Output current per pin, DC - - 10 mA Input voltage (Note 2) -0.3 - 5.75 V Ambient temperature (power applied) (Note 3) -45 - 85 °C Storage temperature -55 - 150 °C Parameter Symbol Min Typ Max Min Typ Max UnitCS4610 CS4611 Power Supplies PCIVDD CVDD CRYVDD VDD5REF 4.75 3.3 3.3 3.3 3.6 3.6 3.6 5.25 4.75 3.3 3.3 3.3 3.6 3.6 3.6 5.25 V V V V Internal DSP Frequency - - 100 - - 85 MHz Operating Ambient Temperature T A 02 5 7 002 5 7 0° C Dolby’s AC3 Technology is implemented on the CS4610 Stream Processor Only. Supply of this Implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other Industrial or Intellectual Property Right of Dolby Laboratories, to use this Implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories. Dolby and AC-3 are registered trademarks of Dolby Laboratories Licensing Corporation. Windows, Windows 95, DirectSound, and DirectSound3D are registered trademarks of Microsoft Corporation. DirectInput, DirectX and DirectShow are trademarks of Microsoft Corporation. Sound Blaster and Sound Blaster Pro are trademarks of Creative Technology, Ltd. Crystal, CrystalClear, SLIMD and SoundFusion are trademarks of Cirrus Logic, Inc. All other names are trademarks, registered trademarks, or service marks of their respective companies.
Notes: 4. Specifications guaranteed by characterization and not production testing.
- Refer to V/I curves in Figure 1. Specification does not apply to CLK and RST# signals. Switching Current
High specification does not apply to SERR# and INTA# which are open drain outputs.
- Cumulative edge rate across specified range. Rise slew rates do not apply to open drain outputs.
Figure 1. AC Characteristics
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CrystalClear™ SoundFusion™ PCI Audio Accelerator DC CHARACTERISTICS (TA = 70° C; PCIVDD = CVDD = CRYVDD = 3.3 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; all voltages with respect to 0 V unless otherwise noted) Notes: 9. The following signals are tested to 6 mA: FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR#, PERR#, and INTA#. All other PCI interface signals are tested to 3 mA. 10. Input leakage currents include hi-Z output leakage for all bi-directional buffers with three-state outputs. At supply voltages of 3.6 V or higher and ambient temperatures of 70° C, the high level leakage current may exceed 70 µA. For normal operating ranges of 25° C and a supply voltage of 3.3 V, the high level leakage current is within specification. 11. For open drain pins, high level output voltage is dependent on external pull-up used and number of attached gates. 12. Typical values are given as average current with typical SP task execution and data streaming. Current values vary dramatically based on the software running on the SP. Parameter Symbol Min Typ Max Unit PCI Interface Signal Pins High level input voltage V IH 2- 5 . 7 5 V Low level input voltage V IL -0.5 - 0.8 V High level output voltage Iout = -2 mA V OH 2.4 - - V Low level output voltage Iout = 3 mA, 6 mA (Note 9) V OL -- 0 . 5 5 V High level leakage current Vin = 2.7 V (Note 10) I IH -- 7 0 µ A Low level leakage current Vin = 0.5 V (Note 10) I IL -- - 7 0 µ A Non-PCI Interface Signal Pins (Except XTALO) High level input voltage XTALI Other Pins VIH 2.3 3.3 4.0 5.75 V V Low level input voltage XTALI Other Pins VIL -0.5 -0.5 0.8 0.8 V V High level output voltage Iout = -4 mA (Note 11) V OH 2.4 - - V Low level output voltage Iout = 4 mA V OL -- 0 . 4 V High level leakage current Vin = 5.25 V I IH -- 1 0 µ A Low level leakage current Vin = 0 I IL -- - 1 0 µ A Parameter Min Typ Max Min Typ Max UnitCS4610 CS4611 Power Supply Pins (Outputs Unloaded) Power Supply Current: VDD5REF PCIVDD/CVDD/CRYVDD Total (Notes 4,12) 0.6 200 370 0.6 164 240 mA mA Low Power Mode Supply Current - 10 - - 10 - mA
equal to the leakage current. Specification is guaranteed by design, not production tested.
- RST# is asserted and de-asserted asynchronously with respect to PCICLK.
- All output drivers are asynchronously floated when RST# is active.
Figure 2. PCI Timing Measurement Conditions
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Figure 3. CS4610/11 and CS423x Link and 6 Channel Output Timing Diagram
Figure 4. AC’97 Configuration Timing Diagram
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the required external pull-up resistor. Figure 5. EEPROM Timing
CrystalClear™ SoundFusion™ PCI Audio Accelerator OVERVIEW The CS4610 and CS4611 are high performance au- dio accelerator DSPs for the PCI bus. These devic- es, combined with application and driver software, provide a complete system solution for cost effec- tive acceleration of Windows ® DirectSound, DirectSound3D, DirectInput, DirectShow, MIDI playback via Wavetable Synthesis with reverbera- tion and chorus effects processing, and more. The CS4610 is a high-performance, full-featured version of the SoundFusion audio accelerator. The CS4611 is a reduced-cost version of the CS4610. The CS4611 has a lower max clock speed and does not support AC-3 or MPEG-2. Please refer to the OEM Software Reference Manual for more details. There are three main functional blocks within the CS4610/11: the Stream Processor, the PCI Inter- face, and the DMA Engine. The Stream Processor (SP) is a high speed custom Digital Signal Proces- sor (DSP) core designed by Cirrus Logic, Inc. spe- cifically for audio signal processing. This extremely powerful DSP core is capable of running complex algorithms such as Dolby Digital AC-3 or MPEG-2 audio decoding for applications such as DVD movie playback or gaming. The SP is capable of running a number of different signal processing algorithms simultaneously. This high concurrency capability is valuable for applications such as immer- sive 3D games, which may play a number of Direct- Sound streams, a number of DirectSound3D streams, and a MIDI music sequence simultaneously. Separate RAM memories are included on-chip for the SP program code (Program RAM), parameter data (Parameter RAM), and audio sample data (Sample RAM). A small ROM memory (Coeffi- cient ROM) is included to store fixed coefficient data required for the sample rate conversion and audio decompression algorithms. The RAM-based DSP architecture of the CS4610/11 ensures maximum system flexibility. The software function/feature mix can be adapted to meet the requirements of a variety of different applications, such as DirectX™ games, DVD mov- ie playback, or DOS applications. This RAM-based architecture also provides a means for future sys- tem upgrades, allowing the addition of new or up- graded functionality through software updates. The CS4610/11 provides an extremely efficient bus mastering interface to the PCI bus. The PCI Inter- face function allows economical burst mode trans- fers of audio data between host system memory buffers and the CS4610/11 device. Program code and parameter data are also transferred to the CS4610/11 over the PCI Interface. The CS4610/11 DMA Engine provides dedicated hardware to manage transfer of up to 96 concurrent audio/data streams to and from host memory buff- ers. The DMA Engine provides hardware scatter- gather support, allowing simple buffer allocation and management. This implementation improves system efficiency by minimizing the number of host interrupts. The CS4610/11 supports a variety of audio I/O configurations, including direct connection to the CrystalClear CS423x Codecs or to an AC’97 Co- dec such as the CrystalClear CS4297. The system’s flexibility is further enhanced by the inclusion of auxiliary ADC and DAC ports, a bi-directional se- rial MIDI port, a joystick port, a hardware volume control interface, and a serial data port which al- lows connection of an optional external EEPROM device. The block diagram in Figure 6 depicts a mother- board audio subsystem based on the CS4610/11 and the CS423x. This approach features the proven ISA legacy support of the CS423x Codecs (which include the CS423xB family as well as the CS4235 and CS4239 devices). The CS423x provides DOS applications with hardware compatibility for the Sound Blaster Pro™, OPL3, and MPU-401 register sets. In this configuration, the CS423x also pro- vides the system joystick interface. The CS423x
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directional serial data link between the two devices. Figure 6. CS4610/11 + CS423x Motherboard Audio Configuration Figure 7. CS4610/11 + AC ‘97 Codec Configuration
CrystalClear™ SoundFusion™ PCI Audio Accelerator Stream Processor DSP Core The CS4610/11 Stream Processor (SP) is a custom DSP core design optimized for processing and syn- thesizing digital audio data streams. The SP fea- tures a Somewhat Long Instruction Multiple Data (SLIMD) modified dual Harvard architecture. The device uses a 40-bit instruction word and operates on 32-bit data words. The SP core is conservatively rated at 300 Million Instructions per second (300 MIPS) when running at a 100 MHz internal clock speed (CS4611 runs at 85 MHz). The SP includes two Multiply-Accumulate (MAC) blocks and one 16-bit Arithmetic and Logic Unit (ALU). The MAC units perform 20-bit by 16-bit multiplies and have 40-bit accumulators, providing higher quality than typical 16-bit DSP architectures. PLL and Clock Control The CS4610/11 includes a programmable Phase Locked Loop (PLL) circuit which generates the high frequency internal SP clock from a lower fre- quency input clock. The PLL input may come from the CS4610/11 crystal oscillator circuit or the serial port clock (ASCLK/SCLK). The CS4610/11 Clock Control circuitry allows gating of clocks to various internal functional blocks to conserve power during power conservation modes, as well as during nor- mal modes of operation when no tasks are being executed. Host Interface The CS4610/11 host interface is comprised of two separate interface blocks which are memory mapped into host address space. The CS4610/11 interface blocks can be located anywhere in the host 32-bit physical address space. The interface block locations are defined by the addresses pro- grammed into the two Base Address Registers in the CS4610/11 PCI Configuration Space. These base addresses are normally set up by the system’s Plug and Play BIOS. The first interface block (lo- cated using Base Address 0) is a 4 kByte register block containing general purpose configuration, control, and status registers for the device. The sec- ond interface block (located using Base Address 1) is a 1 MByte block which maps all of the CS4610/11 internal RAM memories (SP Program RAM, Parameter RAM, and Sample RAM), along with the SP debug registers, into host memory space. This allows the host to directly peek and poke RAM locations on the device. The relation- ship between the Base Address Registers in the CS4610/11 PCI Configuration Space and the host memory map is depicted in Figure 8. CS4610/11 PCI Interface The CS4610/11 provides a bus mastering PCI bus interface which complies with the PCI Local Bus Specification version 2.1. PCI Bus Transactions As a target of a PCI bus transaction, the CS4610/11 supports the Memory Read (from internal registers or memory), Memory Write (to internal registers or memory), Configuration Read (from CS4610/11 configuration registers), Configuration Write (to CS4610/11 configuration registers), Memory Read Multiple (aliased to Memory Read), Memory Read Line (aliased to Memory Read), and the Memory Write and Invalidate (aliased to Memory Write) transfer cycles. The I/O Read, I/O Write, Interrupt Acknowledge, Special Cycles, and Dual Address Cycle transactions are not supported. As Bus Master, the CS4610/11 generates the Mem- ory Read Multiple and Memory Write transactions. The Memory Read, Configuration Read, Configu- ration Write, Memory Read Line, Memory Write and Invalidate, I/O Read, I/O Write, Interrupt Ac- knowledge, Special Cycles, and Dual Address Cy- cle transactions are not generated.
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phase of transaction is completed). Table 1. CS4610/11 PCI Interface Transaction Summary Figure 8. CS4610/11 Host Interface Base Address Registers
Write of 1 to any error bit position clears it. Table 2. CS4610/11 PCI Configuration Space 1
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tween the CS4610/11 and the host. Table 2. CS4610/11 PCI Configuration Space 1 (Continued)
uration (CS4610/11 plus an AC’97 Codec).
2.822 MHz SCLK output from the CS423x is selected
as the CS4610/11 PLL clock generator input. CS4610/11 final output to the CS423x DACs.
16.9344 MHz
Figure 9. CS4610/11 + CS423x Connection Diagram
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LRCLK, and MCLK runs at 384× the frame rate. tion are summarized in Table 4. as the source to the PLL for internal clock generation. cates right channel data. Frame is sampled on the falling edge of the SCLK input. CS423x device. The serial data on this pin transitions on the rising edge of the SCLK input. output data. The serial data on this pin is sampled on the falling edge of the SCLK input. Table 3. Serial Audio Port Signal Summary for CS4610/11 + CS423x Configuration Figure 10. Serial Audio Port Format for CS4610/11 + CS423x Configuration
ing. Also functions as the source to the PLL for internal clock generation. falling edge of the SCLK input. serial data on these pins transition on the falling edge of the SCLK input. Table 4. Serial Audio Port Signal Summary for CS4610 + CS423x Expanded Output Configuration Figure 11. CS4610 + CS423x Expanded 6-Channel Output Configuration
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not supported in this configuration. face to allow connection of external MIDI devices. FIFOs for the MIDI transmit and receive paths. schematic is illustrated in Figure 14. default is the CS4610/11 + CS423x configuration). BIOS code or by using the external EEPROM. Figure 12. Serial Audio Port Format for CS4610 + CS423x Expanded Output Configuration.
12.288 MHz
24.576 MHz AC'97 Codec
Figure 13. CS4610/11 - AC ‘97 Codec Connection Diagram Figure 14. Joystick Logic
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crements by one until a stop condition is detected. for other specific functions in a given application. Figure 15. External EEPROM Connection Figure 16. External EEPROM Read Access Sequence
CrystalClear™ SoundFusion™ PCI Audio Accelerator PIN DESCRIPTIONS 100-pin MQFP INTA# 81 RST# 82 PCICLK 83 GNT# 84 REQ# 85 PCIVDD[0] 86 PCIGND[0] 87 AD[31] 88 AD[30] 89 AD[29] 90 AD[28] 91 AD[27] 92 PCIGND[1] 93 PCIVDD[1] 94 AD[26] 95 AD[25] 96 AD[24] 97 C/BE[3]# 98 IDSEL 99 PCIVDD[2] 100 TEST 51 JACX 52 JACY 53 JBCX 54 JBCY 55 JAB1/SDO2 56 JAB2/SDO3 57 JBB1/LRCLK 58 JBB2/MCLK 59 MIDIIN 60 CVDD[2] 61 CGND[2] 62 MIDIOUT 63 CVDD[3] 64 CGND[3] 65 SDIN2/GPIO 66 CGND[4] 67 CVDD[4] 68 CRYVDD 69 VOLUP/XTALI 70 VOLDN/XTALO 71 CRYGND 72 VDD5REF 73 ABITCLK/SCLK 74 ASDOUT/SDOUT 75 ASDIN/SDIN 76 ASYNC/FSYNC 77 ARST# 78 EECLK/GPOUT 79 EEDAT/GPIO2 80
30 PCIGND[5]
29 AD[14]
28 AD[15]
27 C/BE[1]#
26 PAR
25 SERR#
24 PERR#
23 STOP#
22 PCIGND[4]
21 PCIVDD[4]
20 DEVSEL#
19 CVDD[0]
18 CGND[0]
17 TRDY#
16 IRDY#
15 FRAME#
14 C/BE[2]#
13 CGND[1]
12 CVDD[1]
11 AD[16]
10 AD[17]
9 AD[18]
8 PCIVDD[3]
7 PCIGND[3]
6 AD[19]
5 AD[20]
4 AD[21]
3 AD[22]
2 AD[23]
1 PCIGND[2]
50 PCIVDD[7]
49 PCIGND[7]
48 AD[0]
47 AD[1]
46 AD[2]
45 AD[3]
44 AD[4]
43 AD[5]
42 AD[6]
41 AD[7]
40 PCIGND[6]
39 PCIVDD[6]
38 C/BE[0]#
37 AD[8]
36 AD[9]
35 AD[10]
34 AD[11]
33 AD[12]
32 AD[13]
31 PCIVDD[5]
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CrystalClear™ SoundFusion™ PCI Audio Accelerator 103 104 105 106 107 108 INTA# 109 RST# 110 PCICLK 111 GNT# 112 REQ# 113 PCIVDD[0] 114 PCIGND[0] 115 AD[31] 116 AD[30] 117 AD[29] 118 AD[28] 119 AD[27] 120 PCIGND[1] 121 PCIVDD[1] 122 AD[26] 123 AD[25] 124 AD[24] 125 C/BE[3]# 126 IDSEL 127 PCIVDD[2] 128 TEST 65 JACX 66 JACY 67 JBCX 68 JBCY 69 JAB1/SDO2 70 JAB2/SDO3 71 JBB1/LRCLK 72 JBB2/MCLK 73 MIDIIN 74 CVDD[2] 75 CGND[2] 76 MIDIOUT 77 CVDD[3] 78 CGND[3] 79 SDIN2/GPIO 88 CGND[4] 89 CVDD[4] 90 CRYVDD 91 VOLUP/XTALI 92 VOLDN/XTALO 93 CRYGND 94 VDD5REF 95 ABITCLK/SCLK 96 ASDOUT/SDOUT 97 ASDIN/SDIN 98 ASYNC/FSYNC 99 ARST# 100 EECLK/GPOUT 101 EEDAT/GPIO2 102
38 PCIGND[5]
37 AD[14]
36 AD[15]
35 C/BE[1]#
34 PAR
33 SERR#
32 PERR#
31 STOP#
30 PCIGND[4]
29 PCIVDD[4]
28 DEVSEL#
27 CVDD[0]
26 CGND[0]
25 TRDY#
24 IRDY#
58 PCIVDD[7]
57 PCIGND[7]
56 AD[0]
55 AD[1]
54 AD[2]
53 AD[3]
52 AD[4]
51 AD[5]
50 AD[6]
49 AD[7]
48 PCIGND[6]
47 PCIVDD[6]
46 C/BE[0]#
45 AD[8]
44 AD[9]
43 AD[10]
42 AD[11]
41 AD[12]
40 AD[13]
39 PCIVDD[5]
CrystalClear™ SoundFusion™ PCI Audio Accelerator Note: A ‘#’ sign suffix on a pin names indicates an active-low signal. PCI Interface AD[31:0] - Address/Data Bus, I/O These pins form the multiplexed address / data bus for the PCI interface. C/BE[3:0]# - Command Type / Byte Enables, I/O (M) pins 98, 14, 27, 38; (Q) pins 126, 14, 35, 46 These four pins are the multiplexed command / byte enables for the PCI interface. During the address phase of a transaction, these pins indicate cycle type. During the data phases of a transaction, active low byte enable information for the current data phase is indicated. These pins are inputs during slave operation and they are outputs during bus mastering operation. PAR - Parity, I/O (M) pin 26; (Q) pin 34 The Parity pin indicates even parity across AD[31:0] and C_BE[3:0] for both address and data phases. The signal is delayed one PCI clock from either the address or data phase for which parity is generated. FRAME# - Cycle Frame, I/O - Active Low (M) pin 15; (Q) pin 15 FRAME# is driven by the current PCI bus master to indicate the beginning and duration of a transaction. IRDY# - Initiator Ready, I/O (M) pin 16; (Q) pin 24 IRDY# is driven by the current PCI bus master to indicate that as the initiator it is ready to transmit or receive data (complete the current data phase). TRDY# - Target Ready, I/O (M) pin 17; (Q) pin 25 TRDY# is driven by the current PCI bus target to indicate that as the target device it is ready to transmit or receive data (complete the current data phase). STOP# - Transition Stop, I/O (M) pin 23; (Q) pin 31 STOP# is driven active by the current PCI bus target to indicate a request to the master to stop the current transaction. IDSEL - Initialize Device Select, Input (M) pin 99; (Q) pin 127 IDSEL is used as a chip select during PCI configuration read and write cycles.
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CrystalClear™ SoundFusion™ PCI Audio Accelerator DEVSEL# - Device Select, I/O (M) pin 20; (Q) pin 28 DEVSEL# is driven by the PCI bus target device to indicate that it has decoded the address of the current transaction as its own chip select range. REQ# - Master Request, Three-State Output (M) pin 85; (Q) pin 113 REQ# indicates to the system arbiter that this device is requesting access to the PCI bus. This pin is high-impedance when RST# is active. GNT# - Master Grant, Input (M) pin 84; (Q) pin 112 GNT# is driven by the system arbiter to indicate to the device that the PCI bus has been granted. PERR# - Parity Error, I/O (M) pin 24; (Q) pin 32 PERR# is used for reporting data parity errors on the PCI bus. SERR# - System Error, Open Drain Output (M) pin 25; (Q) pin 33 SERR# is used for reporting address parity errors and other catastrophic system errors. INTA# - Host Interrupt A (for SP), Open Drain Output (M) pin 81; (Q) pin 109 INTA# is the level triggered interrupt pin dedicated to servicing internal device interrupt sources. PCICLK - PCI Bus Clock, Input (M) pin 83; (Q) pin 111 PCICLK is the PCI bus clock for timing all PCI transactions. All PCI synchronous signals are generated and sampled relative to the rising edge of this clock. RST# - PCI Device Reset (M) pin 82; (Q) pin 110 RST# is the PCI bus master reset. VDD5REF: Clean 5 V Power Supply (M) pin 73; (Q) pin 95 VDD5REF is the power connection pin for the 5 V PCI pseudo supply for the PCI bus drivers.
CrystalClear™ SoundFusion™ PCI Audio Accelerator PCIVDD[7:0] - PCI Bus Driver Power Supply (M) pins 50, 39, 31, 21, 8, 100, 94, 86; (Q) pins 58, 47, 39, 29, 8, 128, 122, 114 PCIVDD pins are the PCI driver power supply pins. PCIGND[7:0] - PCI Bus Driver Ground Pins (Q) pins 57, 48, 38, 30, 7, 1, 121, 115 PCIGND pins are the PCI driver ground reference pins. External Interface Pins TEST - Test Mode Strap, Input (M) pin 51; (Q) pin 65 This pin is sampled at reset for test mode entry. If it is high at reset, test mode is enabled. This pin should normally be pulled to ground in a production design. EEDAT/GPIO2 - External EEPROM Data / General Purpose I/O Pin 2, I/O Drain (M) pin 80; (Q) pin 102 Data line for external serial EEPROM containing device configuration data. When used with an external EEPROM, a 4.7 k Ω pullup resistor is required. In designs without EEPROM requirements, this pin can be used as a general purpose input or open drain output. EECLK/GPOUT - External EEPROM Clock / General Purpose Output Pin, Output (M) pin 79; (Q) pin 101 Clock line for external serial EEPROM containing device configuration data. In designs without EEPROM requirements, this pin can be used as a general purpose output pin. SDIN2/GPIO - Serial Data Input 2 / General Purpose I/O Pin, I/O (M) pin 66; (Q) pin 88 This dual function pin defaults as a general purpose I/O pin. In non-AC’97 system configurations, this pin can function as a second stereo digital data input pin if enabled. VOLUP/XTALI - Volume Up Button / Crystal Input, Input (M) pin 70; (Q) pin 92 This dual function pin is either the volume up button control input or the crystal oscillator input pin, depending on system configuration. When a crystal is used, it must designed for fundamental mode, parallel resonant. This pin may also be used as a general purpose input if its primary function is not needed. VOLDN/XTALO - Volume Down Button / Crystal Output, I/O (M) pin 71; (Q) pin 93 This dual function pin is either the volume down button control input or the crystal oscillator output pin, depending on system configuration. This pin may also be used as a general purpose input if its primary function is not needed.
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CrystalClear™ SoundFusion™ PCI Audio Accelerator Clock / Miscellaneous CRYVDD - Crystal & PLL Power Supply (M) pin 69; (Q) pin 91 Power pin for crystal oscillator and internal phase locked loop. CRYGND - Crystal & PLL Ground Supply (M) pin 72; (Q) pin 94 Ground pin for crystal oscillator and internal phase locked loop. JACX, JACY, JBCX, JBCY - Joystick A and B X/Y Coordinates, I/O (M) pins 52, 53, 54, 55; (Q) pins 66, 67, 68, 69 These pins are the 4 axis coordinates for the joystick port. These pins may also be used as a general purpose inputs or open drain outputs if their primary function is not needed. JAB1/SDO2 - Joystick A Button 1 / Serial Data Output 2, I/O (M) pin 56; (Q) pin 70 This dual function pin defaults as JAB1 (button 1 input for joystick A). In non-AC’97 system configurations, this pin can function as a second stereo digital data output pin if enabled. This pin can also be a general purpose polled input if a second data output stream is not required. JAB2/SDO3 - Joystick A Button 2 / Serial Data Output 3, I/O (M) pin 57; (Q) pin 71 This dual function pin defaults as JAB2 (button 2 input for joystick A). In non-AC’97 system configurations, this pin can function as a third stereo digital data output pin if enabled. This pin can also be a general purpose polled input if a third data output stream is not required. JBB1/LRCLK - Joystick B Button 1 / L/R Framing Clock, I/O (M) pin 58; (Q) pin 72 This dual function pin defaults as JBB1 (button 1 input pin for joystick B). In non-AC’97 system configurations, this pin can function as an alternate framing clock output pin for SDO2 and SDO3. This pin can also be used as a general purpose polled input if alternate data output streams are not required. JBB2/MCLK - Joystick B Button 2 / Master Clock, I/O (M) pin 59; (Q) pin 73 This dual function pin defaults as JBB2 (button 2 input pin for joystick B). In non-AC’97 system configurations, this pin can function as a master (256x sample rate) output clock if enabled. This pin can also be used as a general purpose polled input if alternate data output streams are not required. MIDIIN - MIDI Data Input (M) pin 60; (Q) pin 74 This is the serial input pin for the internal MIDI port.
CrystalClear™ SoundFusion™ PCI Audio Accelerator MIDIOUT - MIDI Data Output (M) pin 63; (Q) pin 77 This is the serial output pin for the internal MIDI port. CVDD[4:0] - Core Power Supply (M) pins 68, 64, 61, 12, 19; (Q) pins 90, 78, 75, 12, 27 Core / Stream Processor power pins. CGND[4:0] - Core Ground Supply (M) pins 67, 65, 62, 13, 18; (Q) pins 89, 79, 76, 13, 26 Core / Stream Processor ground reference pins. Serial Codec Interface ABITCLK/SCLK - AC ‘97 Bit Rate Clock / Serial Audio Data Clock, I/O (M) pin 74; (Q) pin 96 Master timing clock for serial audio data. In AC’97 configurations, this pin is an input which drives the timing for the AC’97 interface, along with providing the source clock for the PLL. In CS423x (ISA Codecs) digital link configurations, this pin is an input for the SCLK from the CS423x DSP port. ASYNC/FSYNC - AC ‘97 Frame Sync / Serial Audio Frame Sync, O/I (M) pin 77; (Q) pin 99 Framing clock for serial audio data. In AC’97 configurations, this pin is an output which indicates the framing for the AC’97 link. In CS423x digital link configurations, this pin is an input for the FSYNC from the CS423x’s DSP port. ASDOUT/SDOUT - AC ‘97 Data Out / Serial Audio Data Out, Output (M) pin 75; (Q) pin 97 Serial audio output data. ASDIN/SDIN - AC ‘97 Data In / Serial Audio Data In, Input (M) pin 76; (Q) pin 98 Serial audio input data. ARST# - AC ‘97 Reset, Output (M) pin 78; (Q) pin 100 AC’97 link reset pin. This pin also functions as a general purpose reset output in non-AC’97 configurations and will follow RST# pin 82 to ground, but must be forced high by software.
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CrystalClear™ SoundFusion™ PCI Audio Accelerator MECHANICAL DRAWINGS ‘M’ Package 100-pin MQFP E D1D e L B A INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.000 0.134 0.000 3.400 A1 0.010 0.014 0.250 0.350 B 0.009 0.015 0.220 0.380 D 0.667 0.687 16.950 17.450 D1 0.547 0.555 13.900 14.100 E 0.904 0.923 22.950 23.450 E1 0.783 0.791 19.900 20.100 e 0.022 0.030 0.550 0.750 ∝ 0.000 7.000 0.000 7.00 L 0.018 0.030 0.450 0.750
CrystalClear™ SoundFusion™ PCI Audio Accelerator INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.000 0.063 0.000 1.600 A1 0.002 0.006 0.050 0.150 B 0.007 0.011 0.170 0.270 D 0.626 0.634 15.900 16.100 D1 0.547 0.555 13.900 14.100 E 0.862 0.870 21.900 22.100 E1 0.783 0.791 19.900 20.100 e 0.016 0.024 0.400 0.600 ∝ 0.000 7.000 0.000 7.000 L 0.018 0.030 0.450 0.750 ‘Q’ Package 128-pin TQFP E D1D e L B A