CS4525

CS4525 CIRRUS | Alldatasheet

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Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) http://www.cirrus.com Advance Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

30 W Digital TV Amplifier with Integrated ADC

Digital Amplifier Features ! Fully Integrated Power MOSFETs ! No Heatsink Required Programmable Power Foldback on Thermal Warning High Efficiency (85%) ! > 100 dB Dynamic Range ! < 0.1% THD+N @ 1 W ! Configurable Outputs (10% THD+N) 1 x 30 W into 4 Ω, Parallel Full-Bridge 2 x 15 W into 8 Ω, Full-Bridge 2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W into 8 Ω, Full-Bridge ! Built-In Protection with Error Reporting Overcurrent/Undervoltage/Thermal Overload Shutdown Thermal Warning Reporting ! PWM Popguard® for Half-Bridge Mode ! Click Free Start-Up ! Programmable Channel Delay for System Noise & Radiated Emissions Management ADC Features ! Stereo, 24-bit, 48 kHz Conversion ! Multi-bit Architecture ! 95 dB Dynamic Range (A-wtd) ! -88 dB THD+N ! 2 Vrms Input Supports SCART System Features ! Asynchronous 2-Channel Digital Serial Port ! 32 kHz to 96 kHz Input Sample Rates ! Operation with On-Chip Oscillator Driver or Applied SYS_CLK at 18.432, 24.576 or

27.000 MHz

! Integrated Sample Rate Converter (SRC) Eliminates Clock-Jitter Effects Input Sample Rate Independent Operation Simplifies System Integration ! Spread Spectrum PWM Modulation Reduces EMI Radiated Energy ! Low Quiescent Current (Features continued on page 2) VP Amplifier Out 1 Amplifier Out 2 PGND Amplifier Out 3 Amplifier Out 4 Stereo Analog In PWM Modulator Output 2 PWM Modulator Output 1 Gate Drive Gate Drive Gate Drive Gate Drive Multi-bit ∆Σ Modulator with Integrated Sample Rate Converter Audio Processing Parametric EQ High-Pass Bass/Treble Adaptive 2-Ch Mixer

2.1 Bass Mgr

Clocks & Data Serial Audio Data I/O Serial Audio Clocks & Data Serial Audio Input Port Multi-bit ∆Σ ADC Volume Crystal Driver I/O System Clock Crystal Oscillator Driver Register /Hardware Configuration I²C or Hardware Configuration Reset Interrupt Error Protection Thermal Warning Over Current Thermal Feedback Under Voltage HP Detect/Mute PWM

2.5 V to 5 V

10.5 V to 18 V

AUGUST '06 DS726A1 CS4525

Software Mode System Features ! Digital Audio Processing

3 Programmable Parametric EQ Filters for

2 Programmable Parametric EQ Filters for

Selectable High-Pass Filter Bass/Treble Tone Control Adaptive Loudness Compensation 2-Channel Mixer

2.1 Bass Management

24 dB/octave Linkwitz-Riley Crossover Filters De-emphasis for 32 kHz, 44.1 kHz, 48 kHz ! Selectable Serial Audio Interface Formats Left-Justified up to 24-bit I²S up to 24-bit Right-Justified 16-, 18-, 20-, 24-bits ! Digital Serial Connection to Additional CS4525 or DACs for Subwoofer ! Digital Interface to External Lip-Sync Delay ! PWM Switch Rate Shifting Eliminates AM Frequency Interference ! Digital Volume Control with Soft ramp +24 to -103 dB in 0.5 dB steps ! Programmable Peak Detect and Limiter ! Flexible Power Output Configurations ! Thermal Foldback for Interruption-Free Power-Stage Protection Supports Internal and External Power Stages ! Operation from On-Chip Oscillator Driver or Applied Systems Clock ! Supports I²C® Host Control Interface Hardware Mode System Features ! 2-Channel Stereo Full-Bridge Power Outputs ! Analog and Digital Inputs ! I²S and Left-Justified Serial Input Formats ! Thermal Foldback for Interruption-Free Protection of Internal Power Stage ! Operation from Applied Systems Clock ! External Mute Input Common Applications ! Integrated Digital TV’s ! Flat Panel TV Monitors ! Computer/TV Monitors ! Mini/Micro Shelf Systems ! Digital Powered Speakers ! Portable Docking Stations ! Computer Desktop Audio General Description The CS4525 is a stereo analog or digital input PWM high efficiency Class D amplifier audio system with an integrated stereo analog-to-digital (A/D) converter. The stereo power amplifiers can deliver up to 15 W per channel into 8 Ω speakers from a small space saving 48-pin QFN package. The PWM amplifier can achieve greater than 85% efficiency and the package is thermal- ly enhanced for optimal heat dissipation which eliminates the need for a heatsink. The power stage outputs can be configured as two full- bridge channels for 2 x 15 W operation, two half-bridge channels and one full-bridge channel for 2 x 7 W + 1 x 15 W operation, or one parallel full-bridge channel for 1 x 30 W operation. The CS4525 integrates on-chip over-current, under-voltage, over-temperature protection and error reporting as well as a thermal warn- ing indicator and programmable foldback of the output power to allow cooling. The main digital serial port on the CS4525 can support asynchronous operation with the integrated on-chip sample rate converter (SRC) which eases system inte- gration. The SRC allows for a fixed PWM switching frequency regardless of incoming sample rate as well as optimal clocking for the A/D modulators. An on-chip oscillator driver eliminates the need for an external crystal oscillator circuit, reducing overall design cost and conserving circuit board space. The CS4525 automatically uses the on-chip oscillator driver in the absence of an applied master clock. The CS4525 is available in a 48-pin QFN package in Commercial grade (-10° to +70° C). The CRD4525 Cus- tomer Reference Design is also available. Please refer to “Ordering Information” on page 90 for complete ordering information.

1. PIN DESCRIPTIONS - SOFTWARE MODE Pin Name Pin # Pin Description INT Interrupt (Output) - Indicates an interrupt condition has occurred. SCL Serial Control Port Clock (Input) - Serial clock for the I²C control port. SDA Serial Control Data (Input/Output) - Bi-directional data I/O for the I²C control port. LRCK Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. SCLK Serial Clock (Input) - Serial bit clock for the serial audio interface. SDIN Serial Audio Data Input (Input) - Input for two’s complement serial audio data. HP_DETECT/ MUTE Headphone Detect / Mute (Input) - Headphone detection or mute input signal. RST Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when this pin is driven low. Top-Down (Through Package) View 48-Pin QFN Package INT SCL SDA LRCK SCLK SDIN HP_DETECT/MUTE RST LVD DGND VD_REG VD VP OUT1 PGND PGND OUT2 VP VP OUT3 PGND PGND OUT4 VP VA_REG AGND FILT+ VQ AFILTL AFILTR AINL AINR OCREF PGND PGND RAMP_CAP XTI XTO SYS_CLK AUX_LRCK/AD0 AUX_SCLK AUX_SDOUT DLY_SDIN/EX_TWR DLY_SDOUT PWM_SIG1 PWM_SIG2 PGND PGND CS4525

VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying 5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be DGND. DGND Digital Ground (Input) - Ground for the internal logic and digital I/O. VD_REG Core Logic Power (Output) - Internally generated low voltage power supply for digital logic. VD Power (Input) - Positive power supply for the internal regulators and digital I/O. VA_REG Analog Power (Output) - Internally generated positive power for the analog section and I/O. AGND Analog Ground (Input) - Ground reference for the internal analog section and I/O. FILT+ Positive Voltage Reference (Output) - Positive reference voltage for the internal ADC sampling circuits. VQ Common Mode Voltage (Output) - Filter connection for internal common mode voltage. AFILTL AFILTR Antialias Filter Connection (Output) - Antialias filter connection for ADC inputs. AINL AINR Analog Input (Input) - The full-scale input level is specified in the ADC Analog Characteristics specification table. OCREF Over Current Reference Setting (Input) - Sets the reference for over current detection. PGND 22,23 27,28 33,34 37,38 Power Ground (Input) - Ground for the individual output power half-bridge devices. RAMP_CAP Output Ramp Capacitor (Input) - Used for shaping the output ramp time for half-bridge configured outputs. VP 25,30, 31,36 High Voltage Power (Input) - High voltage power supply for the individual half-bridge devices. OUT4 OUT3 OUT2 OUT1 PWM Output (Output) - Amplified PWM power outputs. PWM_SIG2 PWM_SIG1 PWM Output (Output) - PWM switching signals. DLY_SDOUT Delay Serial Audio Data Out (Output) - Output for two’s complement serial audio data. Default pin configuration. DLY_SDIN/ EX_TWR Delay Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Default pin configuration. External Thermal Warning (Input) - Input for an external thermal warning signal. Configurable via the I²C control port. AUX_SDOUT Auxiliary Port Serial Audio Data Out (Output) - Output for two’s complement auxiliary port serial data. AUX_SCLK Auxiliary Port Serial Clock (Output) - Serial clock for the auxiliary port serial interface. AUX_LRCK/ AD0 Auxiliary Port Left Right Clock (Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. AD0 (Input) - Sets the LSB of the I²C device address. Sensed on the release of RST. SYS_CLK System Clock (Input/Output) -Clock source for the internal logic, processing, and modulators. XTO Crystal Oscillator Output (Output) - Crystal oscillator driver output. XTI Crystal Oscillator Input (Input) - Crystal oscillator driver input.

1. PIN DESCRIPTIONS - HARDWARE MODE Pin Name Pin # Pin Description CLK_FREQ0 CLK_FREQ1 Clock Frequency (Input) - Determines the frequency of the clock expected to be driven into the SYS_CLK pin. ADC/SP ADC/Serial Port (Input) - Selects between the Analog to Digital Converter and the Serial Port for audio input. Selects the ADC when high or the serial port when low. LRCK Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. SCLK Serial Clock (Input) - Serial bit clock for the serial audio interface. SDIN Serial Audio Data Input (Input) - Input for two’s complement serial audio data. MUTE Mute (Input) - Mute input signal. RST Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when this pin is driven low. Top-Down (Through Package) View 48-Pin QFN Package CLK_FREQ0 CLK_FREQ1 ADC/SP LRCK SCLK SDIN MUTE RST LVD DGND VD_REG VD VP OUT1 PGND PGND OUT2 VP VP OUT3 PGND PGND OUT4 VP VA_REG AGND FILT+ VQ AFILTL AFILTR AINL AINR OCREF PGND PGND RAMP_CAP TSTI TSTO SYS_CLK I2S/LJ EN_TFB ERROC ERRUVTE TWR PWM_SIG1 PWM_SIG2 PGND PGND CS4525

VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying 5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be con- nected to DGND. DGND Digital Ground (Input) - Ground for the internal logic and I/O. VD_REG Core Logic Power (Output) - Internally generated low voltage power supply for digital logic. VD Digital Power (Input) - Positive power supply for the internal regulators and digital I/O. VA_REG Analog Power (Output) - Internally generated positive power for the analog section and I/O. AGND Analog Ground (Input) - Ground reference for the internal analog section and I/O. FILT+ Positive Voltage Reference (Output) - Positive reference voltage for the internal ADC sampling circuits. VQ Common Mode Voltage (Output) - Filter connection for internal common mode voltage. AFILTL AFILTR Antialias Filter Connection (Output) - Antialias filter connection for ADC inputs. AINL AINR Analog Input (Input) - The full-scale input level is specified in the ADC Analog Characteristics specification table. OCREF Over Current Reference Setting (Input) - Sets the reference for over current detection. PGND 22,23 27,28 33,34 37,38 Power Ground (Input) - Ground for the individual output power half-bridge devices. RAMP_CAP Output Ramp Capacitor (Input) - Used for shaping the output ramp time for half-bridge configured outputs. VP 25,30, 31,36 High Voltage Power (Input) - High voltage power supply for the individual half-bridge devices. OUT4 OUT3 OUT2 OUT1 PWM Output (Output) - Amplified PWM power outputs. PWM_SIG2 PWM_SIG1 PWM Output (Output) - PWM switching signals. TWR Thermal Warning Output (Output) - Thermal warning output. ERRUVTE Thermal and Undervoltage Error Output (Output) - Error flag for thermal shutdown and under- voltage. ERROC Overcurrent Error Output (Output) - Overcurrent error flag. EN_TFB Enable Thermal Feedback (Input) - Enables the thermal foldback feature when high. I2S/LJ I²S/Left Justified (Input) - Selects between I²S and Left-Justified data format for the serial input and output ports. Selects I²S when high and LJ when low. SYS_CLK System Clock (Input/Output) -Clock source for the delta-sigma modulators. TSTO Test Output (Output) - This pin is an output used for the crystal oscillator driver available only in software mode. It must be left unconnected for normal hardware mode operation. TSTI Test Input (Input) - This pin is an input used for the crystal oscillator driver available only in soft- ware mode. It must be tied to digital ground for normal hardware mode operation.

The logic level for each input is set by its corresponding power supply and should not exceed the maximum ratings.

2.5 V, CMOS

Table 1. I/O Power Rails

1. TYPICAL CONNECTION DIAGRAMS

24.576 MHz

Figure 1. Typical Connection Diagram - Software Mode

18.432 MHz

Figure 2. Typical Connection Diagram - Hardware Mode

1. TYPICAL SYSTEM CONFIGURATION DIAGRAMS

27 MHz

Figure 3. Typical System Configuration 1 Figure 4. Typical System Configuration 2

Figure 5. Typical System Configuration 3

Figure 6. Typical System Configuration 4

1. CHARACTERISTIC AND SPECIFICATION TABLES (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND = DGND=PGND=0 V, all voltages with respect to ground.) ABSOLUTE MAXIMUM RATINGS (AGND = DGND = PGND = 0 V; all voltages with respect to ground.) Notes: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. The maximum over/under voltage is limited by the input current. Parameters Symbol Min Nom Max Units DC Power Supply Digital and Analog Core VD 2.375 2.5 2.625 V VD 3.135 3.3 3.465 V VD 4.75 5.0 5.25 V Amplifier Outputs VP 10.5 18.0 V Temperature Ambient Temperature Commercial TA -10 +70 Junction Temperature TJ +150 Parameters Symbol Min Max Units DC Power Supply PWM Outputs Digital and Analog Core VP VD -0.3 -0.3 20.0 6.0 V V Input Current (Note 2) Iin ±10 mA Analog Input Voltage (Note 3) VINA AGND-0.7 VA_REG + 0.7 V Digital Input Voltage (Note 3) VIND -0.3 VD + 0.4 V Ambient Operating Temperature - Power Applied Commercial TA -20 +85 Storage Temperature Tstg -65 +150

ANALOG INPUT CHARACTERISTICS Test Conditions (unless otherwise specified): Input Signal: 1 kHz sine wave through the recommended passive input filter shown in Figure 27 on page 56; Sample Frequency = 48 kHz, 10 Hz to 20 kHz Measurement Bandwidth. Power outputs in power-down state (PDnOut1 = 1, PDnOut2 = 1, PDnOut3/4 = 1). Notes: Referred to the typical full-scale voltage. Measured between AINx and AGND. ADC DIGITAL FILTER CHARACTERISTICS Notes: Filter response is clock dependent and scales with the ADC sampling frequency (Fs). With a 27.000 MHz or 24.576 MHz XTAL/SYS_CLK, Fs is equal to the applied clock divided by 512. With an 18.432 MHz XTAL/SYS_CLK, Fs is equal to the applied clock divided by 384. Parameter Min Typ Max Unit Analog In to ADC Dynamic Range (Note 4) A-weighted unweighted dB dB Total Harmonic Distortion + Noise -1 dB -20 dB -60 dB -88 -75 -35 -82 dB dB dB DC Accuracy Interchannel Gain Mismatch 0.1 dB Gain Drift ±100 ppm/°C Input Interchannel Isolation dB Full-scale Input Voltage 1.96 2.18 2.40 Vpp Input Impedance (Note 5) kΩ Parameter Min Typ Max Unit Passband (Frequency Response) (Note 6) to -0.1 dB corner 0.4948 Fs Passband Ripple -0.09 dB Stopband (Note 6) 0.6677 Fs Stopband Attenuation 48.4 dB Total Group Delay 2.7/Fs s High-Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB 3.7 24.2 Hz Hz Phase Deviation 20 Hz Deg Passband Ripple 0.17 dB Filter Settling Time 105/Fs s

PWM POWER OUTPUT CHARACTERISTICS AGND = DGND = PGND = 0 V; All voltages with respect to ground; VP = 18 V; RL = 8 Ω for full-bridge, RL = 4 Ω for half-bridge and parallel full-bridge; PWM Switch Rate = 384 kHz; 10 Hz to 20 kHz Measurement Bandwidth; Per- formance measurements taken with a full scale 997 Hz sine wave and AES17 filter; Unless otherwise specified. Parameters Symbol Conditions Min Typ Max Units Power Output per Channel Stereo Full-Bridge Half-Bridge Parallel Full-Bridge PO THD+N < 10% THD+N < 1% THD+N < 10% THD+N < 1% THD+N < 10% THD+N < 1% 5.5 23.5 W W W W W W Total Harmonic Distortion + Noise Stereo Full-Bridge Half-Bridge Parallel Full-Bridge THD+N PO = 1 W PO = 0 dBFS = 11.3 W PO = 1 W PO = 0 dBFS = 5.0 W PO = 1 W PO = 0 dBFS = 22.6 W 0.1 0.3 0.1 0.3 0.1 0.3 Dynamic Range Stereo Full-Bridge Half-Bridge Parallel Full-Bridge DYR PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted 102 102 102 dB dB dB dB dB dB MOSFET On Resistance RDS(ON) Id = 0.5 A, TJ = 50°C 518 615 mΩ Efficiency h PO = 2 x 11.3 W, RL = 8 Ω Minimum Output Pulse Width PWmin No Load ns Rise Time of OUTx tr Resistive Load ns Fall Time of OUTx tf Resistive Load ns PWM Output Over-Current Error Trip Point ICE TA = 25°C, OCREF = 20 kΩ 2.0 A Junction Thermal Warning Trip Point TTW 120 Junction Thermal Error Trip Point TTE 140 VP Under-Voltage Error Trip Point VUV TA = 25°C V Ramp-Up Time - Half-Bridge Configuration TRU Capacitor = 1000 µF 0.8 s Ramp-Down Time- Half-Bridge Configuration TRD Capacitor = 1000 µF s

After powering up the CS4525, RST should be held low until the power supplies and clocks are stable. Figure 7. Serial Audio Input Port Timing

FCLK is the frequency of the applied crystal or the input SYS_CLK signal. TCLK = 1/FCLK.

1. May vary during normal operation.
2. FSCLKI is the frequency of the input SCLK signal. TSCLKI = 1/FSCLKI.

Figure 8. AUX Serial Port Interface Master Mode Timing

1. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

Figure 11. Control Port Timing - I²C

DC ELECTRICAL CHARACTERISTICS AGND = DGND = PGND = 0 V; All voltages with respect to ground; PWM switch rate = 384 kHz; Unless otherwise specified. Notes: 14. Normal operation is defined as RST = HI. 15. Power-Down Mode is defined as RST = LOW with all input lines held static. 16. The DC current drain represents the allowed current from the VQ pin due to typical leakage through the electrolytic de-coupling capacitors. 17. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will in- crease the PSRR. DIGITAL INTERFACE SPECIFICATIONS AGND = DGND = PGND = 0 V; All voltages with respect to ground; Unless otherwise specified. Parameters Min Typ Max Units Normal Operation (Note 14) Power Supply Current VD = 3.3 V mA Power Dissipation VD = 3.3 V mW Power-Down Mode (Note 15) Power Supply Current VD = 3.3 V 4.3 mA VD_REG Characteristics Nominal Voltage DC current source 2.25 2.5 2.75 V mA VA_REG Characteristics Nominal Voltage DC current source 2.25 2.5 2.75 V mA VQ Characteristics Nominal Voltage Output Impedance DC current source/sink (Note 16) 0.5•VA_REG V kΩ µA Filt+ Nominal Voltage VA_REG V Power Supply Rejection Ratio (Note 17) 1 kHz 60 Hz dB dB Parameters Symbol Min Max Units High-Level Input Voltage VIH 0.7*VD_REG VD V Low-Level Input Voltage VIL 0.20*VD_REG V High-Level Output Voltage Io=2 mA VOH 0.90*VD V Low-Level Output Voltage Io=2 mA VOL 0.2 V Input Leakage Current Iin ±10 uA Input Capacitance pF

6.1.2 Power-Up and Power-Down The CS4525 will remain in a completely powered-down state with the control port inaccessible until the RST pin is brought high. Once RST is high, the control port will be accessible, but all other internal blocks will remain powered-down until they are powered-up via the control port or until hardware mode is en- tered. When an external crystal is present on the XTI/XTO pins, software mode will be automatically entered 10 ms after the release of RST. If SYS_CLK is used as an input, software mode is entered by writing to the control port within 10 ms after the release of RST. If the control port is not written within this time, the device will begin to operate in hardware mode. 6.1.2.1 Recommended Power-Up Sequence Hold RST low until the power supplies and the input SYS_CLK (if used) are stable. Bring RST high. The device will remain in a low-power state and the control port will be accessible. The device will automatically enter software mode after 10 ms if an external crystal is present on the XTI/XTO pins, at which time the output SYS_CLK signal will become active. If SYS_CLK is used as an input, initiate a control port write to set the PDnAll bit in register 5Fh within 10 ms following the release of RST. This operation causes the device to enter software mode and places it in power-down mode. If the LVD pin is tied low and VD is connected to 2.5 V, clear the SelectVD bit in the Power Ctrl register to indicate the 2.5 V VD supply level. The desired register settings can be loaded while keeping the PDnAll bit set. Clear the PDnAll bit to initiate the power-up sequence. 6.1.2.2 Recommended Power-Down Sequence Set the PDnAll bit to power-down the device while eliminating audible pops. Bring RST low to bring the device’s power consumption to an absolute minimum. Remove power. 6.1.3 Input Source Selection The CS4525 can accept analog or digital audio input signals. Digital audio input signals are supplied through the serial audio input port as outlined in “Serial Audio Interfaces” on page 57. Analog audio input signals are supplied through the internal ADC as outlined in “Analog Inputs” on page 56. The input source is selected by the ADC/SP bit in the Input Config register. In software mode, the serial audio input port supports I²S, Left-Justified and Right-Justified data formats. The serial audio input port digital interface format is configured by the DIF[2:0] bits in the Input Config reg- ister. The CS4525 internal ADC includes a dedicated high-pass filter to remove any DC content from the ADC output signal prior to the internal ADC/serial audio input port input multiplexor. This high-pass filter can be bypassed by clearing the EnAnHPF bit. Referenced Control Register Location Referenced Control Register Location

adaptive loudness compensation, channel mixers, and volume controls. filter, will not cause a channel to clip. Figure 14. Digital Signal Flow

6.1.4.2 Digital Signal Processing High-Pass Filter The CS4525 includes a high-pass filter at the beginning of the digital signal processing chain to remove any DC content from the input signal prior to the remaining internal digital signal processing blocks. The high-pass filter operates by continuously subtracting a measure of the DC offset from the input signal and may be used regardless of the input data source. The digital signal processing high-pass filter can be disabled by clearing the EnDigHPF bit. 6.1.4.3 Channel Mixer The CS4525 implements independent channel mixers to provide for both mono mixes and channel swaps for the left and right channels. The channel mixers are controlled by the LChMix[1:0] and RChMix[1:0] bits in the Mixer Config register. To allow stereo headphone operation when a mono mix is configured, when the HP_DETECT/MUTE pin is configured for headphone detection (the HP/Mute bit is set), the operation of the left channel mixer is affected by the active state of the headphone detection input signal. In this configuration, when the left channel mixer is configured for a mono mix (LChMix[1:0] = 01 or 10) and the headphone detection input signal becomes active, the left channel mixer will be automatically reconfigured to output the left channel, thereby disabling the mono mix. When the headphone detection input signal becomes inactive, the mixer will be automatically reconfigured to operate as dictated by the LChMix[1:0] bits. It should be noted that the right channel mixer output is unaffected by the headphone detection input sig- nal and will always operate as dictated by the RChMix[1:0] bits. Referenced Control Register Location Referenced Control Register Location

DeEmph bit in the Tone Config register. in the Tone Config register. and TrebFc[1:0] bits in the Tone Config register. Note that the corner frequency of each filter set scales linearly with the input sample rate. and the corresponding shelving frequency corners are available. Table 2. Bass Shelving Filter Corner Frequencies Figure 15. De-Emphasis Filter

Table 3. Treble Shelving Filter Corner Frequencies

LFE channel generated by the bass manager. The filters are implemented in the bi-quad form shown below. value and x[n] represents the input sample value. the range of -3.99996 decimal (80 00 00 hex) to 3.99996 decimal (7F FF FF hex). ence” section beginning on page 61 for the specific register locations for each coefficient. plements a pass-through function. ister enables and disables parametric equalizers 4 and 5 for the LFE channel. Figure 16. Bi-Quad Filter Architecture

6.1.4.7 Adaptive Loudness Compensation The CS4525 includes adaptive loudness compensation to enhance the audibility of program material at low volume levels. The adaptive loudness compensation feature operates by varying the bass and treble boost of the tone control shelving filters as the volume level changes. The level of boost added to the shelving filters is determined by the average of the effective volume set- tings of channels A and B after the master volume control. As this average volume setting decreases from 0 dB, the boost of the bass and treble shelving filters is gradually increased until it reaches the maximum boost level of 12.0 dB. As the volume is increased, the boost applied due to the adaptive loudness com- pensation feature will be gradually removed until it reaches the level specified by the Treble[3:0] and Bass[3:0] bits in the Tone Control register. The adaptive loudness compensation feature is enabled by setting the Loudness bit in the Tone Config register. When the loudness feature is enabled, it immediately evaluates the effective average volume and applies bass and treble boost accordingly. When disabled, any treble or bass boost applied due to the loudness feature will be removed. Because the adaptive loudness compensation filter operates by adjusting the boost level of the tone con- trol shelving filters, it is necessary that they be enabled with the EnToneCtrl bit in the Tone Config register in order for the loudness feature to be operational. If the tone control filters are disabled, the adaptive loud- ness compensation feature will not be functional. Referenced Control Register Location

and summed to drive the LFE channel. figured with the BassMgr[2:0] bits in the EQ Config register. Note that the corner frequency of each filter set scales linearly with the input sample rate. and the corresponding shelving frequency corners are available. crossover is bypassed and no signal is presented on the LFE channel. ager will be automatically reconfigured to operate as dictated by the BassMgr[2:0] bits. Table 4. Bass Management Cross-Over Frequencies

6.1.4.9 Volume and Muting Control The CS4525’s volume control architecture provides the ability to control the level of each output channel on both an individual and master basis. Individual control allows the volume and mute state of a single channel to be changed independently from the other channels within the device. The CS4525 provides 3 individual volume and muting controls, each permanently assigned to one channel within the device. Each channel has a corresponding Ch X Vol register used to gain or attenuate the channel from +24 dB to -103 dB in 0.5 dB steps. Each output can be independently muted via the MuteChX bits in the Mute Control register. Master control allows the volume of all channels to be changed simultaneously by offsetting each chan- nel’s individual volume setting by +24 dB to -103 dB in 0.5 dB steps. Master volume control is accom- plished via the Master Vol register. The PWM outputs can be configured to output silence as a modulated signal or an exact 50% duty cycle signal during a mute condition. This selection is achieved via the Mute50/50 bit in the Volume Cfg register. The AutoMute bit in the same register dictates whether the device will automatically mute after the recep- tion of 8192 consecutive samples of static 0 or -1. When the AutoMute function is enabled, a single sam- ple of non-static data will cause the automatic mute to be released. The CS4525 implements soft-ramp and zero-crossing detection capabilities to provide noise-free level transitions. When the zero-crossing function is enabled, all volume and muting changes are made on an output signal zero-crossing. The zero-crossing detection function is implemented independently for each channel. When the soft-ramp function is enabled, the volume is ramped from its initial to its final level at a rate of ½ dB every 4 samples for 32, 44.1, and 48 kHz sample rates, and ½ dB every 8 samples for a 96 kHz sampling rate. All volume and muting changes are implemented as dictated by the soft-ramp and zero-cross settings configured by the SZCMode[1:0] bits in the Volume Cfg register. Referenced Control Register Location

by the soft ramp/zero cross settings and sample rate, Fs. slightly below the maximum threshold to cushion the sound as the limiter attacks and releases. limiter is in use. This behavior can be disabled by clearing the LimitAll bit in the Limiter Cfg 1 register. Figure 17. Peak Signal Detection & Limiting

When the LimitAll feature is activated, attenuation will be applied to all channels when a single channel exceeds the maximum threshold and released when the level of all channels is below the minimum threshold. When the LimitAll feature is de-activated, limiter attenuation will be applied and released on a per-channel basis and will only affect the channel on which the limiter event occurred. The limiter can be enabled by setting the EnLimiter bit in the Limiter Cfg register. Referenced Control Register Location

device to again achieve its full output power capability. below demonstrates the foldback process. overload condition has cleared. When the junction temperature crosses the thermal warning threshold, the foldback attack delay timer is started. once again, but the output volume level is not altered. The foldback algorithm then proceeds to step 3. Figure 18. Foldback Process

The AttackDly[1:0] bits in the Foldback Cfg register allow the foldback attack delay timeout period to be adjusted from approximately 0.5 seconds to approximately 2.0 seconds. The maximum attenuation ap- plied by the thermal foldback algorithm can be restricted to -30 dB by setting the EnFloor bit in the same register. The foldback adjustment lock feature causes the attenuation applied by the foldback algorithm to be main- tained after the foldback condition has subsided. The applied attenuation will continue to be applied until the master volume or all active channel volume controls are lowered below the foldback attenuation level, or until a subsequent foldback condition occurs causing the applied attenuation to be lowered further. If the foldback algorithm applies attenuation while this feature is enabled, when the feature is subsequently disabled, the applied attenuation will be gradually released as long as the temperature remains within the safe operating range. This foldback lock adjustment feature is enabled by the LockAdj bit in the Foldback Cfg register. Thermal warnings will only affect the foldback algorithm and cause attenuation to be applied when en- abled by the EnTherm bit in the Foldback Cfg register. The CS4525 can be configured to accept an external thermal warning indicator input. When in this con- figuration, an active input signal indicates that a thermal warning threshold has been exceeded. If thermal foldback is enabled, the foldback algorithm will respond as described above making no distinction be- tween an internal or external thermal warning condition. See “External Warning Input Port” on page 43 for more information. Referenced Control Register Location

to compensate for differences in the tweeter and mid-range/woofer sensitivity. bits in the Volume Cfg register. Note that the corner frequency of each filter set scales linearly with the input sample rate. and the corresponding shelving frequency corners are available. The 2-way crossover can be enabled by setting the En2Way bit in the Volume Cfg register. Table 5. 2-Way Cross-Over Frequencies

of the sources shown in the Digital Signal Flow diagram on page 29. is configured to output channels 1 and 2 on the auxiliary output data channels 1 and 2 respectively. enabled, the port operates as a master and clocks out data in the format dictated by the AuxI²S/LJ bits. When disabled, the AUX_LRCK, AUX_SCLK, and AUX_SDOUT pins continuously drive a logic ‘0’. Table 6. Auxiliary Serial Port Data Output

delay interface to operate properly. pletely disrupting the system’s operation. warning input to the foldback algorithm and the DLY_SDOUT pin becomes high-impedance. page 39 for more information. manage system switching noise. support stereo full-bridge, stereo half-bridge with full-bridge LFE, and mono parallel full-bridge output. Table 7. PWM Power Output Configurations

putCfg[1:0] bits while the device is powered-up will be ignored. Processing section and Figure 14 on page 29. Processing section and Figure 14 on page 29. Table 8. PWM Logic-Level Output Configurations

6.1.7.3 PWM PopGuard Transient Control The CS4525 uses PopGuard technology to minimize the effects of power-up and power-down output tran- sients commonly produced by half-bridge, single supply amplifiers implemented with external DC-block- ing capacitors connected in series with the audio outputs. PWM PopGuard operates by linearly ramping the PWM power outputs up to and down from their bias point of VP/2 when a channel is powered up and down respectively using the PDnOutX or PDnAll bits. This gradual voltage ramp minimizes output transients while the DC blocking capacitor is charged and discharged. The PWM PopGuard output ramp time can be varied from approximately 0.70 seconds to approximately 0.85 seconds and can be completely disabled via the RmpSpeed[1:0] bits in the Foldback Cfg register. All output channels are affected by the RmpSpeed[1:0] bits, and PWM PopGuard is disabled by default. Referenced Control Register Location

PWM switch rate shift feature. switch rate is lowered and the quantization levels are increased as shown in Table 9 below. Sample Rate Converters” on page 53. a mute state when the pin is active. page 35 for more information. PWM_SIG output pins will mute by outputting a non-modulated 50% duty cycle. In both configurations, the active logic input level is determined by the HP/MutePol bit. Table 9. PWM Output Switching Rates and Quantization Levels

6.1.9 Interrupt Reporting The CS4525 has comprehensive interrupt reporting capabilities. Many conditions including SRC lock, ADC overflow, digital data path overflow, and amplifier errors can cause an interrupt. The INT output pin is intended to drive an interrupt input pin on a host microcontroller. The INT pin is an open-drain active-low output and requires an external pull-up for proper operation. If an interrupt source is un-masked, its occurrence will cause the interrupt output pin to become active. To enhance flexibility, each interrupt source may be masked such that its occurrence does not cause the in- terrupt output pin to become active. This masking function is accomplished by clearing an interrupt’s re- spective mask bit located in the 4 LSB’s of the Interrupt register. When a specific interrupt condition occurs, it’s respective bit located in the 4 MSB’s of the Interrupt register will be set to indicate that a change has occurred for the associated interrupt type. When the interrupt reg- ister is read, the contents of the 4 MSB’s will be cleared. The Int Status register may then be read to de- termine the current state of the interrupt source. For specific information regarding interrupt types and reporting, see the Interrupt, Int Status and Amp Er- ror register descriptions. 6.1.10 Automatic Power Stage Shut-Down To prevent permanent damage, the CS4525 will automatically shut down its internal PWM power output stages when a thermal error, PWM power output over-current error, or VP under-voltage condition occurs. In the shut-down state, all digital functions of the device will operate as normal, however the PWM power output pins become high-impedance. The levels of the over-current error, thermal error, and VP under-voltage trip points are listed in the PWM Power Output Characteristics table on page 20. Automatic shut-down will occur whenever any of these preset thresholds are crossed. Once in the shut-down state, the PDnAll bit in the Power Ctrl register must be set and then cleared to resume normal device operation. Referenced Control Register Location Referenced Control Register Location

described in the following sections. All device configuration is achieved via hardware control input pins. ous internal filter coefficients. Specifications table on page 23 for complete input frequency range specifications. Figure 12 below demonstrates a typical clocking configuration using the SYS_CLK input. The CS4525 will remain in a completely powered-down state until the RST pin is brought high. Hold RST low until the power supplies and the input SYS_CLK signal are stable. Hardware mode will be entered after approximately 10 ms. Bring MUTE low to mute the device’s outputs and minimize audible pops. Bring RST low to halt the operation of the device. The device’s power consumption will be brought to an absolute minimum. Table 10. SYS_CLOCK Frequency Selection Figure 21. Typical SYS_CLK Input Clocking Configuration

ing any audible pops or clicks. interface format is selected by the I2S/LJ pin as shown in Table 12 below. aging switching noise and reducing radiated emissions. in Figure 22 below. The absolute delay time is calculated by multiplying the period SYS_CLK by 4. Table 11. Input Source Selection Table 12. Serial Audio Interface Format Selection Figure 22. Hardware Mode PWM Output Delay

The digital signal flow is shown in Figure 14 below. ware mode are disabled in hardware mode. ERRUVTE pin, indicates a thermal error condition. The ERRUVTE pin indicates the presence of a VP undervoltage or thermal error condition. Figure 23. Hardware Mode Digital Signal Flow

thereby allowing the device to again achieve its full output power capability. below demonstrates the foldback process. enabled by the EN_TFB pin as shown in Table 13 below. Table 13. Thermal Foldback Enable Selection When the junction temperature crosses the thermal warning threshold, the foldback attack delay timer is started. thermal warning threshold, the output volume level is lowered by 0.5 dB and the foldback attack timer is restarted. level is lowered accordingly. restarted once again, but the output volume level is not altered. The foldback algorithm then proceeds to step 3. as a result of the foldback event. Figure 24. Foldback Process

PWM power output pins become high-impedance. preset thresholds are crossed. jitter PWM output and higher dynamic range. Table 14. PWM Output Switching Rates and Quantization Levels

sented when LRCK is low. Either 16 bits per sample or 24 bits per sample are supported. Figure 31. Right-Justified Serial Audio Formats

Receive byte, contents of selected register. byte is separated by an acknowledge bit.

1. PCB LAYOUT CONSIDERATIONS

arrangements if its potential performance is to be realized. pin as shown in Table 18 below. in the typical connection diagrams. table on page 18), the VD, VD_REG, and VA_REG pins must all be connected to the VD supply source. ly drive the internal digital and analog sections. layers. The CRD4525 reference design demonstrates the optimum thermal pad and via configuration.

5 V Nominal

Table 18. Input Source Selection

1. REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Adr Name 01h Clock Config EnSysClk DivSysClk ClkFreq1 ClkFreq0 HP/MutePol HP/Mute PhaseShift FreqShift page 64 02h Input Config ADC/SP EnAnHPF Reserved SPRate1 SPRate0 DIF2 DIF1 DIF0 page 66 x x 03h Aux Config EnAuxPort DlyPortCfg1 DlyPortCfg0 AuxI²S/LJ RChDSel1 RChDSel0 LChDSel1 LChDSel0 page 67 04h Output Cfg OutputCfg1 OutputCfg0 PWMDSel1 PWMDSel0 OutputDly3 OutputDly2 OutputDly1 OutputDly0 page 68 05h Foldback Cfg Reserved EnTherm LockAdj AttackDly1 AttackDly0 EnFloor RmpSpd1 RmpSpd0 page 69 06h Mixer Config PreScale2 PreScale1 PreScale0 Reserved RChMix1 RChMix0 LChMix1 LChMix0 page 70 07h Tone Config DeEmph Loudness EnDigHPF TrebFc1 TrebFc0 BassFc1 BassFc0 EnToneCtrl page 71 08h Tone Control Treble3 Treble2 Treble1 Treble0 Bass3 Bass2 Bass1 Bass0 page 72 09h EQ Config Freeze Reserved BassMgr2 BassMgr1 BassMgr0 EnLFEPEq EnChBPEq EnChAPEq page 73 0Ah Channel 1&2 BiQuad 1 A1 Coeff MSB MSB-7 0Bh MSB-8 LSB+8 0Ch LSB+7 LSB 0Dh Channel 1&2 BiQuad 1 A2 Coeff MSB MSB-7 0Eh MSB-8 LSB+8 0Fh LSB+7 LSB 10h Channel 1&2 BiQuad 1 B0 Coeff MSB MSB-7 11h MSB-8 LSB+8 12h LSB+7 LSB 13h Channel 1&2 BiQuad 1 B1 Coeff MSB MSB-7 14h MSB-8 LSB+8 15h LSB+7 LSB 16h Channel 1&2 BiQuad 1 B2 Coeff MSB MSB-7 17h MSB-8 LSB+8 18h LSB+7 LSB 19h Channel 1&2 BiQuad 2 A1 Coeff MSB MSB-7 1Ah MSB-8 LSB+8 1Bh LSB+7 LSB 1Ch Channel 1&2 BiQuad 2 A2 Coeff MSB MSB-7 1Dh MSB-8 LSB+8 1Eh LSB+7 LSB 1Fh Channel 1&2 BiQuad 2 B0 Coeff MSB MSB-7 20h MSB-8 LSB+8 21h LSB+7 LSB 22h Channel 1&2 BiQuad 2 B1 Coeff MSB MSB-7 23h MSB-8 LSB+8 24h LSB+7 LSB

25h Channel 1&2 BiQuad 2 B2 Coeff MSB MSB-7 26h MSB-8 LSB+8 27h LSB+7 LSB 28h Channel 1&2 BiQuad 3 A1 Coeff MSB MSB-7 29h MSB-8 LSB+8 2Ah LSB+7 LSB 2Bh Channel 1&2 BiQuad 3 A2 Coeff MSB MSB-7 2Ch MSB-8 LSB+8 2Dh LSB+7 LSB 2Eh Channel 1&2 BiQuad 3 B0 Coeff MSB MSB-7 2Fh MSB-8 LSB+8 30h LSB+7 LSB 31h Channel 1&2 BiQuad 3 B1 Coeff MSB MSB-7 32h MSB-8 LSB+8 33h LSB+7 LSB 34h Channel 1&2 BiQuad 3 B2 Coeff MSB MSB-7 35h MSB-8 LSB+8 36h LSB+7 LSB 37h Channel 3 BiQuad 1 A1 Coeff MSB MSB-7 38h MSB-8 LSB+8 39h LSB+7 LSB 3Ah Channel 3 BiQuad 1 A2 Coeff MSB MSB-7 3Bh MSB-8 LSB+8 3Ch LSB+7 LSB 3Dh Channel 3 BiQuad 1 B0 Coeff MSB MSB-7 3Eh MSB-8 LSB+8 3Fh LSB+7 LSB 40h Channel 3 BiQuad 1 B1 Coeff MSB MSB-7 41h MSB-8 LSB+8 42h LSB+7 LSB 43h Channel 3 BiQuad 1 B2 Coeff MSB MSB-7 44h MSB-8 LSB+8 45h LSB+7 LSB 46h Channel 3 BiQuad 2 A1 Coeff MSB MSB-7 47h MSB-8 LSB+8 48h LSB+7 LSB 49h Channel 3 BiQuad 2 A2 Coeff MSB MSB-7 4Ah MSB-8 LSB+8 4Bh LSB+7 LSB 4Ch Channel 3 BiQuad 2 B0 Coeff MSB MSB-7 4Dh MSB-8 LSB+8 4Eh LSB+7 LSB 4Fh Channel 3 BiQuad 2 B1 Coeff MSB MSB-7 50h MSB-8 LSB+8 51h LSB+7 LSB 52h Channel 3 BiQuad 2 B2 Coeff MSB MSB-7 53h MSB-8 LSB+8 54h LSB+7 LSB Adr Name

2WayFreq2 2WayFreq1 2WayFreq0 page 75 56h Sensitivity LowPass3 LowPass2 LowPass1 LowPass0 HighPass3 HighPass2 HighPass1 HighPass0 page 76 57h Master Vol MVol7 MVol6 MVol5 MVol4 MVol3 MVol2 MVol1 MVol0 page 77 58h Ch 1 Vol Ch1Vol7 Ch1Vol6 Ch1Vol5 Ch1Vol4 Ch1Vol3 Ch1Vol2 Ch1Vol1 Ch1Vol0 page 78 59h Ch 2 Vol Ch2Vol7 Ch2Vol6 Ch2Vol5 Ch2Vol4 Ch2Vol3 Ch2Vol2 Ch2Vol1 Ch2Vol0 page 78 5Ah Ch 3 Vol Ch3Vol7 Ch3Vol6 Ch3Vol5 Ch3Vol4 Ch3Vol3 Ch3Vol2 Ch3Vol1 Ch3Vol0 page 78 5Bh Mute Control InvADC InvCh3 InvCh2 InvCh1 MuteADC MuteCh3 MuteCh2 MuteCh1 page 78 5Ch Limiter Cfg 1 Max2 Max1 Max0 Min2 Min1 Min0 LimitAll EnLimiter page 79 5Dh Limiter Cfg 2 Reserved Reserved RRate5 RRate4 RRate3 RRate2 RRate1 RRate0 page 80 5Eh Limiter Cfg 3 Reserved Reserved ARate5 ARate4 ARate3 ARate2 ARate1 ARate0 page 80 5Fh Power Ctrl Reserved Reserved SelectVD PDnADC PDnOut3/4 PDnOut2 PDnOut1 PDnAll page 81 60h Interrupt SRCLock ADCOvfl ChOvfl AmpErr SRCLockM ADCOvflM ChOvflM AmpErrM page 82 x x x x 61h Int Status SRCLockSt ADCOvflSt Ch3OvflSt Ch2OvflSt Ch1OvflSt RampDone Reserved Reserved page 84 x x x x x x 62h Amp Error OverCurr4 OverCurr3 OverCurr2 OverCurr1 ExtAmpSt UnderV ThermErr ThermWarn page 85 x x x x x x x x 63h Device ID DeviceID4 DeviceID3 DeviceID2 DeviceID1 DeviceID0 RevID2 RevID1 RevID0 page 87 x x x Adr Name

1. REGISTER DESCRIPTIONS All registers are read/write unless otherwise stated. All “Reserved” bits must maintain their default state. 9.1 Clock Configuration (Address 01h) 9.1.1 SYS_CLK Output Enable (EnSysClk) Default = 1 Function: This bit controls the output driver for the SYS_CLK signal. When cleared, the output driver is disabled and the SYS_CLK pin is high-impedance. When set, the output driver is enabled. If the SYS_CLK output is unused, this bit should be set to ‘0’b to disable the driver. 9.1.2 SYS_CLK Output Divider (DivSysClk) Default = 0 Function: This bit determines the divider for the XTAL clock signal for generating the SYS_CLK signal. This divider is only available if the clock source is an external crystal attached to XTI/XTO and the SYS_CLK output is enabled. 9.1.3 Clock Frequency (ClkFreq[1:0]) Default = 01 Function: These bits must be set to identify the nominal clock frequency of the crystal attached to the XTI/XTO pins or that of the input SYS_CLK signal. See the XTI Switching Specifications table on page 23 and the SYS_CLK Switching Specifications table on page 23 for complete input frequency range specifications. EnSysClk DivSysClk ClkFreq1 ClkFreq0 HP/MutePol HP/Mute PhaseShift FreqShift EnSysClk Setting Output Driver State DivSysClk Setting SYS_CLK Output Frequency ClkFreq[1:0] Setting Specified Nominal Input Clock Frequency

9.1.4 HP_Detect/Mute Pin Active Logic Level (HP/MutePol) Default = 0 Function: This bit determines the active logic level for the HP_DETECT/MUTE input signal. 9.1.5 HP_Detect/Mute Pin Mode (HP/Mute) Default = 0 Function: Configures the function of HP_DETECT/MUTE input pin. See “Headphone Detection & Hardware Mute Input” on page 47 for more information. 9.1.6 Modulator Phase Shifting (PhaseShift) Default = 0 Function: When enabled, forces the output of the PWM modulator to output differential signals which are the inverse of each other and have been phase shifted by 180 degrees. This causes, for instance, the differential sig- nal pair to be exactly in phase with one another during a mute condition, thereby reducing the amount of switching current through the load. 9.1.7 AM Frequency Shifting (FreqShift) Default = 0 Function: Controls the state of the PWM AM frequency shift feature. See “PWM AM Frequency Shift” on page 47 for more information. HP/MutePol Setting Headphone Detect/Mute Input Polarity HP/Mute Setting HP_DETECT/MUTE Pin Function PhaseShift Setting Modulator Phase Shift State FreqShift Setting AM Frequency Shift State

9.2 Input Configuration (Address 02h) 9.2.1 Input Source Selection (ADC/SP) Default = 0 Function: This bit selects the audio input source. 9.2.2 ADC High-Pass Filter Enable (EnAnHPF) Default = 1 Function: Controls the operation of the ADC high-pass filter. 9.2.3 Serial Port Sample Rate (SPRate[1:0]) - Read Only Default = XX Function: Identifies the sample rate of the incoming LRCK signal on the serial audio input port. 9.2.4 Input Serial Port Digital Interface Format (DIF [2:0]) Default = 000 Function: Selects the serial audio interface format used for the data in on SDIN. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section “Serial Audio Interfaces” on page 57. ADC/SP EnAnHPF Reserved SPRate1 SPRate0 DIF2 DIF1 DIF0 ADC/SP Setting Audio Input Source EnAnHPF Setting ADC High-Pass Filter State SPRate[1:0] Setting Identified Input Sample Rate DIF[2:0] Setting Input Serial Port Serial Audio Interface Format

9.3 AUX Port Configuration (Address 03h) 9.3.1 Enable Aux Serial Port (EnAuxPort) Default = 0 Function: Controls the operation of the auxiliary serial port. 9.3.2 Delay & Warning Port Configuration (DlyPortCfg[1:0]) Default = 00 Function: Controls the operation of the delay and warning port. See “Serial Audio Delay & Warning Input Port” on page 42 for more information. 9.3.3 Aux/Delay Serial Port Digital Interface Format (AuxI²S/LJ) Default = 0 Function: Selects the serial audio interface format for the data on AUX_SDOUT, DLY_SDIN, DLY_SDOUT. The re- quired relationship between the Left/Right clock, serial clock and serial data is defined by the Digital In- terface Format and the options are detailed in the “Serial Audio Interfaces” on page 57. 9.3.4 Aux Serial Port Right Channel Data Select (RChDSel[1:0]) Default = 01 Function: Selects the data to be sent over the right channel of the auxiliary port serial data output signal. EnAuxPort DlyPortCfg1 DlyPortCfg0 AuxI²S/LJ RChDSel1 RChDSel0 LChDSel1 LChDSel0 EnAuxPort Setting Auxiliary Port State DlyPortCfg[1:0] Setting Delay Port Configuration AuxI²S/LJ Setting Auxiliary/Delay Port Serial Audio Interface Format RChDSel[1:0] Setting Aux Serial Port Right Channel Output Data Source

9.3.5 Aux Serial Port Left Channel Data Select (LChDSel[1:0]) Default = 00 Function: Selects the data to be sent over the left channel of the auxiliary port serial data output signal. 9.4 Output Configuration Register (Address 04h) 9.4.1 Output Configuration (OutputCfg[1:0]) Default = 00 Function: Identifies the power output configuration. This parameter can only be changed when all modulators and associated logic are in the power-down state (the PDnAll bit is set). Attempts to write this register while the PDnAll is cleared will be ignored. See “PWM Power Output Configurations” on page 43 for more in- formation. 9.4.2 PWM Signals Output Data Select (PWMDSel[1:0]) Default = 00 Function: Selects the PWM data output on the PWM_SIG1 and PWM_SIG2 output signals.See “PWM_SIG Logic- Level Output Configurations” on page 44 for more information. 9.4.3 Channel Delay Settings (OutputDly[3:0]) Default = 0000 Function: The channel delay bits allow delay adjustment of each of the power output audio channels. The value of this register determines the amount of delay inserted in the output path. The delay time is calculated by multiplying the register value by the period of the SYS_CLK or crystal input clock source. These bits can LChDSel[1:0] Setting Aux Serial Port Left Channel Output Data Source OutputCfg1 OutputCfg0 PWMDSel1 PWMDSel0 OutputDly3 OutputDly2 OutputDly1 OutputDly0 OutputCfg[1:0] Setting Power Output Configuration PWMDSel Setting PWM Signal Output Mapping PWM_SIG2 output disabled. Channel 2 output on PWM_SIG2. Channel 3 output on PWM_SIG2. Channel 3 output on PWM_SIG2.

only be changed while all modulators and associated logic are in the power-down state (the PDnAll bit is set). Attempts to write these bits while the PDnAll bit is cleared will be ignored. See “PWM Channel Delay” on page 50 for more information. 9.5 Foldback and Ramp Configuration (Address 05h) 9.5.1 Enable Thermal Foldback (EnTherm) Default = 0 Function: Enables the thermal foldback feature. See “Thermal Foldback” on page 39 for more information. 9.5.2 Lock Foldback Adjust (LockAdj) Default = 0 Function: Controls the operation of the foldback lock adjustment feature. See “Thermal Foldback” on page 39 for more information. 9.5.3 Foldback Attack Delay (AttackDly[1:0]) Default = 01 Function: Controls the foldback attack delay. See “Thermal Foldback” on page 39 for more information. OutputDly[3:0] Setting Output Delay in Input Clock Source Cycles Reserved EnTherm LockAdj AttackDly1 AttackDly0 EnFloor RmpSpeed1 RmpSpeed0 EnTherm Setting Thermal Foldback State LockAdj Setting Foldback Adjustment Lock State AttackDly[1:0] Setting Foldback Attack Time

9.5.4 Enable Foldback Floor (EnFloor) Default = 0 Function: Controls the foldback attenuation floor feature. See “Thermal Foldback” on page 39 for more information. 9.5.5 Ramp Speed (RmpSpd[1:0]) Default = 11 Function: Controls the PWM output ramp speed. See “PWM PopGuard Transient Control” on page 45 for more in- formation. 9.6 Mixer / Pre-Scale Configuration (Address 06h) 9.6.1 Pre-Scale Attenuation (PreScale[2:0]) Default = 000 Function: Controls the pre-scale attenuation level. See “Pre-Scaler” on page 29 for more information. 9.6.2 Right Channel Mixer (RChMix[1:0]) Default = 00 Function: Controls the right channel mixer output. See “Channel Mixer” on page 30 for more information. EnFloor Setting Attenuation Floor RmpSpd[1:0] Setting Ramp Speed PreScale2 PreScale1 PreScale0 Reserved RChMix1 RChMix0 LChMix1 LChMix0 PreScale[2:0] Setting Pre-Scale Attenuation Setting RChMix[1:0] Setting Right Channel Mixer Output on Channel B

9.6.3 Left Channel Mixer (LChMix[1:0]) Default = 00 Function: Controls the left channel mixer output. See “Channel Mixer” on page 30 for more information. 9.7 Tone Configuration (Address 07h) 9.7.1 De-Emphasis Control (DeEmph) Default = 0 Function: Controls the operation of the internal de-emphasis filter. See “De-Emphasis” on page 31 for more infor- mation. 9.7.2 Adaptive Loudness Compensation Control (Loudness) Default = 0 Function: Controls the operation of the adaptive loudness compensation feature. See “Adaptive Loudness Compen- sation” on page 34 for more information. 9.7.3 Digital Signal Processing High-Pass Filter (EnDigHPF) Default = 0 Function: Controls the operation of the digital signal processing high-pass filter. See “Digital Signal Processing High-Pass Filter” on page 30 for more information. LChMix[1:0] Setting Left Channel Mixer Output on Channel A DeEmph Loudness EnDigHPF TrebFc1 TrebFc0 BassFc1 BassFc0 EnToneCtrl DeEmph Setting De-Emphasis State Loudness Setting Adaptive Loudness Compensation State EnDigHPF Setting Digital Signal Processing High-Pass Filter State

9.7.4 Treble Corner Frequency (TrebFc[1:0]) Default = 00 Function: Sets the corner frequency for the treble shelving filter as shown below. 9.7.5 Bass Corner Frequency (BassFc[1:0]) Default = 01 Function: Sets the corner frequency for the bass shelving filter as shown below. 9.7.6 Tone Control Enable (EnToneCtrl) Default = 0 Function: When set, enables the bass and treble shelving filters. When cleared, disables the bass and treble shelv- ing filters. 9.8 Tone Control (Address 08h) 9.8.1 Treble Gain Level (Treb[3:0]) Default = 1000 Function: Sets the gain/attenuation level of the treble shelving filter.The level can be adjusted in 1.5 dB increments from +12.0 to -10.5 dB. TrebFc[1:0] Setting Treble Corner Frequency BassFc[1:0] Setting Bass Corner Frequency EnToneCtrl Setting Tone Control Filter State Treble3 Treble2 Treble1 Treble0 Bass3 Bass2 Bass1 Bass0 Treb[3:0] Setting Treble Shelving Filter Gain/Attenuation

9.8.2 Bass Gain Level (Bass[3:0]) Default = 1000 Function: Sets the gain/attenuation level of the bass shelving filter. The level can be adjusted in 1.5 dB increments from +12.0 to -10.5 dB. 9.9

2.1 Bass Manager/Parametric EQ Control (Address 09h)

9.9.1 Freeze Controls (Freeze) Default = 0 Function: This function will freeze the previous output of, and allow modifications to be made to the master volume control (address 57h), channel X volume control (address 58h - 5Ah), and bi-quad coefficients for channel 1, channel 2 and channel 3 (address 0Ah - 54h) registers without the changes taking effect until the Freeze bit is disabled. To make multiple changes in these control port registers take effect simulta- neously, enable the Freeze bit, make all register changes, then disable the Freeze bit. 9.9.2 Bass Cross-Over Frequency (BassMgr[2:0]) Default = 000 Function: Controls the operation and cross-over frequency of the bass manager. See “Bass Management” on page 35 for more information. Bass[3:0] Setting Bass Shelving Filter Gain/Attenuation Freeze Reserved BassMgr2 BassMgr1 BassMgr0 EnLFEPEq EnChBPEq EnChAPEq Freeze Setting Register Freeze State BassMgr[2:0] Setting Bass Manager Crossover Setting

9.9.3 Enable LFE Parametric EQ (EnLFEPEq) Default = 0 Function: Enables the parametric EQ 4 and 5 bi-quad filters for the LFE channel. 9.9.4 Enable Channel B Parametric EQ (EnChBPEq) Default = 0 Function: Enables the parametric EQ 1, 2, and 3 bi-quad filters for channel B. 9.9.5 Enable Channel A Parametric EQ (EnChAPEq) Default = 0 Function: Enables the parametric EQ 1, 2, and 3 bi-quad filters for channel A. EnLFEPEq Setting LFE Parametric EQ State EnChBPEq Setting Channel B Parametric EQ State EnChAPEq Setting Channel A Parametric EQ State

9.10 Volume and 2-Way Cross-Over Configuration (Address 55h) 9.10.1 Soft Ramp and Zero Cross Control (SZCMode[1:0]) Default = 10 Function: Sets the soft ramp and zero crossing detection modes by which volume and muting changes will be im- plemented. 9.10.2 Enable 50% Duty Cycle for Mute Condition (Mute50/50) Default = 0 Function: Enables the outputs of the amplifiers to switch at an exact 50%-duty-cycle signal (not modulated) for all mute conditions. This bit does not cause a mute condition to occur. The Mute50/50 bit only defines oper- ation during a normal mute condition. 9.10.3 Auto-Mute (AutoMute) Default = 1 Function: When enabled, the outputs of the CS4525 will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. See “Volume and Muting Control” on page 36 for more informa- tion. SZCMode1 SZCMode0 Mute50/50 AutoMute En2Way 2WayFreq2 2WayFreq1 2WayFreq0 SZCMode[1:0] Setting Soft Ramp & Zero Crossing Mode When immediate change is selected, all level changes will take effect immediately in one step. Zero cross dictates that signal level changes, both muting and attenuation, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period (approximately 18.7 ms for a PWM switch rate of 384/768 kHz and 17.0 ms for a PWM switch rate of 421.875/843.75 kHz) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in ½ dB steps, from the current level to the new level at a rate of ½ dB per 4 sample peri- ods for 32, 44.1, and 48 kHz, and ½ dB per 8 sample periods for 96 kHz. Soft ramp on zero cross dictates that signal level changes, both muting and attenuation, will occur in ½ dB steps and be implemented on a signal zero crossing. The ½ dB level change will occur after a timeout period (approximately 18.7 ms for a PWM switch rate of 384/768 kHz and 17.0 ms for a PWM switch rate of 421.875/843.75 kHz) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Mute50/50 Setting 50% Duty Cycle Mute State AutoMute Setting AutoMute State

9.10.4 Enable 2-Way Crossover (En2Way) Default = 0 Function: Enables the 2-way crossover filters for channel 1 and channel 2. 9.10.5 2-Way Cross-Over Frequency (2WayFreq[2:0]) Default = 000 Function: Selects the cross-over frequency for the 2-Way Linkwitz-Riley filters. 9.11 Channel 1-2: 2-Way Sensitivity Control (Address 56h) 9.11.1 Channel 1 and Channel 2 Low-Pass Sensitivity Adjust (LowPass[3:0]) Default = 0000 Function: Controls the 2-way cross-over low-pass sensitivity adjustment. See “2-Way Crossover & Sensitivity Con- trol” on page 41 for more information. En2Way Setting 2-Way Crossover State 2WayFreq Setting 2-Way Crossover Frequency LowPass3 LowPass2 LowPass1 LowPass0 HighPass3 HighPass2 HighPass1 HighPass0 LowPass[3:0] Setting Sensitivity Compensation Level

9.11.2 Channel 1 and Channel 2 High-Pass Sensitivity Adjust (HighPass[3:0]) Default = 0000 Function: Controls the 2-way cross-over high-pass sensitivity adjustment. See “2-Way Crossover & Sensitivity Con- trol” on page 41 for more information. 9.12 Master Volume Control (Address 57h) 9.12.1 Master Volume Control (MVol[7:0]) Default = 30h Function: Sets the gain/attenuation level of the master volume control. See “Volume and Muting Control” on page 36 for more information. HighPass[3:0] Setting Sensitivity Compensation Level MVol7 MVol6 MVol5 MVol4 MVol3 MVol2 MVol1 MVol0 MVol[7:0] Setting Master Volume Setting

9.13 Channel 1, 2, & 3 Volume Control (Address 58h, 59h, & 5Ah) 9.13.1 Channel X Volume Control (ChXVol[7:0]) Default = 30h Function: Sets the gain/attenuation levels of the channel 1, 2, and 3 individual volume controls. See “Volume and Muting Control” on page 36 for more information. 9.14 Mute/Invert Control (Address 5Bh) 9.14.1 ADC Invert Signal Polarity (InvADC) Default = 0 Function: When set, the signal polarity of the ADC will be inverted. 9.14.2 Invert Signal Polarity (InvChX) Default = 0 Function: When set, the signal polarity of the respective channels will be inverted. 9.14.3 ADC Channel Mute (MuteADC) Default = 0 Function: The output of the ADC will mute when enabled. ChXVol7 ChXVol6 ChXVol5 ChXVol4 ChXVol3 ChXVol2 ChXVol1 ChXVol0 ChXVol[7:0] Setting Channel X Volume Setting InvADC InvCh3 InvCh2 InvCh1 MuteADC MuteCh3 MuteCh2 MuteCh1 InvADC Setting ADC Signal Inversion State InvChX Setting Channel X Signal Inversion State MuteADC Setting ADC Mute State

9.14.4 Independent Channel Mute (MuteChX) Default = 0 Function: The PWM outputs of the CS4525 will mute when enabled. The muting function is affected, similar to at- tenuation changes, by the soft and zero cross bits (SZCMode[1:0]). See “Volume and Muting Control” on page 36 for more information. 9.15 Limiter Configuration 1 (Address 5Ch) 9.15.1 Maximum Threshold (Max[2:0]) Default = 000 Function: Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the limiter attack rate. 9.15.2 Minimum Threshold (Min[2:0]) Default = 000 Function: Sets a minimum level below full scale at which the limiter will begin to release its applied attenuation. 9.15.3 Peak Signal Limit All Channels (LimitAll) Default = 1 Function: When cleared, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the specific channel indicating clipping. The other channels will not be affected. When set, the peak signal MuteChX Setting Channel X Mute State Max2 Max1 Max0 Min2 Min1 Min0 LimitAll EnLimiter Max[2:0] Setting Maximum Threshold Setting Min[2:0] Setting Minimum Threshold Setting

limiter will limit the maximum signal amplitude to prevent clipping on all channels in response to any single channel indicating clipping. See “Peak Signal Limiter” on page 37 for more information. 9.15.4 Peak Detect and Limiter Enable (EnLimiter) Default = 0 Function: Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak signal limit- ing is performed by digital attenuation. 9.16 Limiter Configuration 2 (Address 5Dh) 9.16.1 Limiter Release Rate (RRate[5:0]) Default = 000000 Function: Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in the limiter threshold register. The limiter release rate is a function of the sampling frequency, Fs, and the soft and zero cross setting. 9.17 Limiter Configuration 3 (Address 5Eh) 9.17.1 Limiter Attack Rate (ARate[5:0]) Default = 000000 Function: Sets the rate at which the limiter attenuates the analog output from levels above the maximum setting in the limiter threshold register. The limiter attack rate is a function of the sampling frequency, Fs, and the soft and zero cross setting. LimitAll Setting Limit All Channels Configuration EnLimiter Setting Peak Signal Limiter State Reserved Reserved RRate5 RRate4 RRate3 RRate2 RRate1 RRate0 RRate[5:0] Setting Limiter Release Rate Reserved Reserved ARate5 ARate4 ARate3 ARate2 ARate1 ARate0 ARate[5:0] Setting Limiter Attack Rate

9.18 Power Control (Address 5Fh) 9.18.1 Select VD Level (SelectVD) Default = 1 Function: This bit selects between a VD of 2.5 V or 3.3 V when the LVD pin is connected to DGND. This bit is ignored when the LVD pin is connected to VD. 9.18.2 Power Down ADC (PDnADC) Default = 1 Function: The ADC will enter a power down state when this bit is enabled. 9.18.3 Power Down PWM Power Output X (PDnOutX) Default = 1 Function: When set, the specific PWM power output will enter a power-down state. Only the output power stage is powered down. The PWM modulator is not affected, nor is the setup or delay register values. When set to normal operation, the specific output will power up according to the state of the RmpSpd[1:0] bits and the channel output configuration selected. When transitioning from normal operation to power down, the specific output will power down according to the state of the RmpSpd[1:0] bits and the channel output con- figuration selected. 9.18.4 Power Down (PDnAll) Default = 1 Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation can occur. Reserved Reserved SelectVD PDnADC PDnOut3/4 PDnOut2 PDnOut1 PDnAll SelectVD Setting Selected VD Level PDnADC Setting ADC Power-Down State PDnChX Setting Power Output X Power-Down State PDnAll Setting Device Power-Down State

9.19 Interrupt Register (Address 60h) Bits [7:4] in this register are read only. A ‘1’b in these bit positions indicates that the associated condition has oc- curred at least once since the register was last read. A ‘0’b indicates that the associated condition has not occurred since the last reading of the register. Reading the register resets bits to [7:4] ‘0’b. These bits are considered “edge- trigger” events. The operation of these 4 bits is not affected by the interrupt mask bits and the condition of each bit can be polled instead of generating an interrupt as required. 9.19.1 SRC Lock State Transition Interrupt Bit (SRCLock) Default = 0 Function: This bit is read only. When set, indicates that the SRC has transitioned from an unlock to lock state or from a lock state to an unlock state since the last read of this register. Conditions which cause the SRC to transition states, such as loss of LRCK, SCLK, an LRCK ratio change, or the SRC achieving lock, will cause this bit to be set. This interrupt bit is an edge-triggered event and will be cleared following a read of this register. If this bit is set, indicating a SRC state change condition, and the SRCLockM bit is set, the INT pin will go active. To determine the current lock state of the SRC, read the SRCLockSt bit in the interrupt status reg- ister. 9.19.2 ADC Overflow Interrupt Bit (ADCOvfl) Default = 0 Function: This bit is read only. When set, indicates that an over-range condition occurred anywhere in the CS4525 ADC signal path and has been clipped to positive or negative full scale as appropriate since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this register. If this bit is set, indicating an ADC over-range condition, and the ADCOvflM bit is set, the INT pin will go active. To determine the current overflow state of the ADC, read the ADCOvflSt bit in the interrupt status register. 9.19.3 Channel Overflow Interrupt Bit (ChOvfl) Default = 0 Function: This bit is read only. When set, indicates that the magnitude of an output sample on channel 1, 2, or 3 has exceeded full scale and has been clipped to positive or negative full scale as appropriate since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this register. SRCLock ADCOvfl ChOvfl AmpErr SRCStateM ADCOvflM ChOvflM AmpErrM SRCLock Setting SRC Lock State Change Status ADCOvfl Setting ADC Overflow Event Status

If this bit is set, indicating a channel over-range condition, and the ChOvflM bit is set, the INT pin will go active. To determine the current overflow state of each channel, read the ChXOvflSt bits in the interrupt status register. 9.19.4 Amplifier Error Interrupt Bit (AmpErr) Default = 0 Function: This bit is read only. When set, indicates that an error was detected in the power amplifier section since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this register. This bit is the logical OR of all the bits in the amplifier error status register. Read the amplifier error status register to determine which condition occurred. If this bit is set, indicating an amplifier stage error condition, and the AmpErrM bit is set to a ‘1’b, the INT pin will go active. To determine the actual current state of the amplifier error condition, read the amplifier error status register. 9.19.5 Mask Bit for SRC State (SRCLockM) Default = 0 Function: This bit serves as a mask for the SRC status interrupt source. If this bit is set, the SRCLock interrupt is unmasked, meaning that if the SRCLock bit is set, the INT pin will go active. If the SRCLockM bit is cleared, the SRCLock condition is masked, meaning that its occurrence will not affect the INT pin. How- ever, the SRCLock and SRCLockSt bits will continue to reflect the lock status of the SRC. 9.19.6 Mask Bit for ADC Overflow (ADCOvflM) Default = 0 Function: This bit serves as a mask for the ADC overflow interrupt source. If this bit is set, the ADCOvfl interrupt is unmasked, meaning that if the ADCOvfl bit is set, the INT pin will go active. If the ADCOvflM bit is cleared, the ADCOvfl condition is masked, meaning that its occurrence will not affect the INT pin. However, the ADCOvfl and ADCOvflSt bits will continue to reflect the overflow state of the ADC. ChOvfl Setting Channel Overflow Event Status AmpErr Setting Amplifier Error Event Status SRCLockM Setting SRCLock INT Pin Mask State ADCOvflM Setting ADCOvfl INT Pin Mask State

9.19.7 Mask Bit for Channel X Overflow (ChOvflM) Default = 0 Function: This bit serves as a mask for the channel overflow interrupt source. If this bit is set, the ChOvfl interrupt is unmasked, meaning that if the ChOvfl bit is set, the INT pin will go active. If the ChOvflM bit is cleared, the ChOvfl condition is masked, meaning that its occurrence will not affect the INT pin. However, the ChO- vfl and ChXOvflSt bits will continue to reflect the overflow state of the individual channels. 9.19.8 Mask Bit for Amplifier Error (AmpErrM) Default = 0 Function: This bit serves as a mask for the amplifier error interrupt sources. If this bit is set, the AmpErr interrupt is unmasked, meaning that if the AmpErr bit is set, the INT pin will go active. If the AmpErrM bit is cleared, the AmpErr condition is masked, meaning that its occurrence will not affect the INT pin. However, the Am- pErr and the amplifier error bits in the amplifier error status register will continue to reflect the status of the amplifier error conditions. 9.20 Interrupt Status Register (Address 61h) - Read Only All bits in this register are considered “level-trigger” events, meaning as long as a condition continues, the corre- sponding bit will remain set. These status bits are not affected by the interrupt mask bit and the condition of each bit can be polled. These bits will not be cleared following a read to this register, nor can they be written to cause an interrupt condition. 9.20.1 SRC State Transition (SRCLockSt) Default = 0 Function: This bit is read only and reflects the current lock state of the SRC. When set, indicates the SRC is currently locked. When cleared, indicates the SRC is currently unlocked. ChOvflM Setting ChOvfl INT Pin Mask State AmpErrM Setting AmpErr INT Pin Mask State SRCLockSt ADCOvflSt Ch3OvflSt Ch2OvflSt Ch1OvflSt RampDone Reserved Reserved SRCLockSt Setting SRC Lock State

9.20.2 ADC Overflow (ADCOvfl) Default = 0 Function: This bit is read only and will identify the presence of an overflow condition within the ADC. When set, in- dicates that an over-range condition is currently occurring in the CS4525 ADC signal path and has been clipped to positive or negative full scale. 9.20.3 Channel X Overflow (ChXOvfl) Default = 0 Function: These bits are read only and will identify the presence of an overflow condition anywhere in the associated channel’s signal path. When set, indicates that an over-range condition is currently occurring in the chan- nel’s signal path and has been clipped to positive or negative full scale. 9.20.4 Ramp-Up Cycle Complete (RampDone) Default = 0 Function: When set, indicates that all active channels have completed the configured ramp-up interval. 9.21 Amplifier Error Status (Address 62h) - Read Only All bits in this register are considered “level-trigger” events, meaning as long as a condition continues, the corre- sponding bit will remain set. These status bits are not affected by the interrupt mask bit and the condition of each bit can be polled. These bits will not be cleared following a read to this register, nor can they be written to cause an interrupt condition. 9.21.1 Over-Current Detected On Channel X (OverCurrX) Default = 0 Function: When set, indicates an over current condition is currently present on the corresponding amplifier output. ADCOvfl Setting ADC Overflow State ChXOvfl Setting Channel X Overflow State RampDone Setting Ramp Completion State OverCurr4 OverCurr3 OverCurr2 OverCurr1 ExtAmpErr UnderV ThermErr ThermWarn OverCurrX Setting Amplifier Over-Current Status

9.21.2 External Amplifier State (ExtAmpSt) Default = 0 Function: When set, indicates a thermal warning condition is currently being reported by an external amplifier. For proper operation, the delay serial port must be configured to support an external thermal warning input signal. This status bit reflects the active state of the external thermal warning input signal. 9.21.3 Under Voltage Detected (UnderV) Default = 0 Function: When set, indicates an undervoltage condition is currently present on the VP voltage rail. 9.21.4 Thermal Error Detected (ThermErr) Default = 0 Function: When set, indicates a thermal error condition (specified by the thermal error trip point listed in the PWM Power Output Characteristics table on page 20) is currently present. 9.21.5 Thermal Warning Detected (ThermWarn) Default = 0 Function: When set, indicates a thermal warning condition (specified by the thermal warning trip point listed in the PWM Power Output Characteristics table on page 20) is currently present. ExtAmpSt Setting External Amplifier Status UnderV Setting VP Under Voltage Status ThermErr Setting Thermal Error Status ThermWarn Setting Thermal Warning Status

9.22 Chip I.D. and Revision Register (Address 63h) - Read Only 9.22.1 Device Identification (DeviceID[4:0]) Default =11000 Function: Identification code for the CS4525. 9.22.2 Device Revision (RevID[2:0]) Default = 000 Function: CS4525 revision level. DeviceID4 DeviceID3 DeviceID2 DeviceID1 DeviceID0 RevID2 RevID1 RevID0 DeviceID[4:0] Setting Device ID Notes RevID[2:0] Setting Device Revision ID

10.PARAMETER DEFINITIONS Dynamic Range (DYR) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measurement over the spec- ified band width made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Ex- pressed in decibels. Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The amplitude cor- ner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The listed minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequency to maxi- mum frequency inclusive. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. Fs Sampling Frequency. Resolution The number of bits in a serial audio data word. SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. 11.REFERENCES Cirrus Logic, “AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,” Version 6.0, February 1998. Cirrus Logic, “AN22: Overview of Digital Audio Interface Data Structures, Version 2.0”, February 1998.; A useful tutorial on digital audio specifications. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998. http://www.semiconductors.philips.com

12.PACKAGE DIMENSIONS Notes: Dimensioning and tolerance per ASME Y4.5M - 1994. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0.0354 0.90 0.0000 0.0020 0.00 0.05 b 0.0118 0.0138 0.0157 0.30 0.35 0.40 1,2 D

0.3543 BSC

9.00 BSC

0.2618 0.2677 0.2736 6.65 6.80 6.95 E 0.2618 0.2677 0.2736 6.65 6.80 6.95 e

0.0256 BSC

0.65 BSC

L 0.0177 0.0217 0.0276 0.45 0.55 0.70 JEDEC #: MO-220 Controlling Dimension is Millimeters. Table 19: Side View Bottom View Top View A Pin #1 ID D E L b e Pin #1 ID 48L QFN (9 × 9 MM BODY) PACKAGE DRAWING

13.THERMAL CHARACTERISTICS 13.1 Thermal Flag This device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane on the PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be coupled with vias to a large metal plane on the backside (and inner ground layer, if applicable) of the PCB. In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those imme- diately surrounding the CS4525. In addition to improving in electrical performance, this practice also aids in heat dissipation. The heat dissipation capability required of the metal plane for a given output power can be calculated as follows: θCA = [(TJ(MAX) - TA) / PD] - θJC where, θCA = Thermal resistance of the metal plane in °C/Watt TJ(MAX) = Maximum rated operating junction temperature in °C, equal to 150 °C TA = Ambient temperature in °C PD = RMS power dissipation of the device, equal to 0.15*PRMS (assuming 85% efficiency) θJC = Junction-to-case thermal resistance of the device in °C/Watt 14.ORDERING INFORMATION Parameter Symbol Min Typ Max Units Junction to Case Thermal Impedance θJC °C/Watt Product

Description

Order# CS4525 Digital TV Amp with Integrated ADC 48-QFN Yes Commercial -10° to +70°C Rail CS4525-CNZ Tape and Reel CS4525-CNZR CRD4525 2 x 15 W Reference Design Board CRD4525 CRD4412 1 x 30 W Reference Design Daughter Card CRD4412

15.REVISION HISTORY Release Changes Initial Release Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) be- lieve that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the infor- mation only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor.