CS44800-DQZ

CS44800_06 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

 > 100 dB Dynamic Range - System Level  < 0.03% THD+N @ 1 W - System Level  32 kHz to 192 kHz Sample Rates  Internal Oscillator Circuit Supports 24.576 MHz to 54 MHz Crystals  Integrated Sample Rate Converter (SRC) – Eliminates Clock Jitter Effects – Input Sample Rate Independent Operation  Power Supply Rejection Realtime Feedback  Spread Spectrum Modulation - Reduces EMI  PWM Popguard® for Single-Ended Mode  Eliminates AM Frequency Interference  Programmable Load Compensation Filters  Support for up to 40 kHz Audio Bandwidth  Digital Volume Control with Soft Ramp – +24 to -127 dB in 0.25 dB Steps  Per Channel Programmable Peak Detect and Limiter  SPI™ and I²C ® Host Control Interfaces  Separate 2.5 V to 5.0 V Serial Port and Host Control Port Supplies DAI Serial Port XTAL PWMOUTA1+ Power Supply Rejection PWMOUTB1+ SPI/I2C Host Control Port SCL/CCLK AD1/CDIN AD0/CS RST INT PSR_MCLK PSR_SYNC PSR_DATA PWM Backend Control/ Status GPIO4 GPIO5 GPIO0 GPIO1 GPIO2 XTO XTI PWMOUTA1- PWMOUTB1- PWMOUTA2+ PWMOUTB2+ PWMOUTA2- PWMOUTB2- PWMOUTA3+ PWMOUTB3+ PWMOUTA3- PWMOUTB3- MUTE PWMOUTA4+ PWMOUTB4+ PWMOUTA4- PWMOUTB4- DAI_MCLK DAI_SCLK DAI_LRCK DAI_SDIN1 DAI_SDIN2 DAI_SDIN3 DAI_SDIN4 Volume / Limiter Multibit Modulator PWM Conversion PWM Conversion PWM Conversion PWM Conversion Volume / Limiter Multibit Modulator Volume / Limiter Multibit Modulator Volume / Limiter Multibit Modulator PWM Clock Control Auto Fs Detect GPIO3 GPIO6 PSR_EN PSR_RESETPS_SYNC SRC SYS_CLK SDA/CDOUT MARCH '06 DS632F1 CS44800

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The CS44800 is a multi-channel digital-to-PWM Class D audio system controller including interpolation, sample rate conversion, half- and full-bridge PWM driver outputs, and power supply rejection feedback in a 64-pin LQFP pack- age.The architecture uses a direct-to-digital approach that ma intains digital signal integrity to the final output filter, minimizing analog interference effects which negatively affect system performance. The CS44800 integrates on-chip digital volume control, peak detect with limiter, de-emphasis, and 7 GPIO’s, allow- ing easy interfacing to many commonly available power stages. The PWM amplifier can achieve greater than 90% efficiency. This efficiency provides for smaller device package, less heat sink requirements, and smaller power supplies. The CS44800 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, digital speaker and automotive audio systems.

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7.18 Chnl XX Load Compensation Filter - Coarse Adjust

7.19 Chnl XX Load Compensation Filter - Fine Adjust

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1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to ground) Notes: ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.) WARNING: Operation at or beyond these limit s may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. Parameter Symbol Min Typ Max Units DC Power Supply Digital 2.5 V VD 2.37 2.5 2.63 V XTAL (Note 1) 2.5 V 3.3 V 5.0 V VDX 2.37 3.14 4.75 2.5 3.3 5.0 2.63 3.47 5.25 V V V PWM Interface 3.3 V 5.0 V VDP 3.14 4.75 3.3 5.0 3.47 5.25 V V Serial Audio Interface 2.5 V 3.3 V 5.0 V VLS 2.37 3.14 4.75 2.5 3.3 5.0 2.63 3.47 5.25 V V V Control Interface 2.5 V 3.3 V 5.0 V VLC 2.37 3.14 4.75 2.5 3.3 5.0 2.63 3.47 5.25 V V V Ambient Operating Temperature Commercial -CQZ Automotive -DQZ T A -10 -40 +70 +85 Parameters Symbol Min Max Units DC Power Supply Digital XTAL PWM Interface Serial Audio Interface Control Interface VD VDX VDP VLS VLC -0.3 -0.3 -0.3 -0.3 -0.3 3.5 6.0 6.0 6.0 6.0 V V V V V Input Current (Note 2) I in -± 1 0 m A Digital Input Voltage PWM Interface (Note 3) Serial Audio Interface Control Interface VIND-PWM VIND-S VIND-C -0.3 -0.3 -0.3 VDP+0.4 VLS+0.4 VLC+0.4 V V V Ambient Operating Temperature -CQ (power applied) -DQ T A -20 -50 +85 +95 Storage Temperature T stg -65 +150 °C

DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to ground; DAI_MCLK = 12.288 MHz, XTAL = 24.576 MHz, PWM Switch Rate = 384 kHz unless otherwise specified.) 4. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input. 5. Current consumption increases with increasing XT AL clock rates and PWM switch rates. Variance be- tween DAI clock rates is negligible. 6. I LC measured with no external loading on the SDA pin. 7. Valid with PSRR function enabled and the reco mmended external ADC (CS4461) and filtering. 8. Power down mode is defined as RST pin = LOW with all clock and data lines held static. 9. When RST pin = LOW, the internal oscillator is active to provide a valid clock for the SYS_CLK output. DIGITAL INTERFACE CHARACTERISTICS (GND = 0 V, all voltages with respect to ground) 10. Serial Port signals include: SYS_CL K, DAI_MCLK, DAI_SCLK, DAI_LRCK, DAI_SDIN1-4 Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS , AD1/CDIN, INT, RST , MUTE PWM signals include: PWMOUTA1-B4, PSR_MCLK, PSR_SYNC, PSR_DATA, PS_SYNC, GPIO[6:0] Parameter Symbol Min Typ Max Units Normal Operation (Note 4) Power Supply Current (Note 5) VD = 2.5 V VDX = 3.3 V VDP = 3.3 V VLS = 3.3 V VLC = 3.3 V (Note 6) ID IDX IDP ILS ILC 150 1.2 150 250 mA mA mA µA µA Power Dissipation VD=2.5 V, VDX = VDP = VLS = VLC = 3.3 V - 387 500 mW Power Supply Rejection Ratio (Note 7) (1 kHz) (60 Hz) PSRR - dB dB Power-Down Mode (Note 8) Power Supply Current All Supplies except VDX (Note 9) I pd -8 0- µ A Parameters (Note 10) Symbol Min Typ Max Units High-Level Input Voltage XTAL PWM Interface Serial Audio Interface Control Interface VIH 0.7xVDX 0.7xVDP 0.7xVLS 0.7xVLC V V V V Low-Level Input Voltage XTAL PWM Interface Serial Audio Interface Control Interface V IL 0.2xVDX 0.2xVDP 0.2xVLS 0.2xVLC V V V V High-Level Output Voltage at I o = -2 mA PWM Interface Serial Audio Interface Control Interface VOH VDP-1.0 VLS-1.0 VLC-1.0 V V V Low-Level Output Voltage at I o = 2 mA PWM Interface Serial Audio Interface Control Interface VOL 0.45 0.45 0.45 V V V Input Leakage Current I in -- ± 1 0 µ A Input Capacitance - - 8 pF

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1. Performance characteristics me asured using filter shown in Figure 1.

Figure 1. Performance Characteristics Evaluation Active Filter Circuit

1. Filter response is not production tested but is characterized and guaranteed by design.
2. XTAL = 49.152 MHz; PWM Switch Rate = 768 kHz; Fs = 96 kHz to 192 kHz.
3. The equation for the group delay through the sample rate converter with OSRATE = 0b is (8.5 / Fsi) + (10

Figure 2. XTI Timings

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Figure 3. SYS_CLK Timings Figure 4. PWMOUTxx Timings Figure 5. PS_SYNC Timings

1. After powering up, the CS44800, RST should be held low until after the power supplies and clocks are set-
2. See Table 1 on page 26 for suggested MCLK frequencies.
3. Max DAI sample rate is 96 kHz for One Line and TDM modes of operation.

Figure 6. Serial Audio Interface Timing Figure 7. Serial Audio Interface Timing - TDM Mode

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1. Data must be held for sufficient time to bridge the transition time, t f, of SCL.

Figure 8. Control Port Timing - I²C Format

1. Data must be held for su fficient time to bridge the transition time of CCLK.

Figure 9. Control Port Timing - SPI Format

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Figure 10. CS44800 Pinout Diagram

PS_SYNC 3 Power Supply Synchronization Clock (Output) - The PWM synchronized clock to the switch mode power supply. XTI 5 Crystal Oscillator Input (Input) - Crystal Oscillator input or accepts an external clock input signal that is used to drive the internal PWM core logic. XTO 6 Crystal Oscillator Output (Output) - Crystal Oscillator output. SYS_CLK 8 External System Clock (Output) - Clock output. This pin provides a divided down clock derived from the XTI input. DAI_MCLK 9 Digital Audio Input Master Clock (Input) - Master audio clock. DAI_SCLK 10 Digital Audio Input Serial Clock (Input) - Serial clock for the Digital Audio Input Inter- face. The clock frequency is a multiple of the Left/Right Clock running at Fs. DAI_LRCK 11 Digital Audio Input Left/Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The rate is determined by the sampling fre- quency Fs. DAI_SDIN1 DAI_SDIN2 DAI_SDIN3 DAI_SDIN4 Digital Audio Input Serial Data (Input) - Input for two’s complement serial audio data. MUTE 20 Mute (Input) - The device will perform a hard mute on all channels. All internal registers are not reset to their default settings. SCL/CCLK 21 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up resistor to the logic interface voltage in I²C mode as shown in the Typical Connection Diagram. SDA/CDOUT 22 Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an external pull-up resistor to the logic interface voltage, as shown in the Typical Connection Diagram.; CDOUT is the output data line for the control port interface in SPI mode. AD1/CDIN 23 Address Bit 1 (I²C)/Serial Control Data (SPI) (Input) - AD1 is a chip address pin in I²C mode.;CDIN is the input data line for the control port interface in SPI mode. AD0/CS

24 Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in

I²C mode; CS is the chip select signal in SPI mode. INT 25 Interrupt Request (Output) - CMOS or open-drain interrupt request output. This pin is driven to the configured active state to indicate that the PWM Controller has status data that should be read by the host. RST 26 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. GPIO6 29 General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST condition. It can be configured as a general purpose input or output which can be individually controlled by the Host Controller. GPIO5 30 General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST condition. It can be configured as a general purpose input or output which can be individually controlled by the Host Controller. GPIO4 31 General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST condition. It can be configured as a general purpose input or output which can be individually controlled by the Host Controller. GPIO3 32 General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST condition. It can be configured as a general purpose input or output which can be individually controlled by the Host Controller.

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General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST condition. It can be configured as a general purpose input or output which can be individually controlled by the Host Controller. GPIO1 34 General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST condition. It can be configured as a general purpose input or output which can be individually controlled by the Host Controller. GPIO0 35 General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- ing a RST condition. It can be configured as a general purpose input or output which can be individually controlled by the Host Controller. PSR_MCLK 49 Power Supply Rejection Master Clock (Output) - Master audio clock for external PSR ADC (CS4461). PSR_DATAL 50 Power Supply Rejection Input Serial Data (Input) - Input for serial audio data from external PSR ADC (CS4461). PSR_SYNC 51 Power Supply Rejection Sync Clock (Input) - Synchronization signal for external PSR ADC (CS4461). PSR_RESET 52 Power Supply Rejection Reset (Output) - The reset pin for the external Power Supply Rejection circuitry. PSR_EN 2 Power Supply Rejection Enable (Output) - The enable pin for the external Power Supply Rejection circuitry. PWMOUTA1+ PWMOUTA1- PWMOUTB1+ PWMOUTB1- PWMOUTA2+ PWMOUTA2- PWMOUTB2+ PWMOUTB2- PWMOUTA3+ PWMOUTA3- PWMOUTB3+ PWMOUTB3- PWMOUTA4+ PWMOUTA4- PWMOUTB4+ PWMOUTB4- PWM Output (Output) - PWM control signals for the Class D amplifier backend. VDX 7 Crystal Power (Input) - Positive power supply for the Crystal section. VD 19, 27 Digital Power (Input) - Positive power supply for the digital section. VLC 17 Host Interface Power (Input) - Determines the required signal level for the digital input/output signals for the host interface. VLS 16 Digital Audio Interface Power (Input) - Determines the required signal level for the digital input signals for the digital audio interface. VDP 39, 45, 56, 62 PWM Interface Power (Input) - Determines the required signal level for the digital input/output signals for the PWM and GPIO interface.

1, 4, 18, 28, 36, 42, 48, 53, Digital Ground (Input) - Ground reference for digital circuits.

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2.1 I/O Pin Characteristics

RST VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible. SCL/CCLK VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis. SDA/CDOUT VLC Input / Output 2.5-5.0 V, CMOS/Open Drain 2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis. AD0/CS VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-up. AD1/CDIN VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-up. INT VLC Output 2.5-5.0 V, CMOS/Open Drain - MUTE VLC Input - 2.5 V and 3.3/5.0 V TTL Compatible. DAI_SDINx VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible. DAI_SCLK VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible. DAI_LRCK VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible. DAI_MCLK VLS Input - 2.5 V and 3.3/5.0 V TTL Compatible. SYS_CLK VLS Output 2. 5-5.0 V, CMOS - XTI VDX Input - 2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-down. XTO VDX Output - - GPIOx VDP Input / Output 3.3/5.0 V, CMOS/Open Drain 3.3/5.0 V TTL Compatible. PWMOUTAx+/- VDP Outp ut 3.3/5.0 V, CMOS - PWMOUTBx+/- VDP Outp ut 3.3/5.0 V, CMOS - PSR_MCLK VDP Output 3.3/5.0 V, CMOS - PSR_SYNC VDP Input - 3.3/5.0 V TTL Compatible, Internal pull-up. PSR_DATA VDP Input - 3.3/5.0 V TTL Compatible, Internal pull-up. PSR_EN VDP Output 3.3/5.0 V, CMOS - PSR_RESET VDP Output 3.3/5.0 V, CMOS - PS_SYNC VDP Output 3.3/5.0 V, CMOS -

1. TYPICAL CONNECTION DIAG RAMS

Figure 11. Typical Full-Bridge Connection Diagram

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Figure 12. Typical Half-Bridge Connection Diagram

1. APPLICATIONS

4.1 Overview

The CS44800 is a multi-channel digital-to-PWM Clas s D audio system controlle r including interpolation, sample rate conversion, half- and full-bridge PWM driver outputs, and power supply rejection feedback in a 64-pin LQFP package. The architecture uses a direct-to-digital approach that maintains digital signal integ- rity to the final output filter, minimizing analog in terference effects which negat ively affect system perfor- mance. The CS44800 integrates on-chip sample rate conversi on, digital volume control, peak detect with volume limiter, de-emphasis, programmable interrupt conditions, and the ability to change the PWM switch rate to eliminate AM frequency interference. The CS44800 also has a programmable load compensation filter, which allows the speaker load to vary while the output filter remains fixed, maintaining a flat frequency re- sponse. For single-ended half-bridge applications PWM Popguard ® reduces the transient pops and clicks and realtime power supply feedback reduces noise coupling from the power supply. The PWM amplifier can achieve greater than 90% efficiency. This efficiency provides for a smaller device package, less heat sink requirements, and smaller power supplies. The CS44800 is ideal for audio systems requiring wide dynamic range, negligible distortion, and low noise such as A/V receivers, DVD receivers, digital speaker, and automotive audio systems.

4.2 Feature Set Summary

• 2.5 V digital core voltage, VD.
• VLC voltage pin for host interface logic levels between 2.5 V and 5.0 V.
• VLS voltage pin for digital audio interface logic levels between 2.5 V and 5.0 V.
• VDP voltage pin for PWM backend interfac e logic levels between 3.3 V and 5.0 V.
• VDX voltage pin for clock input signals between 2.5 V and 5.0 V. Clocking
• Minimum of 128Fs DAI_MCLK for DAI serial interface.
• DAI interface uses automatic detection of LRCK/M CLK ratio to configure internal DAI/SRC clocks.
• All PWM Processing clocks generated internally via: – An external crystal - 24.576 MHz to 54 MHz, or – XTI input pin capable of supporting a cl ock signal at the VDX voltage level.
• Programmable divide of XTI by 1, 2, 4, 8 for SYS_CLK output.
• Programmable divide of XTI by 32, 64, 128, 256 fo r PS_SYNC (power supply synchronization signal). Digital Audio Playback
• Supports 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kH z, 176.4 kHz and 192 kHz sample frequencies.
• High performance sample rate converter.
• 16, 20 and 24 bit audio sample lengths.
• De-emphasis for 32 kHz, 44.1 kHz, 48 kHz.

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• Digital volume cont rol with soft ramp.
• Individual channel volume gain, attenuation and mute capability; +24 to -127 dB in 0.25 dB steps.
• Master volume attenuation; +24 to -127 dB in 0.25 dB steps.
• Peak Detect and Volume Limiter with programmable attack and release rates.
• Signal-clipping in terrupt indicator. Additional Features
• Contains a two-stage digital output filt er for speaker impedance compensation.
• Provides 7 programmable GPIO pins with interrupt gene ration for easily interfacing to a variety of com- monly available power state parts. Interrupts can be masked.
• Selectable over-sample rate for increased audio bandwidth.
• Power supply clock output, PS_SYNC, with programmable divider

4.3 Clock Generation

• FsIn Domain: – DAI_MCLK, minimum 128Fs
• FsOut Domain: – XTI/XTO (Fundamental or 3 rd overtone crystal), or – Clock signal on XTI (VDX is used to set logic voltage level) DAI_SCLK DAI_SDINx Digital Audio Input Port DAI_MCLK DAI_LRCK Ratio Detect SYS_CLK XTI XTO PWM Engine VOL mute PEAK DETECT SRC 2-pole Load Compensation Filter 128Fs LIMITER Multibit Modulator Σ Master Volume Channel Volume Over Sample (OSRATE) Delay Delay XTAL / CLKIN 1,2,4,8 Clock Control PWM_MCLK MOD_MCLK SRC_MCLK (128Fs) PSR Feedback PWM_OUT+ PWM_OUT- FsIn FsOut 1, 1.5, 2, 3, 4, 6, 8 AM Freq. Hop (AM_FREQ_HOP) 2.25 1,1.5, 2,4 Over Sample (OSRATE) De- Emphasis

Figure 13. CS44800 Data Flow Diagram (Single Channel Shown)

4.3.1 FsIn Domain Clocking

Common DAI_MCLK frequencies and sample rates are shown in Table 1.

4.3.2 FsOut Domain Clocking

Table 1. Common DAI_MCLK Frequencies Figure 14. Fundamental Mode Crystal Configuration

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Figure 15. 3rd Overtone Crystal Configuration Figure 16. CS44800 Internal Clock Generation

4.4 FsIn Clock Domain Modules

4.4.1 Digital Audio Input Port

the data bits and must be synchronously derived from the master clock. 2's complement binary form with the MSB first in all formats. data line. Table 2 outlines the serial port channel allocations. configuration bits in the “Misc. Configuration (address 04h)” on page 52. Table 2. DAI Serial Audio Port Channel Allocations

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4.4.1.1 I²S Data Format

DAI_LRCK is low; the right channel data is presented when DAI_LRCK is high.

4.4.1.2 Left-Justified Data Format

is presented when DAI_LRCK is high and the right channel data is presented when DAI_LRCK is low. Figure 17. I²S Serial Audio Formats Figure 18. Left-Justified Serial Audio Formats

4.4.1.3 Right-Justifi ed Data Format

4.4.1.4 One Line Mode #1

Figure 19. Right-Justified Serial Audio Formats Figure 20. One Line Mode #1 Serial Audio Format

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4.4.1.5 One Line Mode #2

4.4.1.6 TDM Mode

transition and is valid on the rising edge of DA I_SCLK. DAI_SCLK must operate at a 256 Fs rate. Figure 21. One Line Mode #2 Serial Audio Format Figure 22. TDM Mode Serial Audio Format

4.4.2 Auto Rate Detect

receives the required clock rate. A minimum DAI_MCLK rate of 128Fs is required for proper operation. The supported DAI_MCLK to DAI_LRCK ratios are shown in Table 1 on page 26.

4.4.3 De-Emphasis

modate older audio recordings th at utilize pre-emphasis equalization as a means of noise reduction. 48 kHz is selected via the de-emphasis control bits in “Misc. Configuration (address 04h)” on page 52. Figure 23. De-Emphasis Curve

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4.5 FsOut Clock Domain Modules

4.5.1 Sample Rate Converter

ing modes that keep the PWM switching frequency fixed. very stable crystal or oscillator. This results in very low jitter PWM output and higher dynamic range.

4.5.2 Load Compensation Filter

switching clock is highly dependant on the resistive load (speaker) attached. Compensation Filter - Fine Adjust (CHXX_FINE[5:0])” on page 63.

4.5.3 Digital Volume and Mute Control

SZC[1:0] bits in “Volume Control Configuration (address 06h)” on page 55. Table 3. Load Compensation Example Settings

ger (addresses 09h - 10h)” on page 58. Volume control changes are programmable to ramp in increments of 0.125 dB at a variable rate controlled by the SZC[1:0] bits. Each PWM channel output can be independently muted via mute control bits in the register “Channel Mute (address 13h)” on page 60. When enabled, each CHXX_MUTE bit attenuates the corresponding PWM channel to its maximum value (-127 dB). When the CHXX_MUTE bit is disabled, the corresponding PWM channel returns to the atten- uation level set in the Volume Control register. The attenuation is ramped up and down at the rate spec- ified by the SZC[1:0] bits.

4.5.4 Peak Detect / Limiter

The CS44800 has the ability to limit the maximum signal amplitude to prevent clipping. The “Peak Limiter Control Register (address 15h)” on page 60 is used to configure the peak detect and limiter engines’ op- eration. Peak Signal Limiting is performed by digital attenuation. The attack rate is determined by the “Lim- iter Attack Rate (address 16h)” on page 61. The release rate is determined by the “Limiter Release Rate (address 17h)” on page 61.

4.5.5 PWM Engines

There are four stereo PWM Engines: PWM_ENG_1, PWM_ENG_2, PWM_ENG_3 and PWM_ENG_4. Each PWM can handle one stereo pair and connects to a driver or a pair of drivers, depending on the output configuration. Each PWM Engine receives the master clock, PWM_MCLK, from the Clock Control block, and the associated channel data and audio sample timings from the Sample Rate Converter. The “PWM Configuration Register (address 31h)” on page 68 is used to configure the PWM engines’ op- eration. This register controls the parameters of the PWM engines and can only be changed while the PWM engines are in the power down state. Features:

• U p t o 8 channel support
• 64 Quantization levels
• PSRR compensation feedback
• Programmable Over Sampling - interpolate times 2 (2 x) or filter by-pass. By-pass is intended for 384 kHz (single-speed) PWM switch rate support. The interpolate 2x filter is used to upsample the data to support a PWM switch rate of 768 kHz (double speed mode). This enables the output frequency re- sponse to extend past 20 kHz when the DAI sample rate is 96 kHz or 192 kHz.
• Programmable registers to move PWM edges for dela y adjustment. This lowers the overall noise con- tribution by allowing each PWM edge to switch at different times.
• Programmable Modulation Setup – Min/Max PWM pulse width allowed – Programmable Modulation index. The table below shows the available settings for the PWM Engine for a 384 kHz/768 kHz or 421.875 kHz/843.75 kHz PWM Fswitch rate verses the supported Fsin sample rates using the SRC with a maximum PWM_MCLK of 49.152 MHz/54 MHz.

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4.5.6 Interpolation Filter

Register (address 31h)” on page 68 and employs digital filtering to provide high quality interpolation.

4.5.7 Quantizer

required at the PWM drivers. Its stereo outputs are running at the PWM switch rate.

4.5.8 Modulator

4.5.9 PWM Outputs

ning at the PWM switch rate as determined by the settings shown in Table 4. Pulse Width Register (address 32h)” on page 69. Output. The delay is measured in periods of PWM_MCLK. Table 4. Typical PWM Switch Rate Settings

4.5.10 Power Supply Rejecti on (PSR) Real-Time Feedback

Inherent to most Class D power amplifier solutions is the requirement for a clean and well-regulated high voltage power supply. An y noise or tones present on the powe r rail will couple through each channel’s power MOSFET output device. These spurious distortion components on the output signal consist of dis- crete tones, which can be audible from the speaker, and tones that modulate around the audio signal be- ing played. To remove the requirement for a well-regulated power supply, and therefore reduce overall system costs, the rejection of harmonic distortion from the power supply and tones coupled onto the power rail is ac- complished by the patented power supply rejection realtime feedback. By using the CS4461 and associ- ated attenuation circuitry, the scaled AC and DC co mponents of the power supply rail are fed back into the PWM modulator. All delays through the feedback path have been minimized such that the noise can- cellation is accomplished in real-time allowing for substantial noise rejection within the output audio signal. See “Typical Connection Diagrams” on page 22 for examples on how to connect the external ADC (CS4461) to the CS44800 for PSR feedback, “Recommended PSR Calibration Sequence” on page 44, and the CS4461 datasheet.

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4.6 Control Port Desc ription and Timing

should remain static if no operation is required. the desired AD0 bit address state.

4.6.1 SPI Mode

as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. Figure 24. Control Port Timing in SPI Mode

4.6.2 I²C Mode

In I²C mode, SDA is a bidirectional da ta line. Data is clocked into and out of the part by the clock, SCL. CS44800 from the microcontroller after each transmitted byte. Autoincrement reads are not supported. Send 10011xx0 (chip address & write operation). Send MAP byte, auto increment off. Send stop condition, aborting write. Send 10011xx1(chip address & read operation). Figure 25. Control Port Timing, I²C Slave Mode Write Figure 26. Control Port Timing, I²C Slave Mode Read

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Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Each byte is separated by an acknowledge bit.

4.6.3 GPIOs

The CS44800 GPIO pins will have the following features:

• Data direction control.
• Programmable open-drain or push-pull driver when configured as an output pin.
• Maskable interrupt for GPIO[3:0] pins when set as a general purpose input.
• Level-sensitive or edge-trigger event selector for all GPIO pins.

4.6.4 Host Interrupt

The CS44800 has a comprehensive interrupt capability. The INT output pin is intended to drive the inter- rupt input pin on the host microcontroller. The INT pin may be set to be active low, active high or active low with an open-drain driver. This last mode is used for active low, wired-OR hook-ups, with multiple pe- ripherals connected to the microcontroller interrupt input pin. Many conditions can cause an interrupt, as listed in th e interrupt status register descriptions. See “Inter- rupt Status (address 2Ah) (read only)” on page 64. Each source may be masked off through mask register bits. In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer.

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decoupling capacitors. Y1 is the crystal and C3, C4, L1 and C5 are the associated components for the crystal circuit. used as much as possible around and in between all crystal circuit components to minimize noise. Figure 28. Recommended CS44800 Crystal Circuit Layout

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5.1 Reset and Power-Up

Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks, and configuration pins are stable. It is also recommended that the RST pin be activated if the voltage supplies drop below the recommended operating condition to prevent power-glitch- related issues. When RST is low, the CS44800 enters a low-power mode an d all internal states are reset, including the control port and registers. When RST is high, the control port becomes operational and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control Register will then cause the part to leave the low-power state and begin operation.

5.1.1 PWM PopGuard ® Transient Control

The CS44800 uses PopGuard® technology to minimize the effects of output transients during power-up and power-down. This technique reduces the audio transients commonly produced by half-bridge, single- supply amplifiers when implemented with external DC-blocking capacitors connected in series with the audio outputs. Each PWM channel can individually be controlled for ramp-up and ramp-down cycles. When the device is initially powered-up and configured for ramp-up, the PWMOUTxx outputs are clamped to GND. Following a write of a 0 to the PDN_PWMxx bit in the PWM Channel Power Down Control (ad- dress 03h) register, each output begins to increase the PWM duty cycle toward the bias voltage point. By a speed set by the RAMP_SPDx bits, the PWMOUTxx outputs will ramp from 0 V (GND) and reach the bias point (50% PWM duty cycle). This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the bias voltage, minimizing the power-up transient. To prevent an audible transient at the next power-on, the DC-blocking capacitors must fully discharge be- fore turning off the power. If full di scharge does not occur, a transient will occur when the audio outputs are initially clamped to GND. To prevent transients at power-down, the user must first mute the outputs. When this occurs, audio output ceases and the PWM duty cycle is approximately 50 % duty cycle, which represents the mute condition. Once the channels are powered down, the PWMOUTxx outputs slowly decrease the DC offset until it reaches GND. The time required to reach GND is de termined by the RAMP_SPD x bits. This allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on.

5.1.2 Recommended Power-Up Sequence

1. Hold RST low until the power supply and clocks are stable. In this state, all control port registers are reset to the default settings. The PWMOUTxx pins are driven low. 2. The SYS_CLK pin will output a divid ed-down clock of the signal attached to the XTI pin. If the MUTE pin is held low, SYS_CLK is equal to the XTI frequency. If the MUTE pin is held high, then SYS_CLK is equal to the XTI frequency divided by 2. 3. Bring RST high. The device will remain in a low power state and all registers will contain the specified default value. The logic state of the MUTE pin will be latched and used to specify the clock divider for SYS_CLK. The control port will be accessible at this time. 4. With the CS44800 in the power-down state, PDN bit is ‘1’b, set up the required PWM configuration registers and volume control registers. Configure the GPIO pins for normal operation. Do not enable the power stages at this time. 5. Mute all channel outputs by setting the corresponding CHxx_MUTE bits to ‘1’b.

1. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘11’b and the required ramp speed, to initiate a ramp cycle when the channel is powered on. Set MIN_PULSE[4:0] to ‘00000’b. 7. Set the PDN bit to ‘0’b to take the CS44800 out of the power-down state. 8. Start all clocks on the DAI interf ace (DAI_MCLK, DAI_SCLK, DAI_LRCK). This will initiate the SRC to begin the lock sequence. The SRC lock function can be configured to cause an interrupt condition when lock has been completed. This will be indicated by an active INT signal. 9. Wait for the SRC to lock. 10.If using the PSR feedback, jump to “Recommended PSR Calibration Sequence” on page 44. When finished, continue to step 12. If not using PSR feedback, continue to step 12. 11.Set the appropriate GPIO pin, or other cont rol signal, to enable the power output stage. 12.Enable each channel’s PWM modulator by setting the PDN_PWMxx bit to ‘0’b. If full-bridged, go to step 14. If single-ended (half-bridged), this will initiate a sequence which will slowly increase the DC voltage, from 0V to Vpower÷2, across the AC coupling capacitor. This will eliminate the instantaneous charge across the capacitor which would have caused an audible pop from the speaker. 13.Wait for the ramp-up sequence to complete. The ramp-up function can be configured to cause an interrupt condition when the ramp period has completed. This will be indicated by an active INT signal. Once the ramp-up sequence has completed, set the RAMP[1:0] bits to ‘01’b 14.For full-bridged power output stage configurations, the ramp-up sequence is not required. Enabling the power output stage will not cause an audible pop from the speaker. 15.If using the PSR feedback, se t the FEEDBACK_EN bit to ‘1’b. 16.Un-mute all active channels. 17. At this point, the CS44800 is ready to accept audio samples and begin playback.

5.1.3 Recommended PSR Calibration Sequence

1. Set the DEC_SHIFT[2:0]/DEC _SCALE[18:0] coefficient (CPSR) to decimal 1.0 (register 35h = 22h, 36h = 00h, 37h = 00h). 2. Set the PSR_RESET bit to ‘1’b. 3. Set the PSR_EN bit to ‘1’b. 4. Set the PSR_EN bit to ‘0’b. 5. Read DEC_OUTD[23:0]. 6. See Figure 30 to adjust the DEC_SHIFT[2:0]/DEC_SCALE[18:0] registers. 7. Continue Recommended Power-Up Sequence.

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5.1.4 Recommended Power-Down Sequence

1. Mute all channel outputs by setting the corresponding CHxx_MUTE bits to ‘1’b.
2. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘01’b and the required ramp speed, to initiate

a ramp cycle when the channel is powered down.

1. Power down each channel’s PWM modulator by setting the PDN_PWMxx bit to ‘1’b. If single-ended, this will initiate a sequence which

will slowly decrease the DC voltage, from Vpower÷2 to 0 V, across the AC-coupling capacitor.

1. The ramp-down function can be configured to cause an interrupt condition when the ramp period has completed. This will be indicated
2. Once the ramp-down sequence has completed, set the appropriate GPIO pin, or other control signal, to power down the power output
3. For full-bridged power output stage configurations, the ramp-down sequence is not required. Powering down the power output st age

will not cause an audible pop from the speaker.

1. Concurrently with the ramp-down sequence, if desired, stop all clocks on the DAI interface (DAI_MCLK, DAI_SCLK, DAI_LRCK).

Figure 30. PSR Calibration Sequence

1. Set the PDN bit to ‘1’b to put the CS44800 in the power down state.

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1. REGISTER QUICK REFERENCE Addr Function 7 6 5 4 3 2 1 0 01h ID / Rev. CHIP_ID3 CHIP_ID2 CHIP_ID1 CHIP_ID0 REV_ID3 REV_ID2 REV_ID1 REV_ID0 page 50 default 1 1 0 0 0 0 0 1 02h Clock Config / Power Control EN_SYS_CLK SYS_CLK_DIV1 SYS_CLK_DIV0 PWM_MCLK_DIV1 PWM_MCLK_DIV0 PDN_XTAL PDN_OUTPUT_MO DE PDN page 51. default 1 0 0 0 0 0 0 1 03h Chnl Power Down PDN_PWMB4 PDN_PWMA4 PDN_PWMB3 PDN_PWMA3 PDN_PWMB2 PDN_PWMA2 PDN_PWMB1 PDN_PWMA1 page 52. default 1 1 1 1 1 1 1 1 04h Misc. Config. DIF2 DIF1 DIF0 RESERVED AM_FREQ_HOP FREEZE DEM1 DEM0 page 53 default 0 0 1 0 0 0 0 0 05h Ramp Config RESERVED RESERVED RESERVED RAMP1 RAMP0 RESERVED RAMP_SPD1 RAMP_SPD0 page 54 default 0 0 0 0 0 0 0 1 06h Vol Control Config SNGVOL SZC1 SZC0 RESERVED MUTE_50/50 SRD_ERR SRU_ERR AMUTE page 55 default 0 1 0 0 0 0 0 1 07h Master Vol. Control - Integer MSTR_IVOL7 MSTR_IVOL6 MSTR_IVOL5 MSTR_IVOL4 MSTR_IVOL3 MSTR_IVOL2 MSTR_IVOL1 MSTR_IVOL0 page 57 default 0 0 0 0 0 0 0 0 08h Master Vol. Control - Fraction RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED MSTR_FVOL1 MSTR_FVOL0 page 57 default 0 0 0 0 0 0 0 0 09h Channel A1 Vol. Control - Integer CHA1_IVOL7 CHA1_IVOL6 CHA1_IVOL5 CHA1_IVOL4 CHA 1_IVOL3 CHA1_IVOL2 CHA1_IVOL1 CHA1_IVOL0 page 59 default 0 0 0 0 0 0 0 0 0Ah Channel B1 Vol. Control - Integer CHB1_IVOL7 CHB1_IVOL6 CHB1_IVOL5 CHB1_IVOL4 CHB 1_IVOL3 CHB1_IVOL2 CHB1_IVOL1 CHB1_IVOL0 page 59 default 0 0 0 0 0 0 0 0 0Bh Channel A2 Vol. Control - Integer CHA2_IVOL7 CHA2_IVOL6 CHA2_IVOL5 CHA2_IVOL4 CHA 2_IVOL3 CHA2_IVOL2 CHA2_IVOL1 CHA2_IVOL0 page 59 default 0 0 0 0 0 0 0 0 0Ch Channel B2 Vol. Control - Integer CHB2_IVOL7 CHB2_IVOL6 CHB2_IVOL5 CHB2_IVOL4 CHB 2_IVOL3 CHB2_IVOL2 CHB2_IVOL1 CHB2_IVOL0 page 59 default 0 0 0 0 0 0 0 0 0Dh Channel A3 Vol. Control - Integer CHA3_IVOL7 CHA3_IVOL6 CHA3_IVOL5 CHA3_IVOL4 CHA 3_IVOL3 CHA3_IVOL2 CHA3_IVOL1 CHA3_IVOL0 page 59 default 0 0 0 0 0 0 0 0 0Eh Channel B3 Vol. Control - Integer CHB3_IVOL7 CHB3_IVOL6 CHB3_IVOL5 CHB3_IVOL4 CHB 3_IVOL3 CHB3_IVOL2 CHB3_IVOL1 CHB3_IVOL0 page 59 default 0 0 0 0 0 0 0 0 0Fh Channel A4 Vol. Control - Integer CHA4_IVOL7 CHA4_IVOL6 CHA4_IVOL5 CHA4_IVOL4 CHA 4_IVOL3 CHA4_IVOL2 CHA4_IVOL1 CHA4_IVOL0 page 59. default 0 0 0 0 0 0 0 0 10h Channel B4 Vol. Control - Integer CHB4_IVOL7 CHB4_IVOL6 CHB4_IVOL5 CHB4_IVOL4 CHB 4_IVOL3 CHB4_IVOL2 CHB4_IVOL1 CHB4_IVOL0 page 59. default 0 0 0 0 0 0 0 0

11h Channel Vol. Con- trol 1-Fraction CHB2_FVOL1 CHB2_FVOL0 CHA2_FVOL1 CHA2_FVOL0 CHB1_FVOL1 CHB1_FVOL0 CHA1_FVOL1 CHA1_FVOL0 page 59. default 0 0 0 0 0 0 0 0 12h Channel Vol. Con- trol 2-Fraction CHB4_FVOL1 CHB4_FVOL0 CHA4_FVOL1 CHA4_FVOL0 CHB3_FVOL1 CHB3_FVOL0 CHA3_FVOL1 CHA3_FVOL0 page 59 default 0 0 0 0 0 0 0 0 13h Channel Mute CHB4_MUTE CHA4_MUTE CHB3_MUTE CHA3_MUTE CHB2_MUTE CHA2_MUTE CHB1_MUTE CHA1_MUTE page 60 default 0 0 0 0 0 0 0 0 14h Channel Invert CHB4_INV CHA4_INV CHB3_INV CHA3_INV CHB2_INV CHA2_INV CHB1_INV CHA1_INV page 60 default 0 0 0 0 0 0 0 0 15h Peak Limiter Control RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED LIMIT_ALL LIMIT_EN page 61 default 0 0 0 0 0 0 0 0 16h Limiter Attack Rate ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0 page 61 default 0 0 0 1 0 0 0 0 17h Limiter Release Rate RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0 page 62 default 0 0 1 0 0 0 0 0 18h Chnl A1 Comp. Filter - Coarse Adj RESERVED RESERVED CHA1_CORS5 CHA1_CORS4 CHA1_ CORS3 CHA1_CORS2 CHA 1_CORS1 CHA1_CORS0 page 62 default 0 0 0 0 0 0 0 0 19h Chnl A1 Comp. Filter - Fine Adj RESERVED RESERVED CHA1_FINE5 CHA1_FINE4 CHA1_FINE3 CHA1_FINE2 CHA1_FINE1 CHA1_FINE0 page 63 default 0 0 0 0 0 0 0 0 1Ah Chnl B1 Comp. Filter - Coarse Adj RESERVED RESERVED CHB1_CORS5 CHB1_CORS4 CHB1_ CORS3 CHB1_CORS2 CHB 1_CORS1 CHB1_CORS0 page 62 default 0 0 0 0 0 0 0 0 1Bh Chnl B1 Comp. Filter - Fine Adj RESERVED RESERVED CHB1_FINE5 CHB1_FINE4 CHB1_FINE3 CHB1_FINE2 CHB1_FINE1 CHB1_FINE0 page 63 default 0 0 0 0 0 0 0 0 1Ch Chnl A2 Comp. Filter - Coarse Adj RESERVED RESERVED CHA2_CORS5 CHA2_CORS4 CHA2_ CORS3 CHA2_CORS2 CHA 2_CORS1 CHA2_CORS0 page 62 default 0 0 0 0 0 0 0 0 1Dh Chnl A2 Comp. Filter - Fine Adj RESERVED RESERVED CHA2_FINE5 CHA2_FINE4 CHA2_FINE3 CHA2_FINE2 CHA2_FINE1 CHA2_FINE0 page 63 default 0 0 0 0 0 0 0 0 1Eh Chnl B2 Comp. Filter - Coarse Adj RESERVED RESERVED CHB2_CORS5 CHB2_CORS4 CHB2_ CORS3 CHB2_CORS2 CHB 2_CORS1 CHB2_CORS0 page 62 default 0 0 0 0 0 0 0 0 1Fh Chnl B2 Comp. Filter - Fine Adj RESERVED RESERVED CHB2_FINE5 CHB2_FINE4 CHB2_FINE3 CHB2_FINE2 CHB2_FINE1 CHB2_FINE0 page 63 default 0 0 0 0 0 0 0 0 20h Chnl A3 Comp. Filter - Coarse Adj RESERVED RESERVED CHA3_CORS5 CHA3_CORS4 CHA3_ CORS3 CHA3_CORS2 CHA 3_CORS1 CHA3_CORS0 page 62 default 0 0 0 0 0 0 0 0 Addr Function 7 6 5 4 3 2 1 0

48 DS632F1

21h Chnl A3 Comp. Filter - Fine Adj RESERVED RESERVED CHA3_FINE5 CHA3_FINE4 CHA3_FINE3 CHA3_FINE2 CHA3_FINE1 CHA3_FINE0 page 63 default 0 0 0 0 0 0 0 0 22h Chnl B3 Comp. Filter - Coarse Adj RESERVED RESERVED CHB3_CORS5 CHB3_CORS4 CHB3_CORS3 CHB3_CORS2 CHB3_CORS1 CHB3_CORS0 page 62 default 0 0 0 0 0 0 0 0 23h Chnl B3 Comp. Filter - Fine Adj RESERVED RESERVED CHB3_FINE5 CHB3_FINE4 CHB3_FINE3 CHB3_FINE2 CHB3_FINE1 CHB3_FINE0 page 63 default 0 0 0 0 0 0 0 0 24h Chnl A4 Comp. Filter - Coarse Adj RESERVED RESERVED CHA4_CORS5 CHA4_CORS4 CHA4_CORS3 CHA4_CORS2 CHA4_CORS1 CHA4_CORS0 page 62 default 0 0 0 0 0 0 0 0 25h Chnl A4 Comp. Filter - Fine Adj RESERVED RESERVED CHA4_FINE5 CHA4_FINE4 CHA4_FINE3 CHA4_FINE2 CHA4_FINE1 CHA4_FINE0 page 63 default 0 0 0 0 0 0 0 0 26h Chnl B4 Comp. Filter - Coarse Adj RESERVED RESERVED CHB4_CORS5 CHB4_CORS4 CHB4_CORS3 CHB4_CORS2 CHB4_CORS1 CHB4_CORS0 page 62 default 0 0 0 0 0 0 0 0 27h Chnl B4 Comp. Filter - Fine Adj RESERVED RESERVED CHB4_FINE5 CHB4_FINE4 CHB4_FINE3 CHB4_FINE2 CHB4_FINE1 CHB4_FINE0 page 63 default 0 0 0 0 0 0 0 0 28h Interrupt Mode Control INT1 INT0 RESERVED RESERVED RESERVED RESERVED RESERVED OVFL_L/E page 63 default 0 0 0 0 0 0 0 0 29h Interrupt Mask M_SRC_UNLOCK M_SRC_LOCK M_RMPUP_DONE M_RMPDN_DONE M_MUTE_DONE M_OVFL_INT RESERVED RESERVED page 64 default 0 0 0 0 0 0 0 0 2Ah Interrupt Status SRC_UNLOCK SRC_LOCK RMPUP_DO NE RMPDN_DONE MUTE_DONE OVFL_INT GPIO_INT RESERVED page 64 default 0 0 0 0 0 0 0 0 2Bh Chnl Over Flow Sta- tus CHB4_OVFL CHA4_OVFL CHB3_OVFL CHA3_OVFL CHB2_OVFL CHA2_OVFL CHB1_OVFL CHA1_OVFL page 66 default 0 0 0 0 0 0 0 0 2Ch GPIO Pin I/O RESERVED GPIO6_I/O GPIO5_I/O GPIO4_I/O GPIO3_I/O GPIO2_I/O GPIO1_I/O GPIO0_I/O page 66 default 0 0 0 0 0 0 0 0 2Dh GPIO Pin Polar- ity/Type RESERVED GPIO6_P/T GPIO5_P/T GPIO4_P/T GPIO3_P/T GPIO2_P/T GPIO1_P/T GPIO0_P/T ppage 66 default 0 1 1 1 1 1 1 1 2Eh GPIO Pin Level/Edge trigger RESERVED GPIO6_L/E GPIO5_L/E GPIO4_L/E GPIO3_L/E GPIO2_L/E GPIO1_L/E GPIO0_L/E page 67 default 0 0 0 0 0 0 0 0 2Fh GPIO Pin Status RESERVED GPIO6_STATUS GPIO5_STATUS GPIO4_STATUS GPIO3_STATUS GPIO2_STATUS GPIO1_STATUS GPIO0_STATUS page 67 default X X X X X X X X 30h GPIO Interrupt Mask RESERVED RESERVED RESERVED RESERVED M_GPIO3 M_GPIO2 M_GPIO1 M_GPIO0 page 68 default 0 0 0 0 0 0 0 0 Addr Function 7 6 5 4 3 2 1 0

31h PWM Config OSRATE RESERVED RESERVED A1/B1_OUT_CNFG A2/ B2_OUT_CNFG A3_OUT_CNFG B3_OUT_CNFG A4/B4_ OUT_CNFG page 68 default 0 0 0 0 0 0 0 0 32h PWM Minimum Pulse Width DISABLE_ PWMOUTxx- RESERVED RESERVED MIN_PULSE4 MIN_PULSE3 MIN_PULSE2 MIN_PULSE1 MIN_PULSE0 page 69 default 0 0 0 0 0 0 0 0 33h PWMOUT Delay DIFF_DLY2 DIFF_DLY1 DIFF_DLY0 CHNL_DLY4 CHNL_DLY3 CHNL_DLY2 CHNL_DLY1 CHNL_DLY0 page 70 default 0 0 0 0 0 0 0 0 34h PSR / Power Supply Config PSR_EN PSR_RESET FEEDBACK_ EN RESERVED RESERVED PS_SYNC_DIV2 PS_SYNC_DIV1 PS_SYNC_DIV0 page 73 default 0 0 0 0 0 0 0 0 35h PSR_Decimator Scaled RESERVED DEC_SHIFT2 DEC_SHIFT1 DEC_SHIFT0 RESE RVED DEC_SCALED18 DEC_SCALED17 DEC_SCALED16 page 74 default 0 0 1 0 0 0 1 0 36h PSR_Decimator Scaled DEC_SCALED15 DEC_SCALED14 DEC_SCALED13 DEC_SCALED12 DEC_SCALED11 DEC_SCALED10 DEC_SCALED09 DEC_SCALED08 page 74 default 0 1 0 1 1 0 0 0 37h PSR_Decimator Scaled DEC_SCALED07 DEC_SCALED06 DEC_SCALED05 DEC_SCALED04 DEC_SCALED03 DEC_SCALED02 DEC_SCALED01 DEC_SCALED00 page 74 default 0 1 1 0 1 0 0 0 38h Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED default 0 0 0 0 0 0 0 0 39h Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED default 0 0 0 0 0 0 0 0 3Ah Reserved RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED default 0 0 0 0 0 0 0 0 3Bh PSR_Decimator Outd DEC_OUTD23 DEC_OUTD22 DEC_OUTD21 DEC_OUTD20 DEC_OUTD19 DEC_OUTD18 DEC_OUTD17 DEC_OUTD16 page 75 default 0 0 0 0 0 0 0 0 3Ch PSR_Decimator Outd DEC_OUTD15 DEC_OUTD14 DEC_OUTD13 DEC_OUTD12 DEC_OUTD11 DEC_OUTD10 DEC_OUTD09 DEC_OUTD08 page 75 default 0 0 0 0 0 0 0 0 3Dh PSR_Decimator Outd DEC_OUTD07 DEC_OUTD06 DEC_OUTD05 DEC_OUTD04 DEC_OUTD03 DEC_OUTD02 DEC_OUTD01 DEC_OUTD00 page 75 default 0 0 0 0 0 0 0 0 Addr Function 7 6 5 4 3 2 1 0

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1. REGISTER DESCRIPTION All registers are read/write except for I.D. and Revision Register, Interrupt Status an d Decimator OutD registers which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description.

7.1 Memory Address Pointer (MAP)

7.1.1 Increment (INCR)

Default = 1 Function: memory address pointer auto increment control – 0 - MAP is not incremented automatically. – 1 - Internal MAP is automatically in cremented after each read or write.

7.1.2 Memory Addr ess Pointer (MAPx)

Default = 0000001 Function: Memory address pointer (MAP). Sets the register address that will be read or written by the control port. 7.2 CS44800 I.D. and Revision Re gister (address 01h) (Read Only) 7.2.1 Chip I.D. (Chip_IDx) Default = 1100 Function: I.D. code for the CS44800. Permanently set to 1100.

7.2.2 Chip Revision (Rev_IDx)

Default = 0001 Function: CS44800 revision level. Revision A is coded as 0001. 76543210 INCR MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0 76543210 CHIP_ID3 CHIP_ID2 CHIP_ID1 CHIP_ID0 REV_ID3 REV_ID2 REV_ID1 REV_ID0

7.3 Clock Configuration and Power Control (address 02h)

7.3.1 Enable SYS_CLK Output (EN_SYS_CLK)

Default = 1 Function: This bit enables the driv er for the SYS_CLK signal. If the SYS_CLK output is unused, this bit should be set to ‘0’b to disable the driver.

7.3.2 SYS_CLK Clock Divider Settings (SYS_CLK_DIV[1:0])

Default = 00 Function: These two bits determine the divider for the XTAL clock signal for generating the SYS_CLK signal. During a reset condition, with the RST input pin held low, the logic level on the MUTE input pin will determine the divider used for the SYS_CLK output. If MUTE is pulled low, the SYS_CLK divider will be set to divide the clock frequency on XTI by a factor of 1. If the MUTE pin is pulled high, t he SYS_CLK output will be set to perform a divide-by-2 on the XTI clock. The state of the MUTE pin will be latched on the rising edge of the RST. The MUTE pin can then be used as defined.

7.3.3 PWM Master Clock Divider Settings (PWM_MCLK_DIV[1:0])

Default = 00 Function: These two bits determine the divider for the XTAL clock signal for generating the PWM_MCLK signal.

7.3.4 Power Down XTAL (PDN_XTAL)

Default = 0 0 - Crystal Oscillator Circuit is running. 1 - Crystal Oscillator Circuit is powered down. Function: This bit is used to power down the crystal oscillator circuitry when not being used. When using a clock signal attached to the XTI input, this bit should be set to ‘1’b. 76 5 4 3 2 1 0 EN_SYS_CLK SYS_CLK_DIV1 SYS_CLK_DIV0 PWM_MCLK_D IV1 PWM_MCLK_DIV0 PDN_XTAL PDN_OUTPUT_MODE PDN SYS_CLK_DIV[1:0] SYS_CL K Clock Divider

00 Use state of MUTE input pin following RST

01 Divide by 2

10 Divide by 4

11 Divide by 8

PWM_MCLK_DIV[1:0] PWM Master Clock Divider

00 Divide by 1

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7.3.5 Power Down Output Mode (PDN_OUTPUT_MODE)

Default = 0 0 - PWM Outputs are driven low during power down 1 - PWM Outputs are driven to the inactive state during power down Function: This bit is used to select the power-down state of the PWM output signals. When set to 0, each channel which has been powered down, follo wing the ramp-down cycle if enable d, will drive the output signals, PWMOUTxx+ and PWMOUTxx-, low. When set to 1, each channel which has been powe red down, following the ra mp-down cycle if enabled, will drive the output signals to the inactive state. PWMOUTxx+ is dr iven low and PWMOUTxx- is driven high.

7.3.6 Power Down (PDN)

Default = 1 0 - Normal Operation 1 - Power down Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation can occur.

7.4 PWM Channel Power Down Control (address 03h)

7.4.1 Power Down PW M Channels (PDN_PWMB4:PDN_PWMA1)

Default = 11111111 0 - Normal Operation 1 - Power down PWM channel Function: The specific PWM channel is in the power-down state. All processing is halted for the specific channel, but does not alter the setup or delay register values. The PWM output signals are driven to the appropriate logic level as defined by the Power-Down Output Mode bit, PDN_OUTPUT_MODE. When set to normal operation, the specific channel will power up according to the state of the RAMP[1:0] bits and the channel output configuration selected. When transitioning from normal operation to power down, the specific chan- nel will power down according to the state of the RAMP[1:0] bits and the channel output configuration se- lected. Ramp control is found in “Ramp Configuration (address 05h)” on page 54. 76543210 PDN_PWMB4 PDN_PWMA4 PDN_PWMB3 PDN_PWMA3 PDN_PWMB2 PDN_PWMA2 PDN_PWMB1 PDN_PWMA1

7.5.1 Digital Interface Format (DIFX)

options are detailed in Figures 17 - 22.

7.5.2 AM Frequency H opping (AM_FREQ_HOP)

7.5.3 Freeze Controls (FREEZE)

changes, then disable the FREEZE bit. Table 5. Digital Audio Interface Formats

54 DS632F1

7.5.4 De-Emphasis Control (DEM[1:0])

Default = 00 00 - no de-emphasis 01 - 32 kHz de-emphasis filter 10 - 44.1 kHz de-emphasis filter 11 - 48 kHz de-emphasis filter Function: Enables the appropriate digital filter to maintain the standard 15 ms/50 ms digital de-emphasis filter re- sponse.

7.6 Ramp Configuration (address 05h)

7.6.1 Ramp-Up/Down Setting (RAMP[1:0])

Default = 00 00 - Ramp-up and ramp-down are disabled 01 - Ramp-up is disabled. Ramp-down is enabled. 10 - Reserved 11 - Ramp-up and ramp-down are enabled. Note that after a ramp-up sequence has completed, audio will not play until RAMP[1:0] is set to 01. Function: When ramping is enabled, the duty cycle of the output PWM signal is increased (ramp-up) or decreased (ramp-down) at a rate determined by the Ramp Speed variable (RAMP_SPDx). This function is used in single-ended applications to reduce pops in the ou tput caused by the DC-blo cking capacitor. When the ramp-up/down function is disabled in single-ended applications, there will be an abrupt change in the out- put signal. Refer to Section 5.1.1 . If ramp-up or down is not needed, as in a full-bridge application, these bits should be set to 00. If ramp- up or down is needed, as in a single-ended half-bridge application, these bits must be used in the proper sequence as outlined in “Recommended Power-Up Sequence” on page 43 and “Recommended Power- Down Sequence” on page 45.

7.6.2 Ramp Speed (RAMP_SPD[1:0])

Default = 01 00 - Ramp speed = approximately 0.1 seconds 01 - Ramp speed = approximately 0.2 seconds 10 - Ramp speed = approximately 0.3 seconds 11 - Ramp speed = approximately 0.65 seconds Function: This feature is used in single-ended applications to reduce pops in the output caused by the DC-blocking capacitor. The Ramp Speed sets the time for the PWM signal to linearly ramp-up and down from the bias point (50% PWM duty cycle). Refer to Section 5.1.1 76543210 RESERVED RESERVED RESERVED RAMP1 RAMP0 RESERVED RAMP_SPD1 RAMP_SPD0

7.7 Volume Control Conf iguration (address 06h)

7.7.1 Single Volume Control (SNGVOL)

Default = 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control reg- isters when this function is disabled. When enabled, the volume on all channels is determined by the A1 Channel Volume Control register. The other Volume Control registers are ignored.

7.7.2 Soft Ramp and Zero Cross Control (SZC[1:0])

Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected, all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a tim- eout period (approximately 18.7 ms for a PWM switch rate of 384/768 kHz and 17.0 ms for a PWM switch rate of 421.875/843.75 kHz) if the signal does not enc ounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that si gnal level changes, either by attenuation changes or muting, will occur in 1/8-dB steps and be implemented on a signal zero crossing. The 1/8-dB level change will occur after a timeout period (approximately 18. 7 ms for a PWM switch rate of 384/768 kHz and 17.0 ms for a PWM switch rate of 421.875/843.75 kHz) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

7.7.3 Enable 50% Duty Cycle fo r Mute Condition (MUTE_50/50)

Default = 0 0 - Disabled 1 - Enabled Function: This bit enables the modulator to output an exact 50%-duty-cycle PWM signal (not modulated), which cor- responds to digital silence, for all mute conditions. The muting function is affected, similar to volume con- 76543210 SNGVOL SZC1 SZC0 RESERVED MUTE_50/50 SRD_ERR SRU_ERR AMUTE

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trol changes, by the Soft and Zero Cross bits (SZC[1:0]). This bit does not cause a mute condition to occur. The MUTE_50/50 bit only defines operation during a normal mute condition. When MUTE_50/50 is set and a mute condition occurs, PSR will not affe ct the output of the modulator, regardless if PSR is enabled. Output noise may be increased in this case if the noise on the high voltage power supply is greater than the system noise. Therefore, it is recommended that if a noisy power supply is used in a single-ended half-bridge configuratio n with PSR enabled, MUTE_50/50 should be disabled and a normal, modulated mute should be used. This will allow the modulator to use the PSR feedback to reject power supply noise and improve system performance.

7.7.4 Soft Ramp-Down on Interface Error (SRD_ERR)

Default = 0 0 - Disabled 1 - Enabled Function: A mute will be performed upon detection of a timing error on the Digital Audio Interface or if an SRC_LOCK error has occurred. An SRC_LOCK interrupt is an indication that the sample rate converter timings have become unstable, or have changed abruptly. Audio data from the SRC is no longer consid- ered valid and could cause unwanted pops or clicks. When this feature is enabled, this mute is affected, similar to atte nuation changes, by the Soft and Zero Cross bits (SZC[1:0]). When disabled, an immediate mute is performed on detection of an error. Note: For best results, it is recommended that this bit be used in conjunction with the SRU_ERR bit.

7.7.5 Soft Ramp-Up on Recover ed Interface Error (SRU_ERR)

Default = 0 0 - Disabled 1 - Enabled Function: An un-mute will be performed after a MCLK/LRCK ratio change, recovered DAI timing error, or after the SRC has gained lock. When this feature is enabled, this un-mute is affected, similar to attenuation chang- es, by the Soft and Zero Cross bits (SZC[1:0]). W hen disabled, an immediate un-mute is performed in these instances. Note: For best results, it is recommended that this bit be used in conjunction with the SRD_ERR bit.

7.7.6 Auto-Mute (AMUTE)

Default = 1 0 - Disabled 1 - Enabled Function: The PWM converters of t he CS44800 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will releas e the mute. Detection and muting is done independently for each channel. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]).

7.8 Master Volume Control - Integer (address 07h)

7.8.1 Master Volume Control - Integer (MSTR_IVOL[7:0])

0 dB are in two’s complement form.

7.9 Master Volume Contro l - Fraction (address 08h)

7.9.1 Master Volume Control - Fraction (MSTR_FVOL[1:0])

1. Convert the decimal integer to binary. This is MSTR_IVOL[7:0].
2. Select the bit representation of the desired 0. 25 fractional increment. This is MSTR_FVOL[1:0].

Table 6. Master Integer Volume Settings

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1. Convert the decimal integer to binary. This is MSTR_IVOL[7:0].
2. Select the bit representation of the desired 0.25 fractional increment. This is MSTR_FVOL[1:0].
3. Concatenate MSTR_IVOL[7:0]: MSTR_FVOL[1:0] to form a 10-bit binary value.
4. Perform a 2’s complement conversion on all 10 bits.

The upper 8 bits are now the new MSTR_FVOL[7:0] and the two lower bits are MSTR_FVOL[1:0].

1. Concatenate MSTR_IVOL[7:0]: MSTR_FVOL[1:0] to form a 10-bit binary value.
2. Perform a 2’s complement conversion on all 10 bits.
3. Convert the 10-bit binary number to a decimal value.
4. Divide the decimal value by 4.

Table 7. Master Fractional Volume Settings

7.10 Channel XX Volume Contro l - Integer (addresses 09h - 10h)

7.10.1 Channel Volume Contro l - Integer (CHXx_IVOL[7:0])

0 dB are in two’s complement form.

7.11 Channel XX Volume Contro l1 - Fraction (address 11h)

7.12 Channel XX Volume Cont rol2 - Fraction (address 12h)

7.12.1 Channel Volume Contro l - Fraction (CHXX_FVOL[1:0])

bers to 2’s complement binary values. Table 8. Channel Integer Volume Settings

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7.13 Channel Mute (address 13h)

7.13.1 Independent Channel Mute (CHXX_MUTE)

tenuation changes, by the Soft and Zero Cross bits (SZC[1:0]).

7.14 Channel Invert (address 14h)

7.14.1 Invert Signal Polarity (CHXX_INV)

When enabled, these bits will invert the signal polarity of their respective channels. Table 9. Channel Fractional Volume Settings

7.15 Peak Limiter Control Register (address 15h)

7.15.1 Peak Signal Limit All Channels (LIMIT_ALL)

Default = 0 0 - individual channel 1 - all channels Function: When set to 0, the peak signal lim iter will limit the maximum signal amp litude to prevent clipping on the specific channel indicating clipping. The other channels will not be affected. When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on ALL channels in response to ANY single channel indicating clipping.

7.15.2 Peak Signal Limiter Enable (LIMIT_EN)

Default = 0 0 - Disabled 1 - Enabled Function: The CS44800 will limit the maximum si gnal amplitude to prevent clippi ng when this function is enabled. Peak Signal Limiting is performed by digital attenuat ion. The attack rate is determined by the Limiter At- tack Rate register.

7.16 Limiter Attack Rate (address 16h)

7.16.1 Attack Rate (ARATE[7:0])

Default = 00010000 Function: The limiter attack rate is user selectable. The effective rate is a function of the SRC output sampling fre- quency and the value in the Limiter Attack Rate re gister. Rates are calculated using the function RATE = (32/{value})/SRC Fs, where {value} is the decimal value in the Limiter Attack Rate register and SRC Fs is the output sample rate of the SRC which is determined by the PWM master clock frequency. SRC Fs equals 384 kHz for 24.576 MHz based clocks and 421.875 kHz for 27.000 MHz based clocks. Note: A value of zero in this register is not recommended , as it will induce erratic behavior of the limiter. Use the LIM_EN bit to disable the limiter function (see Peak Limiter Control Register (address 15h)). 76543210 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED LIMIT_ALL LIMIT_EN 76543210 ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0

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7.17 Limiter Release Ra te (address 17h)

7.17.1 Release Rate (RRATE[7:0])

Fs equals 384 kHz for 24.576 MHz based clocks and 421.875 kHz for 27.000 MHz based clocks. Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. Use the LIM_EN bit to disable the limiter function (see Peak Limiter Control Register (address 15h)).

7.18 Chnl XX Load Compensatio n Filter - Coarse Adjust

7.18.1 Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0])

justment bits will attenuate the audio response curve according to the table below in 0.1 dB increments. Filter setting values less than -4.0 dB will cause the PWM output to mute. Table 10. Limiter Attack Rate Settings Table 11. Limiter Release Rate Settings

7.19 Chnl XX Load Compensati on Filter - Fine Adjust

7.19.1 Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0])

0.1 dB increments. Filter setting values less than -4.0 dB will cause the PWM output to mute.

7.20 Interrupt Mode Control (address 28h)

7.20.1 Interrupt Pin Control (INT1/INT0)

10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. Table 12. Channel Load Compensation Filter Coarse Adjust Table 13. Channel Load Compensation Filter Fine Adjust

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7.20.2 Overflow Level/E dge Select (OVFL_L/E)

Default = 0 Function: This bit defines the OVFL interrupt type (0 = level sensitive, 1 = edge trigger). The Over Flow status of all the audio channels when configured as “edge trigger” is cleared by reading the Channel Over Flow Status (address 2Bh) (Read Only), and by reset. After a Reset this bit defaults to 0b, specifying “level sensitive”.

7.21 Interrupt Mask (address 29h)

Default = 00000000 Function: The bits of this register serve as a mask for the inte rrupt sources found in the Interrupt Status register. If a mask bit is set to 1b, the interrupt is unmasked, meaning that its occurrence will affect the INT pin and the Interrupt Status register. If a mask bit is set to 0b, the condition is masked, meaning that its occurrence will not affect the INT pin. The bit positions align with the corresponding bits in the Interrupt Status register. The mask bits for the GPIO_INT interrupt are located in the GPIO Interrupt Mask Register.

7.22 Interrupt Status (address 2Ah) (Read Only)

For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets the SRC_UNLOCK, SRC_LOCK, RMPUP_DONE, RMPDN_DONE and MUTE_DONE bits to 0. These bits are considered “edge-trigger” interrupts. The OVFL_INT and GPIO_INT bits will not reset to 0 by reading this register. The OVFL_INT bit will be set to 0 by a read to the “Channel Over Flow Status (address 2Bh) (Read Only)” on page 66 only when the in- terrupt type is set to “edge-trigger”. The GPIO_INT bit will be set to 0 by a read to the “GPIO Status Register (address 2Fh)” on page 67 only when the interrupt type is set to “edge trigger”. If either of these interrupt types are configured as “level sensitive”, then reading the appropriate status register will not clear the cor- responding status bit in this register. OVFL_INT or GPIO_INT will remain set as long as the logic active level is present. Once the level is cleared, then a read to the proper status register will clear the status bit.

7.22.1 SRC Unlock Inte rrupt (SRC_UNLOCK)

Default = 0 Function: When high, indicates that the DAI interface has detected an error condition and/or the SRC has lost lock. Conditions which cause the SRC to loose lock, such as loss of DAI_LRCK, DAI_MCLK or a DAI_LRCK/ DAI_MCLK ratio change, will cause an interrupt condition. This interrupt is an edge-triggered event. If this bit is set to a 1b, indicating an unlock condition, and an SRC_LOCK interrupt is detected, then this bit will be reset to 0b before a read of the Interrupt Status Register. On ly the last valid state of the SRC will be reported. 765 4 3 2 1 0 M_SRC_UNLOCK M_SRC_LOCK M_RMPUP_DONE M_RMPD N_DONE M_MUTE_DONE M_OVFL_INT RESERVED RESERVED 7 6 5 4 32 10 SRC_UNLOCK SRC_LOCK RMPUP_DONE RMPDN_DO NE MUTE_DONE OVFL_INT GPIO_INT RESERVED

7.22.2 SRC Lock Interrupt (SRC_LOCK)

Default = 0 Function: When high, indicates that on all ac tive channels, the sample rate co nverters have achieved lock. This interrupt is an edge-triggered event. If this bit is set to a 1b, indicating a lock condition, and an SRC_UNLOCK condition is detected, then this bit will be reset to 0b before a read of the Interrupt Status Register. On ly the last valid state of the SRC will be reported.

7.22.3 Ramp-Up Complete Interrupt (RMPUP_DONE)

Default = 0 Function: When high, indicates that all active channels have completed the configured ramp-up interval.

7.22.4 Ramp-Down Complete Interrupt (RMPDN_DONE)

Default = 0 Function: When high, indicates that all active channels have completed the configured ramp-down interval.

7.22.5 Mute Complete Interrupt (Mute_DONE)

Default = 0 Function: When high, indicates that all muted channels have completed the mute cycle-down interval as defined by the SZC[1:0] bits in the “Volume Control Configuration (address 06h)” on page 55.

7.22.6 Channel Over Flow Interrupt (OVFL_INT)

Default = 0 Function: When high, indicates that the magnitude of an output sample on one of the channels has exceeded full scale and has been clipped to positive or negative full scale as appropriate. This bit is the logical OR of all the bits in the Channel Over Flow Status Register. Read the Channel Over Fl ow Status Register to determine which channel(s) had the overflow condition.

7.22.7 GPIO Interrupt Condi tion (GPIO_INT)

Default = 0 Function: When high, indicates that a transition as configured on one of the un-masked GPIO pins has occurred. This bit is the logical OR of all the supported un-masked bits in the GPIO Status Register. Read the GPIO Status Register to determine which GPIO input(s) caused the interrupt condition. The GPIO interrupt is not removed by reading this register. The GPIO Status Register must be read to clear this interrupt. If the GPIO input is configured as “edge trigger” the interrupt will clear. If the GPIO input is configured as “level sensitive”, the interrupt condition will remain as long as the GPIO input remains at the active level.

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7.23 Channel Over Flow Stat us (address 2Bh) (Read Only)

For all bits in this register, a ‘1’ means the associated condition has occurred at least once since the register was last read. A ‘0’ means the associated condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0 if the Over flow Level/Edge interrupt type is set to “edge trigger”. These channel overflow status bits are not effected by the interrupt mask bit, M_OVFL_INT. The overflow condition of each channel can be polled instead of generating an interrupt as required.

7.23.1 ChXX_OVFL

Default = 0 Function: When high, indicates that the magnitude of the current output sample on the associated channel has ex- ceeded full scale and has been clipped to positive or negative full scale as appropriate.

7.24 GPIO Pin In/Out (address 2Ch)

7.24.1 GPIO In/Out Sel ection (GPIOX_I/O)

Default = 0 0 - General Purpose Input 1 - General Purpose Output Function: General Purpose Input - The pin is configured as an input. General Purpose Output - The pin is configured as a general purpose output.

7.25 GPIO Pin Polari ty/Type (address 2Dh)

7.25.1 GPIO Polarity/Type Selection (GPIOX_P/T)

Default = 1 Function: General Purpose Input - If the pin is configured as an input, this bit defines the input polarity (0 = Active Low, 1 = Active High). General Purpose Output - If the pin is configured as a genera l purpose output, this bit defines the GPIO output type (0 = CMOS, 1 = OPEN-DRAIN). 76543210 CHB4_OVFL CHA4_OVFL CHB3_OVFL CHA3_OVFL C HB2_OVFL CHA2_OVFL CHB1_OVFL CHA1_OVFL 76543210 RESERVED GPIO6_I/O GPIO5_I/O GPIO4_I/O GPIO3_I/O GPIO2_I/O GPIO1_I/O GPIO0_I/O 76543210 RESERVED GPIO6_P/T GPIO5_P/T GPIO4_P/T GPIO3_P/T GPIO2_P/T GPIO1_P/T GPIO0_P/T

7.26 GPIO Pin Level/Edge Trigger (address 2Eh)

7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E)

Default = 0 Function: General Purpose Input - This bit defines the GPIO input type (0 = level sensitive, 1 = edge trigger) when a GPIO pin is configured as an input. The GPIO pin st atus of an input configured as “edge trigger” is cleared by reading the GPIO Status Register when not enabled to generate an interrupt (MASK bit equals 0b) and by reset. After a reset this bit defaults to 0b, specifying “level sensitive”. General Purpose Output - Not Used.

7.27 GPIO Status Register (address 2Fh)

7.27.1 GPIO Pin Status (GPIOX_STATUS)

Default = x Function: General Purpose Input - Bits in this register are read only when the corresponding GPIO pin is configured as an input. Each bit indicates the status of the GP IO pin. The corresponding bit of a GPIO input config- ured as “edge trigger” is cleared by reading the GPIO Status Register. GPIO inputs configured as “level sensitive” will not be automatically cleared, but will reflect the logic state on the GPIO input. The mask bits in the GPIO Interrupt Mask Register have no effect on the operation of these status bits. When a GPIO is un-masked and enabled to generate an interrupt, and is configured as “edge trigger”, a read operation to this register will clear the status bit and remove the interrupt condition. A read operation to the Interrupt Status (address 2Ah) (read only) when a GPIO is configured to generate an interrupt con- dition will not clear any bits in this register. General Purpose Output - For GPIO pins configured as outputs, these bits are used to control the output signal level. A 1b written to a particular bit will c ause the corresponding GPIO pin to be driven to a logic high. A 0b will cause a logic low. 76543210 RESERVED GPIO6_L/E GPIO5_L/E GPIO4_L/E GPIO3_L/E GPIO2_L/E GPIO1_L/E GPIO0_L/E 76 543210 RESERVED GPIO6_STATUS GPIO5_STATUS GPIO4_STATUS GPIO 3_STATUS GPIO2_STATUS GPIO1_STATUS GPIO0_STATUS

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7.28 GPIO Interrupt Mask Register (address 30h)

7.28.1 GPIO Pin Interr upt Mask (M_GPIOX)

Default = 0 Function: General Purpose Input - The bits of this register serve as a mask for GPIO[3:0] interrupt sources. If a mask bit is set to 1, the interrupt is unmasked, meaning that its occurrence will affect the INT pin and the Inter- rupt Status register. If a mask bit is set to 0, the condition is masked, meaning that its occurrence will not affect the INT pin or Interrupt Stat us Register. The proper pin status will be reported in the GPIO Status Register. The bit positions align with the corresponding bits in the GPIO Status register. General Purpose Output - This register is not used.

7.29 PWM Configuration Re gister (address 31h)

7.29.1 Over Sample Rate Selection (OSRATE)

Default = 0 0 - modulated PWM output pulses run at single-mode switch rate. Typically 384 kHz or 421.875 kHz. 1 - modulated PWM output pulses run at double-mode switch rate. Typically 768 kHz or 843.75 kHz. Function: Enables the interpolation filter in the modulator to over-sample the incoming audio to support a double- speed PWM switch rate. This parameter can only be changed when all modulators and associated logic are in the power-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.

7.29.2 Channels A1 and B1 Output Configuration (A1/B1_OUT_CNFG)

Default = 0 0 - pwm outputs for both channels A1 and B1 are configured for half-bridge operation 1 - pwm outputs for both channels A1 and B1 are configured for full-bridge operation Function: Identifies the output configuration. The value selected for this bit is applicable to the outputs for channels A1 and B1. This parameter can only be changed when all modulators and associated logic are in the pow- er-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.

7.29.3 Channels A2 and B2 Output Configuration (A2/B2_OUT_CNFG)

Default = 0 0 - pwm outputs for both channels A2 and B2 are configured for half-bridge operation 1 - pwm outputs for both channels A2 and B2 are configured for full-bridge operation Function: Identifies the output configuration. The value selected for this bit is applicable to the outputs for channels A2 and B2. This parameter can only be changed when all modulators and associated logic are in the pow- 76543210 RESERVED RESERVED RESERVED RESERVED M_GPIO3 M_GPIO2 M_GPIO1 M_GPIO0 76 5 4 3 2 1 0 OSRATE RESERVED RESERVED A1/B1_OUT_CNFG A2/B2_OUT _CNFG A3_OUT_CNFG B3_OUT _CNFG A4/B4_OUT_CNFG

er-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.

7.29.4 Channel A3 Output Configuration (A3_OUT_CNFG)

Default = 0 0 - pwm outputs for channel A3 are configured for half-bridge operation 1 - pwm outputs for channel A3 are configured for full-bridge operation Function: Identifies the output configuration. The value selected for this bit is applicable to the outputs for only chan- nel A3. This parameter can only be changed when all modulators and associated logic are in the power down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)” on page 51 to a ‘1’b. Attempts to write this register while the PDN is not set will be ignored.

7.29.5 Channel B3 Output Configuration (B3_OUT_CNFG)

Default = 0 0 - pwm outputs for channel B3 are configured for half-bridge operation 1 - pwm outputs for channel B3 are configured for full-bridge operation Function: Identifies the output configuration. The value selected for this bit is applicable to the outputs for only chan- nel B3. This parameter can only be changed when all modulators and associated logic are in the power- down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.

7.29.6 Channels A4 and B4 Output Configuration (A4/B4_OUT_CNFG)

Default = 0 0 - pwm outputs for both channels A4 and B4 are configured for half-bridge operation 1 - pwm outputs for both channels A4 and B4 are configured for full-bridge operation Function: Identifies the output configuration. The value selected for this bit is applicable to the outputs for chan- nels A4 and B4. This parameter can only be changed when all modulators and associated logic are in the power down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)” on page 51 to a ‘1’b. Attempts to write this register while the PDN is not set will be ignored.

7.30 PWM Minimum Pulse Widt h Register (address 32h)

7.30.1 Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-)

Default = 0 0 - PWM minus (“-”) differential signal is operational when PWM channel is configured for half-bridge. 1 - PWM minus (“-”) differential signal is disabled when PWM channel is configured for half-bridge. Function: Determines if the PWM minus (“-”) differential signal is disabled when the particular PWM channel is con- figured for half-bridge operation. This bit is ignored for channels configured for full-bridge operation. The value selected for this bit is applicable to the outputs for all channels configured for half-bridge operation. This parameter can only be changed when all modulators and associated logic are in the power-down 76 5 4 3 2 1 0 DISABLE_PWMOUTXX- RESERVED RESERVED MIN_PULSE4 MIN_PULSE3 MIN_PULSE2 MIN_PULSE1 MIN_PULSE0

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page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.

7.30.2 Minimum PWM Output Pul se Settings (MIN_PULSE[4:0])

7.31 PWMOUT Delay Regi ster (address 33h)

7.31.1 Differential Signal Delay (DIFF_DLY[2:0])

02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.

7.31.2 Channel Delay Sett ings (CHNL_DLY[4:0])

Table 14. PWM Minimum Pulse Width Settings Table 15. Differential Signal Delay Settings

PDN is not set will be ignored. Table 16. Channel Delay Settings

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Figure 31. PWM Output Delay

7.32 PSR and Power Supply C onfiguration (address 34h)

7.32.1 Power Supply Rejection Enable (PSR_EN)

Default = 0 0 - disable 1 - enable Function: Enables the on-card and internal power supply rejection circuitry. This bit will cause the PSR_EN output signal to change logic level. A ‘0’b in this bit will cause the PSR_EN to drive a logic low. A ‘1’b will drive a logic high. 76 5 4 3 2 1 0 PSR_EN PSR_RESET FEEDBACK_EN RESERVED RESERVED PS_SYNC_DIV2 PS_SYNC_DIV1 PS_SYNC_DIV0

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7.32.2 Power Supply Reject ion Reset (PSR_RESET)

‘0’b. This bit must be set to a ‘1’b for proper PSR operation.

7.32.3 Power Supply Rejection Feedback Enable (FEEDBACK_EN)

Enables the internal power supply rejection feedback logic.

7.32.4 Power Supply Sync Clock Divi der Settings (PS_SYNC_DIV[2:0])

These three bits determine the divider for the XTAL clock signal for generating the PS_SYNC clock signal.

7.33 Decimator Shift/Scale (addresses 35h, 36h, 37h)

7.33.1 Decimator Shift (DEC_SHIFT[2:0])

(DEC_SCALE[18:0]) register description and “Recommended PSR Calibration Sequence” on page 44.

000 Output Disabled

001 Divide by 32

010 Divide by 64

011 Divide by 128

100 Divide by 256

101 Divide by 512

110 Divide by 1024

Table 17. Power Supply Sync Clock Divider Settings

7.33.2 Decimator Scale (DEC_SCALE[18:0])

(DEC_SHIFT[2:0]) register description and “Recommended PSR Calibration Sequence” on page 44.

7.34 Decimator Outd (addresses 3Bh, 3Ch, 3Dh)

7.34.1 Decimator Outd (DEC_OUTD[23:0])

These bits reflect the real-time power supply value as measured by the exte rnal PSR feedback circuit. DEC_OUTD[23:0] has 24-bit precision, formatted as signed 2.22 with decimal values from -4 to 4-2^(-22). Calibration needs to be done to correlate the value of DEC_OUTD[23:0] with the real power supply value. A quiet DC power supply without any ripple is treated as 1.0 with DEC_OUTD[23:0] calibrated at 400000h. See “Recommended PSR Calibration Sequence” on page 44. Table 18. Decimator Shift/Scale Coefficient Calculation Examples

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1. PARAMETER DEFINITIONS Dynamic Range (DR) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measurement over the spec- ified band width made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full-scale, with units in dB FS A. This technique ensures that the distortion components are below the noise level and do not effect the m easurement. This measurement technique has been ac- cepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Frequency Response (FR) FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The amplitude cor- ner, Ac, lists the maximum deviatio n in amplitude above and below the 1 kHz reference point. The listed minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequency to maxi- mum frequency inclusive. Interchannel Isolation A measure of crosstalk between the left and right ch annels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error dB FS A dB FS is defined as dB relative to full-scale. The “A” indicates an A weighting filter was used. Differential Nonlinearity The worst case deviation from the ideal code width. Units in LSB. FFT Fast Fourier Transform. Fs Sampling Frequency. Resolution The number of bits in the output words to the DACs, and in the input words to the ADCs.

Signal to Noise Ratio (SNR) SNR, similar to DR, is the ratio of an arbitrary sinuso idal input signal to the RMS sum of the noise floor, in the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB. SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The CS44800 operates at a fixed sample frequency. The internal samp le rate converter is used to convert digital audio streams playing back at other frequencies to the PWM output rate. Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms su m of all other spectral components over the specified band width (typically 10 Hz to 20 kH z), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. 9. REFERENCES 1. Cirrus Logic, “ Audio Quality Measurement Specification,” Version 1.0, 1997. http://www.cirrus.com/products/papers/meas/meas.html 2. Cirrus Logic, “ AN18: Layout and Design Rules for Data C onverters and Other Mixed Signal Devices ,” Version 6.0, February 1998. 3. Cirrus Logic, “ AN22: Overview of Digital Audio Interface Data Structures, Version 2.0”, February 1998.; A useful tutorial on digital audio specifications. 4. Philips Semiconductor, “ The I²C-Bus Specification: Version 2,” Dec. 1998. http://www.semiconductors.philips.com

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• Nominal pin pitch is 0.50 mmControlling dimension is mm.

Figure 32. 64-Pin LQFP Package Drawing

11.THERMAL CHARACTERISTICS 12.ORDERING INFORMATION 13.REVISION HISTORY Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance 2 Layer Board

4 Layer Board θJA

• °C/Watt Product Description Package Pb-Free Temp Range Container Order# CS44800 8-Channel Digital Ampli- fier Controller LQFP YES -10° to +70°C Rail CS44800-CQZ CS44800 8-Channel Digital Ampli- fier Controller LQFP YES -10° to +70°C Tape and Reel CS44800-CQZR CS44800 8-Channel Digital Ampli- fier Controller LQFP YES -40° to +85°C Rail CS44800-DQZ CS44800 8-Channel Digital Ampli- fier Controller LQFP YES -40° to +85°C Tape and Reel CS44800-DQZR CDB44800 CS44600/800 Evalua- tion Board - - - - CDB44800 CRD44800 8x50 W Half-Bridge Reference Design Board - - - - CRD44800 CRD44800-ST-FB 8x60 W Full-Bridge Reference Design Board - - - - CRD44800-ST-FB CRD44600-PH-FB 2x100 W Full-Bridge Reference Design Board - - - - CRD44600-PH-FB Release Date Changes PP1 May 2005 -Updated “Features” on page 1 -Correcte “Power Supply Current” on page 9 -Corrected “High-Level Input Voltage” on page 9 -Corrected “Low-Level Input Voltage” on page 9 -Corrected “High-Level Output Voltage at Io = -2 mA” on page 9 -Corrected “Low-Level Output Voltage at Io = 2 mA” on page 9 -Corrected “Digital Filter Response (Note 12)” on page 11 -Updated Figure 11. Typical Full-Bridge Connection Diagram on page 21 -Updated Figure 12. Typical Half-Bridge Connection Diagram on page 22 -Corrected Figure 13 on page 24 -Updated Section 7.5.2 "AM Frequency Hopping (AM_FREQ_HOP)" on page 53 -Updated “Ordering Information” on page 79 F1 March 2006 -Final Datasheet Release

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Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRI TICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN S UCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. I²C is a registered trademark of Philips Semiconductor.