CS44210 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
/c108 Up to 100 dB Dynamic Range /c108 2.4 V to 5.0 V supply /c108 Sample rates up to 96 kHz /c108 Digital Tone Control — 3 selectable HPF and LPF corner frequencies — 12 dB boost for bass and treble - 1 dB step size /c108 Programmable Digital volume control — +18 to -96 dB in 1 dB steps /c108 Peak signal soft limiting /c108 De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz /c108 Selectable outputs for each channel including — Channel A: R, L, mono (L + R) / 2, mute — Channel B: R, L, mono (L + R) / 2, mute /c108 PWM PopGuard®
Description
The CS44210 is a complete stereo digital-to-PWM Class D au- dio amplifier system controller including interpolation, volume control, half bridge PWM driver outputs, and an integrated CS44L10 headphone amplifier in a 24-pin TSSOP package. The CS44210 architecture uses a direct-to-digital approach that maintains digital signal integrity to the final output filter. This minimizes analog interference effects that can negatively affect system performance. The CS44210 contains on-chip digital bass and treble boost, peak signal limiting, and de-emphasis. The PWM amplifier can achieve greater than 90% efficiency. This efficiency leads to longer battery life for portable systems, smaller device pack- age, less heat sink requirements, and smaller power supplies. The CS44210 provides all the controls necessary to drive high- er voltage output stages for increased power levels. The CS44210 is ideal for integrated, mult-function systems such as shelf-top audio systems, audio mini systems, audio video receivers (AVR), boom boxes and powered speakers.
ORDERING INFORMATION
CS44210-KZ -10 to 70 °C 24-pin TSSOP Multibit DS Modulator with Correction Multibit DS Modulator with Correction Digital Volume Control, Bass/Treble Boost, Compression Limiting, De-emphasis Control Port SCL/CCLK/DIF0 MCLK Input MUX and Serial Port SDA/CDIN/DEM VL PWM Conversion PWM Conversion SYNC_CLK DRIVER_B HP_B VA_HPB GND_HPB Level Shifter VA_HPA Level Shifter HP_A GND_HPA RST Interpolation AD1/CDOUT TSTIN SCLK LRCK Input Sampling Rate LRCLK/MCLK Ratio AD0/CS/DIF1 SDIN1 SDIN2 SDIN3 DRIVER_A VD GND MAY ‘01 DS539PP1
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- CHARACTERISTICS AND SPECIFICATIONS (TA = 25 °C; GND = 0 V; Logic "1" = VL = 2.4 V; Logic "0" = GND = 0 V; Full-Scale Output Sine Wave, 997 Hz, MCLK = 12.288 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for Single Speed Mode = 48 kHz, SCLK = 3.072 MHz; Fs for Double Speed Mode = 96 kHz, SCLK = 6.144 MHz. Test load R L =1 6 Ω, CL = 10pF.) (See Typical CS44210 Connection Diagram.) Parameter Symbol Min Typ Max Unit Headphone Output Dynamic Performance for VD = VL = VA_HPx = 2.4 V Dynamic Range 18 to 24-Bit A-Weighted UnWeighted 16-Bit A-Weighted Unweighted TBD TBD dB dB dB dB Total Harmonic Distortion + Noise 0 dBFS -20 dBFS -60 dBFS THD+N - -62 -71 -31 TBD dB dB dB Interchannel Isolation (1 kHz) -T B D- d B Headphone Output Dynamic Performance for VD = VL = VA_HPx = 3.0 V Dynamic Range 18 to 24-Bit A-Weighted UnWeighted 16-Bit A-Weighted Unweighted TBD TBD dB dB dB dB Total Harmonic Distortion + Noise 0 dB -20 dB -60 dB THD+N - -64 -72 -32 TBD dB dB dB Interchannel Isolation (1 kHz) -T B D- d B Headphone Output Dynamic Performance for VD = VL = VA_HPx = 5.0 V Dynamic Range 18 to 24-Bit A-Weighted UnWeighted 16-Bit A-Weighted Unweighted TBD TBD dB dB dB dB Total Harmonic Distortion + Noise 0 dB -20 dB -60 dB THD+N - -67 -76 -36 TBD dB dB dB Interchannel Isolation (1 kHz) -T B D- d B
CHARACTERISTICS AND SPECIFICATIONS (Continued) Note: 1. Filter response is not tested but is guaranteed by design. 2. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 11-18) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 3. Referenced to a 1 kHz, full-scale sine wave. 4. For Single Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 5. De-emphasis is not available in double speed mode. Parameters Symbol Min Typ Max Units PWM Headphone Output Full Scale Headphone Output Voltage TBD 0.85 x VA_HP TBD Vp Headphone Output Quiescent Voltage -0 . 5 x V A _ H P- V D C Interchannel Gain Mismatch -0 . 1- d B Modulation Index -- 8 5 % Maximum Headphone Output VA_HPx=2.4V AC-Current VA_HPx=5.0V IHP - mA mA Parameter Single Speed Mode Double Speed Mode Symbol Min Typ Max Min Typ Max Unit Digital Filter Response (Note 1) Passband to -0.05 dB corner (Note 2) to -0.1 dB corner to -3 dB corner .4535 .4998 .4426 .4984 Fs Fs Fs Frequency Response 10 Hz to 20 kHz (Note 3) StopBand .5465 - - .577 - - Fs StopBand Attenuation (Note 4) 50 - - 55 - - dB Group Delay tgd - 9/Fs - - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz ±0.36/Fs ±1.39/Fs ±0.23/Fs s s De-emphasis Error Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz +.2/-.1 +.05/-.14 +0/-.22 (Note 5) dB dB dB
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ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.) CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.) SWITCHING CHARACTERISTICS (TA = -10 to 70°C; VL = 2.4V - 5.0V; Inputs: Logic 0 = GND, Logic 1 = VL, CL = 20pF) Parameters Symbol Min Max Units DC Power Supplies: Headphone Interface Digital VA_HPx VL VD 2.4 2.4 2.4 5.5 5.5 5.5 V V V Input Current, Any Pin Except Supplies Iin ±10 mA Digital Input Voltage VIND -0.3 VL + 0.4 V Ambient Operating T emperature (power applied) TA -55 125 °C Storage Temperature Tstg -65 150 °C Parameters Symbol Min Typ Max Units Ambient Temperature TA -10 - 70 °C DC Power Supplies: Headphone Interface Digital VA_HPx VL VD 2.4 2.4 2.4 5.0 5.0 5.0 V V V Parameters Symbol Min Typ Max Units Input Sample Rate Single Speed Mode Double Speed Mode Fs Fs 100 kHz kHz MCLK Duty Cycle 40 50 60 % LRCK Duty Cycle 40 50 60 % SCLK Pulse Width Low tsclkl 20 - - ns SCLK Pulse Width High tsclkh 20 - - ns SCLK Period Single Speed Mode tsclkw --n s Double Speed Mode tsclkw --n s SCLK rising to LRCK edge delay tslrd 20 - - ns SCLK rising to LRCK edge setup time tslrs 20 - - ns SDIN valid to SCLK rising setup time tsdlrs 20 - - ns SCLK rising to SDIN hold time tsdh 20 - - ns
- Power Down Mode is defined as RST = LO with all clocks and data lines held static.
Figure 1. Serial Audio Data Interface Timing
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DIGITAL CHARACTERISTICS (TA = 25° C ; V L = 2 . 4V - 3 . 6V ; G N D=0V ) SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT (Note 8) (TA =2 5° C; VL = 2.4 V - 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VL, C L =3 0p F ) Note: 7. V OH and VOL are tested at an output current of TBD mA. 8. The Two-Wire Format is compatible with the I 2C protocol. 9. Data must be held for sufficient time to bridge the transition time, t fc, of SCL. 10. The acknowledge delay is based on MCLK and can limit the maximum transaction speed. 11. for Single-Speed Mode and for Double-Speed Mode. Parameters Symbol Min Typ Max Units High-Level Input Voltage VIH 0.7 x VL - - V Low-Level Input Voltage VIL -- 0 . 3 x V L V Input Leakage Current Iin -- ± 1 0 µA Input Capacitance -8- p F High-Level Output Voltage (Pin 15) (Note 7) VOH 0.7 x VL - - V Low-Level Output Voltage (Pin 15) (Note 7) VOL -- 0 . 3 x V L V High-Level Output Voltage (Pins 11, 13, 14) (Note 7) VOH 0.7 x VD - - V Low-Level Output Voltage (Pins 11, 13, 14) (Note 7) VOL - - 0.3 x VD V Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.7 - µs SDA Hold Time from SCL Falling (Note 9) thdd 0- µ s SDA Setup time to SCL Rising tsud 250 - ns Rise Time of SCL and SDA trc, trc -1 µ s Fall Time SCL and SDA tfc, tfc - 300 ns Setup Time for Stop Condition tsusp 4.7 - µs Acknowledge Delay from SCL Falling (Note 10) tack - (Note 11) ns
Figure 2. Control Port Timing - Two-Wire Format
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- t spi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
- Data must be held for sufficient time to bridge the transition time of CCLK.
- CDOUT should not be sampled during this time period.
- This time is not tested but is guaranteed by design.
Figure 3. Control Port Timing - SPI Format
- TYPICAL CONNECTION DIAGRAMS
- This feature is unavailable in this mode.
This pin should be grounded. Figure 4. Typical CS44210 Connection Diagram Stand-Alone Mode
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Figure 5. Typical CS44210 Connection Diagram Control Port Mode
Table 1. Register Quick Reference
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- REGISTER DESCRIPTIONS
4.1 Power and Muting Control (address 02h)
4.1.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC)
Default = 10 00 - Immediate Change 01 - Zero Cross Control 10 - Ramped Control 11 - Reserved Function: Immediate Change When Immediate Change is selected, all level changes will take effect immediately in one step. Zero Cross Control Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-out period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Ramped Control Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Note: Ramped Control is not available in Double Speed Mode.
4.1.2 POWER DOWN (PDN)
Default = 1 0 - Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation in Control Port mode can occur. 76543210 SZC1 SZC0 PDN FLT RUPBYP RDNBYP Reserved Reserved 10100000
4.1.3 FLOAT OUTPUT (FLT)
Default = 0 0 - Disabled 1 - Enabled Function: When enabled, this bit will cause the headphone output of the CS44210 to float when in the power down state (PDN=1). The float function can be used in single-ended applications to maintain the charge on the DC-blocking capacitor during power transients. On power transitions, the output will quickly change to the bias point, however, if the DC-blocking capacitor still has a full charge, as in short power cycles, the tran- sition will be very small, often inaudible. Refer to Section 6.4 .
4.1.4 RAMP UP BYPASS (RUPBYP)
Default = 0 0 - Normal 1 - Bypass Function: When in normal mode, the duty cycle of the output PWM signal is increased at a rate determined by the Ramp Speed variable (RMP_SPx). Normal mode is used in Single Ended applications to reduce pops in the output caused by the DC-blocking capacitor. When the ramp up function is bypassed in Single Ended applications, there will be an abrupt change in the output signal. Refer to Section 6.4.
4.1.5 RAMP DOWN BYPASS (RDNBYP)
Default = 0 0 - Disabled 1 - Enabled Function: When in normal mode, the duty cycle of the output PWM signal is decreased at a rate determined by the Ramp Speed variable (RMP_SPx). Normal mode is used in Single Ended applications to reduce pops in the output caused by the DC-blocking capacitor and changes in bias conditions. When the ramp down function is bypassed in Single Ended applications, there will be an abrupt change in the output signal. Re- fer to Section 6.4.
4.2 Channel A Volume Control (address 03h) (VOLA)
4.3 Channel B Volume Control (address 04h) (VOLB)
Default = 0 dB (No attenuation) Function: The Volume Control registers allow independent control of the signal levels in 1 dB increments from +18 to -96 dB. Volume settings are decoded using a 2 ’s complement code, as shown in Table 2. The volume changes are implemented as dictated by the Soft and Zero Cross bits. All volume settings less than -96 dB are equivalent to muting the channel via the ATAPI bits (see Section 4.8.3). 76543210 VOLx7 VOLx6 VOLx5 VOLx4 VOLx3 VOLx2 VOLx1 VOLx0 00000000
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Note: All volume settings greater than +18 dB are interpreted as +18 dB.
4.4 Tone Control (address 05h)
4.4.1 BASS BOOST LEVEL (BB)
+12 dB are interpreted as +12 dB.
4.4.2 TREBLE BOOST LEVEL (TB)
+12 dB are interpreted as +12 dB. Note: Treble Boost is not available in Double Speed Mode. Table 2. Example Volume Settings Table 3. Example Bass Boost Settings Table 4. Example Treble Boost Settings
4.5 Mode Control 1 (address 06h)
4.5.1 BASS BOOST CORNER FREQUENCY (BBCF)
pling frequency), the DBS bit and the BBCF bits as shown in Table 5 and Table 6.
4.5.2 TREBLE BOOST CORNER FREQUENCY (TBCF)
pling frequency) and the TBCF bits as shown in Table 7. Note: Treble Boost is not available in Double Speed Mode.
11 Reserved Reserved Reserved Reserved
Table 5. Base Boost Corner Frequencies in Single Speed Mode Table 6. Base Boost Corner Frequencies in Double Speed Mode
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4.5.3 TONE CONTROL MODE (TC)
The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured. are a function of LRCK - refer to tables 5, 6, and 7). Note: Treble boost is not available in Double Speed Mode.
4.5.4 TONE CONTROL ENABLE (TC_EN)
The Bass Boost and Treble Boost features are active when this function is enabled.
4.5.5 PEAK SIGNAL LIMITER ENABLE (LIM_EN)
The CS44210 will limit the maximum signal amplitude to prevent clipping when this function is enabled. is determined by the Limiter Release Rate register. Note: The A=B bit should be set to ‘1’ for optimal limiter performance. Table 7. Treble Boost Corner Frequencies in Single Speed Mode
4.6 Limiter Attack Rate (address 07h) (ARATE)
ue} is the decimal value in the Limiter Attack Rate register and RATE is in LRCK ’s per 1/8 dB of change. Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. Use the LIM_EN bit to disable the limiter function (see "Peak Signal Limiter Enable (LIM_EN)" ).
4.7 Limiter Release Rate (address 08h) (RRATE)
Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. Use the LIM_EN bit to disable the limiter function (see "Peak Signal Limiter Enable (LIM_EN)" ). Table 8. Example Limiter Attack Rate Settings Table 9. Example Limiter Release Rate Settings
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4.8 Volume and Mixing Control (address 09h)
4.8.1 INPUT MUX SELECTION (IS)
Default = 00 00 - Selects SDIN1 as input 01 - Selects SDIN2 as input 10 - Selects SDIN3 as input 11 - Reserved Function: The Input Mux Selector determines which SDIN input is selected.
4.8.2 RAMP SPEED (RMP_SP)
Default = 01 00 - Ramp speed = approximately 0.1 seconds 01 - Ramp speed = approximately 0.2 seconds 10 - Ramp speed = approximately 0.3 seconds 11 - Ramp speed = approximately 0.65 seconds Function: This feature is used in Single Ended applications to reduce pops in the output caused by the DC-blocking capacitor. When in control port mode, the Ramp Speed sets the time for the PWM signal to linearly ramp up and down from the bias point (50% PWM duty cycle). Refer to Section 6.4.
4.8.3 ATAPI CHANNEL MIXING AND MUTING (ATAPI)
Default = 1001 - HP_A = L, HP_B = R (Stereo) Function: The CS44210 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 10 and Figure 6 for additional information. Note: All mixing functions occur prior to the digital volume control. 76543210 IS1 IS0 RMP_SP1 RMP_SP0 ATAPI3 ATAPI2 ATAPI1 ATAPI0 00001001
0000 M U T E M U T E
0001 M U T E R
0010 M U T E L
0011 M U T E [ ( L + R ) / 2 ]
0100 R M U T E
0101 R R
0110 R L
0111 R [ ( L + R ) / 2 ]
1000 L M U T E
1001 L R
1010 L L
1011 L [ ( L + R ) / 2 ]
Table 10. ATAPI Decode Figure 6. Dynamics Control Block Diagram
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4.9 Mode Control 2 (address 0Ah)
4.9.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)
Default = 0 Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user ’s MCLK and LRCK require- ments. Refer to Tables 11, 12, 13, 14, and Section 6.2.
4.9.2 CLOCK DIVIDE (CLKDIV)
Default = 00 Function: MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user ’s MCLK and LRCK requirements. Refer to Tables 11, 12, 13, 14, and Section 6.2.
4.9.3 DOUBLE SPEED MODE (DBS)
Default = 0 0 - Single Speed 1 - Double Speed (DBS) Function: Single Speed supports 8kHz to 50 kHz sample rates and Double Speed supports 50 kHz to 96kHz sample rates. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to Tables 11, 12, 13, 14, and Section 6.2. Note: De-emphasis, ramp control, and treble control are not available in Double Speed Mode.
4.9.4 FREQUENCY SHIFT (FRQSFT)
Default = 00 Function: MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user ’s MCLK and LRCK requirements. Refer to Tables 11, 12, 13, 14, and Section 6.2. 76543210 MCLKDIV CLKDV1 CLKDV0 DBS FRQSFT1 FRQSFT0 DEM1 DEM0 00000000
Table 11. Single Speed Clock Modes - Control Port Mode Table 12. Single Speed Clock Modes - Stand-Alone Mode
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4.9.5 DE-EMPHASIS CONTROL (DEM)
sponse at 32, 44.1 or 48 kHz sample rates (see Figure 7). Note: De-emphasis is not available in double speed mode . Table 13. Double Speed Clock Modes - Control Port Mode Table 14. Double Speed Clock Modes - Stand-Alone Mode Figure 7. De-Emphasis Curve
4.10 Mode Control 3 (address 0Bh)
4.10.1 DIGITAL INTERFACE FORMATS (DIF)
Default = 00 00 - I2S 01 - Right Justified, 16 bit 10 - Left Justified 11 - Right Justified, 24 bit Function: The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in figures 19 through 22.
4.10.2 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)
Default = 0 0 - Disabled 1 - Enabled Function: The HP_A and HP_B volume levels and the DRIVER_x outputs are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both HP_A, HP_B, DRIVER_A and DRIVER_B are determined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled.
4.10.3 VOLUME CONTROL BYPASS (VCBYP)
Default = 0 0 - Disabled 1 - Enabled Function: The digital volume control section is bypassed when this function is enabled. This disables the digital vol- ume control, muting, bass boost, treble boost, limiting, and ATAPI functions.
4.10.4 CONTROL PORT ENABLE (CP_EN)
Default = 0 0 - Disabled 1 - Enabled Function: This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg- isters and the pin definitions will conform to Control Port Mode. Refer to Section 7.1 76543210 DIF1 DIF0 A=B VCBYP CP_EN FREEZE HPSEN Reserved 00000000
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4.10.5 FREEZE (FREEZE)
Default = 0 0 - Disabled 1 - Enabled Function: This function allows modifications to be made to the registers without the changes being taking effect until the FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneous- ly, you will first enable the FREEZE Bit, then make all register changes, then Disable the FREEZE bit.
4.11 Revision Indicator (address 0Ch)[Read Only]
Default = none etc. Function: This read-only register indicates the revision level of the device. 76543210 Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0 00000000
- PIN DESCRIPTION 12 13 Serial Data 2 SDIN2 SDIN3 Serial Data 3 Serial Data 1 SDIN1 RST Reset Left/Right Clock LRCK GND Headphone B Ground Serial Clock SCLK HP_B Headphone B Output Master Clock MCLK VA_HPB Headphone B Power Digital Power VD VA_HPA Headphone A Power Ground GND HP_A Headphone A Output Interface Power VL GND Headphone A Ground SCL/CCLK/DIF0 SCL/CCLK/DIF0 SDA/CDIN/DEM SDA/CDIN/DEM Addr0/ChipSel/DIF1 AD0/CS/DIF1 AD1/CDOUT Addr1/CDOUT Sync Clock SYNC_CLK DRIVER_A Driver Output A Test In TSTIN DRIVER_B DriverOutput B SDIN1 SDIN2 SDIN3 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Unused inputs should be grounded. LRCK 3 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs. SCLK 4 Serial Clock (Input) - Serial clock for the serial audio interface. MCLK 5 Master Clock (Input) - Clock source for the PWM modulator and digital filters. Table 11, 12, 13 and 14 illustrate several standard audio sample rates and the required master clock frequen- cies. VD 6 Digital Power (Input) - Positive power supply for the digital section. Refer to "Recommended Operating Conditions" for appropriate voltages. GND 7, 17 & 22 Ground (Input) - Ground Reference. VL 8 Logic Power (Input) - Determines the required signal level for the digital input/output. Refer to "Recommended Operating Conditions" for appropriate voltages. Sync Clock 11 SYNC_CLK (Output) - Provides a high frequency clock signal at 32 x PWM switching frequency to synchronize external circuitry, if needed. TSTIN 12 Test In (Input) - This pin is not used and must remaing floating. DRIVER_A DRIVER_B DRIVER OUTPUTS(Outputs) Outputs used to drive external power devices. HP_A HP_B Headphone Outputs (Output) - PWM Headphone Outputs. An external LC filter should be added to suppress high frequency switching noise. A DC blocking capacitor is also required. Refer to Typical Connection Diagrams. VA_HPA VA_HPB Headphone Amplifier Power (Input) - Positive power supply for the headphone amplifier. Refer to "Recommended Operating Conditions" for appropriate voltages. RST
23 Reset (Input) - The device enters a low power mode and all internal registers are reset to their
default settings when low. The control port cannot be accessed when Reset is low. See Sec- tion 6.5 Control Port Definitions SCL/CCLK 9 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up resistor to VL in Two-Wire mode.
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Two-Wire mode; CS is used to enable the control port interface. AD1/CDOUT 15 Non-applicable (input) - non-functional in this mode should be connected to ground. Speed Modes. When DEM is grounded, de-emphasis is disabled. Table 15. Digital Interface Format - DIF1 and DIF0
- APPLICATIONS
6.1 Grounding and Power Supply Decoupling
As with any switching converter, the CS44210 re- quires careful attention to power supply and grounding arrangements to optimize performance. Figures 4 and 5 show the recommended power ar- rangement with VD, VA_HPx, and VL connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be used on each supply pin.
6.2 Clock Modes
One of the characteristics of a PWM amplifier is that the frequency content of out-of-band noise generated by the modulator is dependent on the PWM switching frequency. The systems designer will specify the external filter based on this switch- ing frequency. The obvious implementation in a digital PWM system is to directly lock the PWM switching rate to the incoming data sample rate. However, this would require a tuneable filter to at- tentuate the switching frequency across the range of possible sample rates. To simplify the external filter design and to accommodate sample rates ranging from 8 kHz to 96 kHz the CS44210 Con- troller uses several clock modes that keep the PWM switching frequency in a small range. In control port mode, for operation at a particular sample rate the user selects register settings (refer to Section 4.9 and Tables 11 and 13) based on their MCLK and MCLK/LRCK parameters. When us- ing Stand-Alone mode, refer to Tables 12 and 14 for available clock modes.
6.3 De-Emphasis
The CS44210 includes on-chip digital de-empha- sis. Figure 7 shows the de-emphasis curve. The fre- quency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. The de-emphasis feature is included to accommo- date older audio recordings that utilize pre-empha- sis equalization as a means of noise reduction.
6.4 PWM PopGuard Transient Control
The CS44210 uses PopGuard® technology to mini- mize the effects of output transients during pow- er-up and power-down. This technique minimizes the audio transients commonly produced by sin- gle-ended, single-supply converters when it is im- plemented with external DC-blocking capacitors connected in series with the audio outputs. When the device is initially powered-up, the DRIVER_x, and HP_x outputs are clamped to GND. Following a delay each output begins to in- crease the PWM duty cycle toward the quiescent voltage point. By a speed set by the RMP_SP bit, the DRIVER_x and HP_x outputs will later reach the bias point (50% PWM duty cycle), and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up transient. To prevent transients at power-down, the device must first enter its power-down state. When this oc- curs, audio output ceases and the PWM duty cycle is decreased until the DRIVER_x and HP_x out- puts reach GND. The time required to reach GND is determined by the RMP_SP bits. This allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on. To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning off the power or exiting the pow- er-down state. If full discharge does not occur, a transient will occur when the audio outputs are ini- tially clamped to GND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 220 µF capacitor
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and a 16 ohm load on the headphone outputs, the minimum power-down time will be approximately 0.4 seconds. Note that ramp up and ramp down period can be set to zero with the RUPBYP and RDNBYP bits re- spectively.
6.5 Recommended Power-up Sequence
6.5.1 Stand Alone Mode
- Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control port is reset to its default settings and the HP_x and DRIVER_x lines will remain low. 2. Bring RST high. The device will remain in a low power state and will initiate the Stand-Alone pow- er-up sequence. The control port will be accessible at this time.
6.5.2 Control Port Mode
- Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control port is reset to its default settings and the HP_x and DRIVER_x lines will remain low. 2. Bring RST high. The device will remain in a low power state and will initiate the Stand-Alone pow- er-up sequence. The control port will be accessible at this time. 3. On the CS44210 the control port pins are shared with stand-alone configuration pins. To enable the control port, the user must set the CP_EN bit. This is done by performing a Two-Wire or SPI write. Once the control port is enabled, these pins are ded- icated to control port functionality. To prevent audible artifacts the CP_EN bit (see Section 4.10.4) should be set prior to the comple- tion of the Stand-Alone power-up sequence, ap- proximately 21mS. Writing this bit will halt the Stand-Alone power-up sequence and initialize the control port to its default settings. Note, the CP_EN bit can be set any time after RST goes high; how- ever, setting this bit after the Stand-Alone pow- er-up sequence has completed can cause audible artifacts.
- CONTROL PORT INTERFACE The control port is used to load all the internal set- tings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference prob- lems, the control port pins should remain static if no operation is required. The CS44210 has MAP auto increment capability, enabled by the INCR bit in the MAP register, which is the MSB. If INCR is 0, then the MAP will stay constant for successive writes. If INCR is set to 1, then MAP will auto increment after each byte is written, allowing block reads or writes of succes- sive registers.
7.1 Format Selection
The control port has 2 formats: SPI and Two-Wire, with the CS44210 operating as a slave device. If Two-Wire operation is desired, AD0/CS should be tied to VL or GND. If the CS44210 ever detects a high to low transition on AD0/CS after power-up and after the control port is activated, SPI format will be selected.
7.2 Two-Wire Format
In Two-Wire Format, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with a clock to data relationship as shown in Figure 8. The receiving device should send an acknowledge (ACK) after each byte re- ceived. There is no CS pin. Pins AD0 and AD1 forms the partial chip address and should be tied to VL or GND as required. The upper 6 bits of the 7- bit address field must be 001000. Note: MCLK is required during all two-wire transactions. The Two-Wire format is compatible with the I 2C protocol.
7.2.1 Writing in Two-Wire Format
To communicate with the CS44210, initiate a START condition of the bus. Next, send the chip address. The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then fol- lowed by the data to be written. To write multiple registers, continue providing a clock and data, waiting for the CS44210 to acknowledge between each byte. To end the transaction, send a STOP condition.
7.2.2 Reading in Two-Wire Format
To communicate with the CS44210, initiate a START condition of the bus. Next, send the chip address. The eighth bit of the address byte is the R/W bit (high for a read). The contents of the reg- ister pointed to by the MAP will be output after the chip address. To read multiple registers, continue providing a clock and issue an ACK after each byte. To end the transaction, send a STOP condi- tion.
7.3 SPI Format
In SPI format, CS is the CS44210 chip select sig- nal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller, CDOUT is the output data line, and the chip address is 0010000. CS, CCLK and CDIN are all inputs and data is clocked in on the rising edge of CCLK. CD- OUT is an output and is three-stated when not ac- tively outputting data.
7.3.1 Writing in SPI
Figure 9 shows the operation of the control port in SPI format. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address and must be 0010000. The eighth bit is a read/write in- dicator (R/W ), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into register designated by the MAP. To write multiple registers, keep CS low and continue providing clocks on CCLK. End the read transaction by setting CS high.
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001000 ADDR
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. Figure 8. Control Port Timing, Two-Wire Format Figure 9. Control Port Timing, SPI Format (Write)
7.3.2 Reading in SPI
CCLK. End the read transaction by setting CS high. The CDOUT line will tri-state once CS goes high.
7.4 Memory Address Pointer (MAP)
7.4.1 INCR (Auto Map Increment Enable)
7.4.2 MAP3-0 (Memory Address Pointer)
Figure 10. Control Port Timing, SPI Format (Read)
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Figure 11. Single Speed Stopband Rejection Figure 12. Single Speed Transition Band Figure 13. Single Speed Transition Band (Detail) Figure 14. Single Speed Passband Ripple Figure 15. Double Speed Stopband Rejection Figure 16. Double Speed Transition Band
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bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. The gain difference between left and right channels. Units in decibels.
9.0 REFERENCES
1) “The I 2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998. Figure 22. Right Justified, 16-Bit Data
- PACKAGE DIMENSIONS Note: 1.“D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2.Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters. 24L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW