CS4412 CIRRUS | Alldatasheet

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Features

 Configurable Outputs (10% THD+N) 2 x 15 W into 8 Ω, Full-Bridge 1 x 30 W into 4 Ω, Parallel Full-Bridge 4 x 7 W into 4 Ω, Half-Bridge 2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W into 8 Ω, Full-Bridge  Space-Efficient Thermally-Enhanced QFN No External Heat Sink Required  > 100 dB Dynamic Range - System Level  0.1% THD+N @ 1 W - System Level  Built-In Protection with Error Reporting Over-current Thermal Warning and Overload Under-voltage  +9 V to +18 V High Voltage Supply  PWM Popguard® for Quiet Startup  High Efficiency (85%)  Low RDS(ON)  Low Quiescent Current  Low Power Standby Mode Common Applications  Integrated Digital Televisions  Portable Docking Stations  Mini/Micro Shelf Systems  Powered Desktop Speakers General Description The CS4412 is a high-efficiency power stage for digital Class-D amplifiers designed to input PWM signals from a modulator such as the CS4525. The power stage out- puts can be configured as four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge channels, or one parallel full-bridge channel. The CS4412 integrates on-chip over-current, under- voltage, over-temperature protection and error report- ing as well as a thermal warning indicator. The low RDS(ON) outputs can source up to 2.4 A peak current, delivering 85% efficiency. This efficiency provides for a small device package and lower power supplies. The CS4412 is available in a 48-pin QFN package in Commercial grade (-40 to +70° C). The CRD4412 cus- tomer reference design is also available. Please refer to “Ordering Information” on page 22 for complete order- ing information. VP Amplifier Out 1 Amplifier Out 2 PGND Amplifier Out 3 Amplifier Out 4 Gate Drive Gate Drive Gate Drive Gate Drive

2.5 V to 5 V

9 V to 18 V

Protection & Error Reporting In 2 In 3 In 4 Current & Thermal Data Control Logic Hardware Configuration Reset Mode Configuration SEPTEMBER '06 DS749A1 CS4412

  1. PIN DESCRIPTION Pin Name Pin # Pin Description CNFG0 CNFG1 CNFG2 Out Configuration Select (Input) - Used to set the PWM output configuration mode. See “Output Mode Configuration” on page 14. IN1 IN2 IN3 IN4 PWM Input (Input) - Inputs from a PWM modulator. RST1/2 RST3/4 Reset Input (Input) - Reset inputs for channels 1/2 and 3/4 respectively. Active low. LVD VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying 5.0 V to VD, LVD must be connected to VD. When applying 2.5 V or 3.3 V to VD, LVD must be GND. VD_REG Core Digital Power (Output) - Filter connection for the internally generated power supply for the low voltage digital circuitry. VD Digital Power (Input) - Low voltage power supply for internal logic. VA_REG Core Analog Power (Output) - Filter connection for internally generated power supply for the low voltage analog circuitry Top-Down View 48-Pin QFN Package GND GND RST34 RAMP ERROC34 ERROC12 TWR GND GND GND GND CNFG0 CNFG1 CNFG2 IN1 IN2 RST12 VP OUT1 PGND PGND OUT2 VP VP OUT3 LVD VD_REG VD PGND PGND PGND PGND PGND PGND OUT4 VP OCREF PGND PGND RAMP_CAP ERRUVTE IN3 IN4 GND GND GND GND VA_REG CS4412

Over-current Reference (Input) - Sets over-current trip level. Connect pin through a resistor to GND. See “Device Protection and Error Reporting” on page 17. This pins should not be left float- ing. RAMP_CAP Output Ramp Capacitor (Input) - Sets the output ramp time for half-bridge configured outputs. GND 10,14 15,16 17,18 19,20 47,48 Ground (Input) - Ground for the internal logic and I/O. These pins should be connected to the common system ground. VP 25,30 31,36 High Voltage Output Power (Input) - High voltage power supply for the individual output power half-bridge devices. PGND 22,23 27,28 33,34 37,38 39,40 Power Ground (Input) - Ground for the individual output power half-bridge devices. These pins should be connected to the common system ground. OUT4 OUT3 OUT2 OUT1 PWM Output (Output) - Amplified PWM power half-bridge outputs. TWR Thermal Warning Output (Output) - Thermal warning output. Open drain, active low. See “Device Protection and Error Reporting” on page 17. ERRUVTE Thermal and Under-voltage Error Output (Output) - Error flag for thermal shutdown and under- voltage. Open drain, active low. See “Device Protection and Error Reporting” on page 17 ERROC1/2 ERROC3/4 Over-current Error Output (Output) - Over-current error flag for the associated outputs. Open drain, active low. See “Device Protection and Error Reporting” on page 17. RAMP Ramp-up/down Select (Input) - Set high to enable ramping. When set low, ramping is disabled. See “PWM Popguard Transient Control” on page 13. Pin Name Pin # Pin Description

  1. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND=PGND=0 V, all voltages with respect to ground. ABSOLUTE MAXIMUM RATINGS GND = PGND = 0 V; all voltages with respect to ground. (Note 1) Notes: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Any pin except supplies. Transient currents of up to ±100 mA on the PWM input pins will not cause SCR latch-up. The maximum over/under voltage is limited by the input current. Parameters Symbol Min Nom Max Units DC Power Supply Digital and Analog Core VD 2.375 2.5 2.625 V VD 3.135 3.3 3.465 V VD 4.75 5.0 5.25 V Power Stage VP 8.1 19.8 V Temperature Ambient Temperature Commercial TA -40 +70 Junction Temperature TJ +150 Parameters Symbol Min Max Units DC Power Supply Power Stage Outputs Switching and Under Load Power Stage No Output Switching Digital and Analog Core (Note 2) VP VP VD -0.3 -0.3 -0.3 19.8 23.0 6.0 V V V Inputs (Note 2) Input Current (Note 3) Iin ±10 mA Digital Input Voltage (Note 4) VIND -0.3 VD + 0.4 V Temperature (Note 2) Ambient Operating Temperature - Power Applied Commercial TA -40 +85 Storage Temperature Tstg -65 +150

PWM POWER OUTPUT CHARACTERISTICS Test Conditions (unless otherwise specified): GND = PGND = 0 V; All voltages with respect to ground; TA = 25° C; VD = 3.3 V; VP = 18 V; RL = 8 Ω for full-bridge, RL = 4 Ω for half-bridge and parallel full-bridge; PWM Switch Rate = 384 kHz; 10 Hz to 20 kHz Measurement Bandwidth; Input source is CS4525 PWM_SIG outputs; Performance measurements taken with a full scale 997 Hz sine wave and AES17 filter. Parameters Symbol Conditions Min Typ Max Units Power Output per Channel Stereo Full-Bridge Half-Bridge Parallel Full-Bridge PO THD+N < 10% THD+N < 1% THD+N < 10% THD+N < 1% THD+N < 10% THD+N < 1% 5.5 23.5 W W W W W W Total Harmonic Distortion + Noise Stereo Full-Bridge Half-Bridge Parallel Full-Bridge THD+N PO = 1 W PO = 0 dBFS = 11.3 W PO = 1 W PO = 0 dBFS = 5.0 W PO = 1 W PO = 0 dBFS = 22.6 W 0.1 0.3 0.1 0.3 0.1 0.3 Dynamic Range Stereo Full-Bridge Half-Bridge Parallel Full-Bridge DYR PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted PO = -60 dBFS, A-Weighted PO = -60 dBFS, Unweighted 102 102 102 dB dB dB dB dB dB MOSFET On Resistance RDS(ON) Id = 0.5 A, TJ = 50°C 518 615 mΩ Efficiency h PO = 2 x 11.3 W, RL = 8 Ω Minimum Output Pulse Width PWmin No Load ns Rise Time of OUTx tr Resistive Load ns Fall Time of OUTx tf Resistive Load ns PWM Output Over-Current Error Trip Point ICE OCREF = 16.2 kΩ 2.4 A Junction Thermal Warning Trip Point TTW 120 Junction Thermal Error Trip Point TTE 140 VP Under-Voltage Error Trip Point VUV 4.5 V Ramp-Up Time - Half-Bridge Configuration TRU Capacitor = 1000 µF 0.8 s Ramp-Down Time- Half-Bridge Configuration TRD Capacitor = 1000 µF s

DC ELECTRICAL CHARACTERISTICS GND = PGND = 0 V; All voltages with respect to ground; PWM switch rate = 384 kHz; Unless otherwise specified. Notes: Normal operation is defined as RSTx/y = HI. All outputs idle. Power-Down Mode is defined as RSTx/y = LOW with all input lines held static. Power supply current increases with increasing PWM switching rates. DIGITAL INTERFACE SPECIFICATIONS GND = PGND = 0 V; All voltages with respect to ground; Unless otherwise specified. Parameters Min Typ Max Units Normal Operation (Notes 5, 8) Power Supply Current VD = 3.3 V mA Power Dissipation VD = 3.3 V mW 50 % Duty Cycle VP Idle Current (Note 6) VP = 18 V mA Power-Down Mode (Note 7) Power Supply Current VD = 3 .3 V 4.3 mA Power Supply Current VP = 18 V 100 μA VD_REG Characteristics Nominal Voltage DC current source 2.25 2.5 2.75 V mA VA_REG Characteristics Nominal Voltage DC current source 2.25 2.5 2.75 V mA Parameters Symbol Min Max Units High-Level Input Voltage VIH 0.7*VD_REG VD V Low-Level Input Voltage VIL 0.20*VD_REG V High-Level Output Voltage Io=2 mA VOH 0.90*VD V Input Leakage Current Iin ±10 μA Input Capacitance pF

The logic level for each input is set by its corresponding power supply and should not exceed the maximum ratings.

9 V-18 V Power MOSFET

Table 1. I/O Power Rails

  1. TYPICAL CONNECTION DIAGRAMS

Figure 1. Stereo Full-Bridge Typical Connection Diagram

Figure 2. 2.1 Channel Typical Configuration Diagram

Figure 3. 4-Channel Half-Bridge Typical Connection Diagram

Figure 4. Mono Parallel Full-Bridge Typical Connection Diagram

  1. APPLICATIONS 4.1 Overview The CS4412 is a high-efficiency power stage for digital Class-D amplifiers designed to be configured as four half-bridge channels, two half-bridge channels and one full-bridge channel, two full-bridge channels, or one parallel full-bridge channel. The CS4412 integrates on-chip over-current, under-voltage, over-temperature protection and error report- ing as well as a thermal warning indicator. The low RDS(ON) outputs can source up to 2.4 A peak current, delivering 85% efficiency. This efficiency provides for smaller device package, no external heat sink require- ments, and smaller power supplies. 4.2 Reset and Power-Up Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks, and configuration pins are stable. It is also recommended that the RSTx/y pin be activated if the voltage supplies drop below the recommended operating condition to prevent power-glitch- related issues. When RSTx/y is low, the corresponding channels of the CS4412 enter a low-power mode and all of the channels’ internal states are reset and the outputs are set to HI-Z. When RSTx/y is high, the desired mode settings will be loaded and the outputs will begin normal operation. 4.2.1 PWM Popguard Transient Control The CS4412 uses Popguard technology to minimize the effects of output transients during power-up and power-down for half-bridge configurations. This technique reduces the audio transients commonly pro- duced by half-bridge, single-supply amplifiers when implemented with external DC-blocking capacitors connected in series with the audio outputs. When the device is configured for ramping (RAMP set high) and RSTx/y is set high, the OUTx/y outputs will ramp-up to the bias point (VP/2). This gradual voltage ramping allows time for the external DC-block- ing capacitor to charge to the quiescent voltage, minimizing the power-up transient. The OUTx/y outputs will not begin normal operation until the ramp has reached the bias point. The INx/y inputs must begin switching before the ramp cycle begins. When the device is configured for ramping (RAMP set high) and RSTx/y is set low, the OUTx/y outputs will begin to slowly ramp down from the bias point to PGND, allowing the DC-blocking capacitor to dis- charge. The ramp feature should only be used in quad half-bridge configuration. It is not necessary to complete a ramp-up/down sequence before ramping up/down again. 4.2.2 Recommended Power-Up Sequence Turn on the system power. Hold RSTx/y low until the power supply and system clocks are stable. In this state, all associated outputs are HI-Z. Start the PWM modulator output. Once the PWM modulator output is valid, release RSTx/y high. If the CS4412 is configured for ramping, the outputs will ramp to the bias point and then begin switching normally. If the CS4412 is not configured for ramping, the outputs will immediately begin switching normally.

4.2.3 Recommended Power-Down Sequence Mute the logic-level PWM inputs present on IN1 - IN4 by applying 50 % duty-cycle inputs. Set RSTx/y low. If the CS4412 is configured for ramping, the outputs will ramp down to PGND and then become HI-Z. If the CS4412 is not configured for ramping, the outputs will immediately become HI-Z. Power down the remainder of the system. Turn off the system power. 4.3 Output Mode Configuration The CS4412 can be configured for several modes of operation. Table 2 shows the setting of the CNFG[2:0] inputs and the corresponding mode of operation. These pins should remain static during operation (RSTx/y set high). CNFG2 CNFG1 CNFG0 Output Config.

Description

IN1 must be inverted from IN2 for full-bridge operation. IN3 must be inverted from IN4 for full-bridge operation. Stereo Half-Bridge and Mono Full- Bridge Tied Loads IN1 must be provided for half-bridge operation. IN2 must be provided for half-bridge operation. IN3 must be inverted from IN4 for full-bridge operation. Mono Parallel Full- Bridge Tied Load IN1 and IN3 must be inverted from IN2 and IN4 for parallel full- bridge operation. Quad Half-Bridge Tied Loads IN1 must be provided for half-bridge operation. IN2 must be provided for half-bridge operation. IN3 must be provided for half-bridge operation. IN4 must be provided for half-bridge operation. Stereo Full-Bridge Tied Loads With Inversion IN1 must be provided for full-bridge operation. Wire IN2 to IN1. IN2 is internally inverted for full-bridge operation. IN3 must be provided for full-bridge operation. Wire IN4 to IN3. IN4 is internally inverted for full-bridge operation. Stereo Half-Bridge & Mono Full-Bridge Tied Loads With Inversion IN1 must be provided for half-bridge operation. IN2 must be provided for half-bridge operation. IN3 must be provided for full-bridge operation. Wire IN4 to IN3. IN4 is internally inverted for full-bridge operation. Mono Parallel Full- Bridge Tied Load With Inversion IN1 must be provided for parallel full-bridge operation. Wire IN4, IN3, and IN2 to IN1. IN2 and IN4 are internally inverted for parallel full-bridge operation. Quad Half-Bridge Tied Loads IN1 must be provided for half-bridge operation. IN2 must be provided for half-bridge operation. IN3 must be provided for half-bridge operation. IN4 must be provided for half-bridge operation. Table 2. Output Mode Configuration Options

of these preset thresholds are crossed. that channel has been toggled from low to high. VP falls below the VP under-voltage error trip point, ERRUVTE will be set low. Over-current error on channel x or channel y. Operating current of channel x and y within allowable limits. Table 6. Over-current Error Conditions Thermal warning and thermal error and/or under-voltage error. Junction temperature and VP voltage within normal limits. Table 7. Thermal and Under-Voltage Error Conditions

  1. POWER SUPPLY, GROUNDING, AND PCB LAYOUT

design demonstrates the optimum layout and power supply arrangements. pin as shown in Table 8 below. in the typical connection diagrams. to directly drive the internal digital and analog sections. layers. The CRD4412 reference design demonstrates the optimum thermal pad and via configuration.

5 V Nominal

Table 8. VD Supply Level Indication

  1. PARAMETER DEFINITIONS Dynamic Range (DYR) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measurement over the spec- ified band width made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Ex- pressed in decibels. Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
  1. PACKAGE DIMENSIONS Notes: Dimensioning and tolerance per ASME Y4.5M - 1994. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0.0354 0.90 0.0000 0.0020 0.00 0.05 b 0.0118 0.0138 0.0157 0.30 0.35 0.40 1,2 D

0.3543 BSC

9.00 BSC

0.2618 0.2677 0.2736 6.65 6.80 6.95 E 0.2618 0.2677 0.2736 6.65 6.80 6.95 e

0.0256 BSC

0.65 BSC

L 0.0177 0.0217 0.0276 0.45 0.55 0.70 JEDEC #: MO-220 Controlling Dimension is Millimeters. Side View Bottom View Top View A Pin #1 ID D E L b e Pin #1 ID 48L QFN (9 × 9 MM BODY) PACKAGE DRAWING

  1. THERMAL CHARACTERISTICS 8.1 Thermal Flag This device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane on the PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be cou- pled with vias to a large metal plane on the backside (and inner ground layer, if applicable) of the PCB. In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those immediately surrounding the CS4412. In addition to improving in electrical performance, this practice also aids in heat dissipation. The heat dissipation capability required of the metal plane for a given output power can be calculated as follows: θCA = [(TJ(MAX) - TA) / PD] - θJC where, θCA = Thermal resistance of the metal plane in °C/Watt TJ(MAX) = Maximum rated operating junction temperature in °C, equal to 150 °C TA = Ambient temperature in °C PD = RMS power dissipation of the device, equal to 0.15*PRMS-IN or 0.176*PRMS-OUT (assuming 85% effi- ciency) θJC = Junction-to-case thermal resistance of the device in °C/Watt Parameter Symbol Min Typ Max Units Junction to Case Thermal Impedance θJC °C/Watt
  1. ORDERING INFORMATION 10.REVISION HISTORY Product

Order# CS4412

30 W Quad Half-

-40° to +70°C Rail CS4412-CNZ Tape and Reel CS4412-CNZR CRD4412 1 x 30 W Reference Design Daughter Card CRD4412 CRD4525 2 x 15 W Reference Design Main Board CRD4525 Release Changes Initial Release Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) be- lieve that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the infor- mation only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.