CS4360_04 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
/circle6 24-bit Conversion /circle6 102 dB Dynamic Range /circle6 -91 dB THD+N /circle6 Low Clock Jitter Sensitivity /circle6 Digital Volume Control with Soft Ramp – 119 dB Attenuation – 1-dB Step Size – Zero Crossing Click-Free Transitions /circle6 ATAPI Mixing /circle6 Logic Levels Between 5.0 V and 1.8 V /circle6 +3.3 V or +5 V Analog Power Supply /circle6 116 mW with 3.3 V Supply /circle6 Popguard Technology® for Control of Clicks and Pops
Description
The CS4360 is a complete 6-channel digital-to-analog system including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera- ture, and a high tolerance to clock jitter. The CS4360 accepts data at audio sample rates from 4 kHz to 200 kHz, consumes very little power, and oper- ates over a wide power supply range. These features are ideal for cost-sensitive, multi-channel audio systems in- cluding DVD players, A/V receivers, set-top boxes, digital TVs and VCRs, mini-component systems, and mixing consoles.
ORDERING INFORMATION
CS4360-KZ -10 to 70 °C 28-pin TSSOP CS4360-KZZ -10 to 70 °C Lead Free 28-pin TSSOP CS4360-DZZ -40 to 85 °C Lead Free 28-pin TSSOP CDB4360 Evaluation Board I Control Port External Mute Control RST Volume ControlInterpolation Filter Analog Filter AOUT A 1∆Σ DAC Mixer Volume Control ∆Σ DAC Analog Filter AO UTB1Interpolation Filter Volume ControlInterpolation Filter Analog Filter AOUTA2∆Σ DAC Mixer Volume Control ∆Σ DAC Analog Filter AO UTB2Interpolation Filter Volume ControlInterpolation Filter Analog Filter AOUT A 3∆Σ DAC Mixer Volume Control ∆Σ DAC Analog Filter AO UT B3Interpolation Filter MCLK Serial Port LRCK SCLK SD I N1 SD I N2 SD I N3 DIF1/SCL/CCLK DIF0/SDA/CDIN M1/AD0/CS VLC ÷2 VQ FILT+ VAGNDVD VLS MUTEC1 MUTEC2 MUTEC3M2 GND JUL ‘04 DS517F2
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Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com/ IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is sub- ject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and con- ditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsi- bility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANT- ED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOM- ER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. Purchase of I²C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies con- veys a license under the Philips I²C Patent Rights to use those components in a standard I²C system.
6.3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h)
Mixing Control Pair 2 (Channels A2 & B2) (address 04h)
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Figure 16. I
- PIN DESCRIPTION VLS MUTEC1 SDIN1 AOUTA1 SDIN2 AOUTB1 SDIN3 MUTEC2 SCLK AOUTA2 LRCK AOUTB2 MCLK VA VD GND GND AOUTA3 RST AOUTB3 DIF1/SCL/CCLK MUTEC3 DIF0/SDA/CDIN VQ M1/AD0/CS FILT+ VLC M2 82 1 12 17 14 15 CS4360
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Pin Name # Pin Description VLS 1 Serial Audio Interface Power (Input) - Positive power for the serial audio interface. SDIN1 SDIN2 SDIN3 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. SCLK 5 Serial Clock (Input) - Serial clock for the serial audio interface. LRCK 6 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. MCLK 7 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. VD 8 Digital Power (Input) - Positive power supply for the digital section. GND 9 Ground (Input) RST 10 Reset (Input) - Powers down device and resets all internal resisters to their default settings. VLC 14 Control Port Interface Power (Input) - Positive power for the control port interface. FILT+ 16 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VA 22 Analog Power (Input) - Positive power supply for the analog section. AOUTB3 AOUTA3 AOUTB2 AOUTA2 AOUTB1 AOUTA1 Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Characteris- tics and Specifications table. MUTEC3 MUTEC2 MUTEC1 Mute Control (Output) - Control signal for optional mute circuit. Control Port Definitions SCL/CCLK 11 Serial Control Port Clock (Input) - Serial clock for the control port interface. SDA/CDIN 12 Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Input for SPI data. AD0/CS 13 Address Bit / Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select the chip in SPI mode. Stand-Alone Definitions DIF1 DIF0 Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial Clock and Serial Audio Data. Mode Selection (Input) - Determines the operational mode of the device.
- TYPICAL CONNECTION DIAGRAM
23 AOUTB2
19 AOUTB3
Figure 1. Typical Connection Diagram
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- CHARACTERISTICS AND SPECIFICATIONS Typical performance characteristics are derived from measurements taken at T A = 25°C. Min/Max performance characteristics and specifications are guaranteed over the operating temperature and voltages. SPECIFIED OPERATING CONDITIONS GND = 0 V; all voltages with respect to GND. ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to GND. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Nominal VD supply must be less than or equal to the nominal VA supply. 2. Any pin except supplies. Parameters Symbol Min Typ Max Units DC Power Supply Analog 3.3 V Nominal (Note 1) 5.0 V Nominal VA 3.0 4.5 3.3 3.6 5.5 V V Digital 2.5 V Nominal (Note 1) 3.3 V Nominal
5.0 V Nominal
VD 2.25 3.0 4.5 2.5 3.3 2.75 3.6 5.5 V V V Serial Audio Interface 1.8 V Nominal
2.5 V Nominal
3.3 V Nominal
VLS 1.7 2.25 3.0 4.5 1.8 2.5 3.3 1.9 2.75 3.6 5.5 V V V V Control Port Interface 1.8 V Nominal VLC 1.7 2.25 3.0 4.5 1.8 2.5 3.3 1.9 2.75 3.6 5.5 V V V V Parameters Symbol Min Max Units DC Power Supply Analog Digital Serial Audio Interface Control Port Interface VA VD VLS VLC -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 V V V V Input Current (Note 2) Iin -± 1 0 m A Digital Input Voltage Serial Audio Interface Control Port Interface VIND_S VIND_C -0.3 -0.3 VLS+0.4 VLC+0.4 V V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C
ANALOG CHARACTERISTICS (CS4360-KZ/KZZ) Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load R L =1 0k Ω, CL = 10 pF (see Figure 2). All supplies = VA = 5.0 V or 3.3 V. Notes: 3. One-half LSB of triangular PDF dither is added to data. Parameter 5.0 V 3.3 V Min Typ Max Min Typ Max Unit Single-Speed Mode Fs = 48 kHz Dynamic Range (Note 3) unweighted A-Weighted A-Weighted 102 100 dB dB dB Total Harmonic Distortion + Noise (Note 3) 0 dB -20 dB -60 dB -91 -79 -39 -86 -91 -74 -34 -86 dB dB dB Double-Speed Mode Fs = 96 kHz Dynamic Range (Note 3) unweighted A-Weighted 40 kHz Bandwidth A-Weighted 102 100 dB dB dB Total Harmonic Distortion + Noise (Note 3) 0 dB -20 dB -60 dB -91 -79 -39 -86 -91 -74 -34 -86 dB dB dB Quad-Speed Mode Fs = 192 kHz Dynamic Range (Note 3) unweighted A-Weighted 40 kHz Bandwidth A-Weighted 102 100 dB dB dB Total Harmonic Distortion + Noise (Note 3) 0 dB -20 dB -60 dB -91 -79 -39 -86 -91 -74 -34 -86 dB dB dB
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Figure 2. Output Test Load Figure 3. Maximum Loading
ANALOG CHARACTERISTICS (CS4360-DZZ) Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 10 kΩ, CL = 10 pF (see Figure 2). All supplies = VA = 5.0 V and 3.3 V. Parameter VA = 5.0 V VA = 3.3 V Min Typ Max Min Typ Max Unit Single-speed Mode Fs = 48 kHz Dynamic Range (Note 3) unweighted A-Weighted A-Weighted 102 100 dB dB dB Total Harmonic Distortion + Noise (Note 3) 0 dB -20 dB -60 dB -91 -79 -39 -84 -91 -74 -34 -84 dB dB dB Double-speed Mode Fs = 96 kHz Dynamic Range (Note 3) unweighted A-Weighted 40 kHz Bandwidth A-Weighted 102 100 dB dB dB Total Harmonic Distortion + Noise (Note 3) 0 dB -20 dB -60 dB -91 -79 -39 -84 -91 -74 -34 -84 dB dB dB Quad-speed Mode Fs = 192 kHz Dynamic Range (Note 3) unweighted A-Weighted 40 kHz Bandwidth A-Weighted 102 100 dB dB dB Total Harmonic Distortion + Noise (Note 3) 0 dB -20 dB -60 dB -91 -79 -39 -84 -91 -74 -34 -84 dB dB dB
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ANALOG CHARACTERISTICS (CS4360-DZZ) (Continued) Parameters Symbol Min Typ Max Units Dynamic Performance for All Modes Interchannel Isolation (1 kHz) - 102 - dB DC Accuracy Interchannel Gain Mismatch ICGM - 0.1 - dB Gain Drift - ±100 - ppm/°C Analog Output Characteristics and Specifications Full Scale Output Voltage 0.60VA 0.66VA 0.72VA Vpp Output Impedance Z out - 100 - Ω AC-load Resistance (Note 4) RL 3--k Ω Load Capacitance (Note 4) CL -- 1 0 0 p F
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Notes: 5. For Single-speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 6. De-emphasis is only available in Single-speed Mode. Parameter Min Typ Max Unit Single-Speed Mode (4 kHz to 50 kHz sample rates) Passband to -0.05 dB corner to -3 dB corner 0.4535 0.4998 Fs Fs Frequency Response 10 Hz to 20 kHz -0.02 - +0.035 dB StopBand 0.5465 - - Fs StopBand Attenuation (Note 5) 50 - - dB Group Delay - 9/Fs - s De-emphasis Error (Relative to 1 kHz) (Note 6) Control Port Mode Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz Stand-alone Mode Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz +0.2/-0.1 +0.05/-0.14 +0/-0.22 +1.5/-0 +0.05/-0.14 +0.2/-0.4 dB dB dB dB dB dB Double-Speed Mode (50 kHz to 100 kHz sample rates) Passband to -0.1 dB corner to -3 dB corner 0.4621 0.4982 Fs Fs Frequency Response 10 Hz to 20 kHz -0.1 - 0 dB StopBand 0.577 - - Fs StopBand Attenuation (Note 5) 55 - - dB Group Delay - 4/Fs - s Quad-Speed Mode - (100 kHz to 200 kHz sample rates) Passband to -3 dB corner 0 - 0.25 Fs Frequency Response 10 Hz to 20 kHz -0.7 - 0 dB Group Delay - 1.5/Fs - s
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Figure 4. Single-speed Stopband Rejection Figure 5. Single-speed Transition Band Figure 6. Single-speed Transition Band (Detail) Figure 7. Single-speed Passband Ripple Figure 8. Double-speed Stopband Rejection Figure 9. Double-speed Transition Band
Figure 10. Double-speed Transition Band (Detail) Figure 11. Double-speed Passband Ripple
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Inputs: Logic 0 = GND, Logic 1 = VLS. Figure 12. Serial Mode Input Timing
Notes: 7. Data must be held for sufficient time to bridge the transition time, t fc, of SCL.
- The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
- for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode.
Figure 13. Control Port Timing - I²C Mode
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Notes: 10. t spi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
- Data must be held for sufficient time to bridge the transition time of CCLK.
Figure 14. Control Port Timing - SPI Mode
DC ELECTRICAL CHARACTERISTICS GND = 0 V; all voltages with respect to GND. Notes: 13. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 14. I LC measured with no external loading on pin 12 (SDA). 15. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 16. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 1. Increasing the capacitance will also increase the PSRR. DIGITAL INPUT CHARACTERISTICS GND = 0 V; all voltages with respect to GND. Parameters Symbol Min Typ Max Units Normal Operation (Note 13) Power Supply Current VA = 5.0 V VD = 5.0 V VA = 3.3 V VD = 3.3 V VLS = 5.0 V VLC = 5.0 V VLS = 3.3 V VLC = 3.3 V (Note 14) IA ID IA ID ILS ILC ILS ILC mA mA mA mA µA µA µA µA Power Dissipation All Supplies = 5.0 V All Supplies = 3.3 V 235 116 265 128 mW mW Power-down Mode (Note 15) Power Supply Current All Supplies = 5.0 V All Supplies = 3.3 V µA µA Power Dissipation All Supplies = 5.0 V All Supplies = 3.3 V µW µW All Modes of Operation Power Supply Rejection Ratio (Note 16) 1 kHz 60 Hz PSRR - dB dB VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink 0.5VA 250 0.01 V kΩ mA Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink VA 250 0.01 V kΩ mA MUTEC Low-level Output Voltage - 0 - V MUTEC High-level Output Voltage - VA - V Maximum MUTEC Drive Current - 3 - mA Parameters Symbol Min Typ Max Units Input Leakage Current I in -- ± 1 0 µA Input Capacitance - 8 - pF
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DIGITAL INTERFACE SPECIFICATIONS GND = 0 V; all voltages with respect to GND. THERMAL CHARACTERISTICS AND SPECIFICATIONS Parameters Symbol Min Max Units
1.8 V Logic
High-level Input Voltage Serial Audio Control Port VIH VIH 80% 80% VLS VLC Low-level Input Voltage Serial Audio Control Port VIL VIL - 13% 13% VLS VLC
2.5 V Logic
High-level Input Voltage Serial Audio Control Port VIH VIH 70% 70% VLS VLC Low-level Input Voltage Serial Audio Control Port VIL VIL - 13% 13% VLS VLC
3.3 V Logic
High-level Input Voltage Serial Audio Control Port VIH VIH 70% 70% VLS VLC Low-level Input Voltage Serial Audio Control Port VIL VIL - 13% 13% VLS VLC
5.0 V Logic
High-level Input Voltage Serial Audio Control Port VIH VIH 70% 70% VLS VLC Low-level Input Voltage Serial Audio Control Port VIL VIL - 13% 13% VLS VLC Parameters Symbol Min Typ Max Units Package Thermal Resistance TSSOP (-KZ/KZZ & -DZZ) θJA -4 0- ° C / W a t t Ambient Operating Temperature (Power Applied) -KZ/KZZ -DZZ TA -10 -40 +70 +85
4.1 Sample Rate Range/Operational Mode Select
4.1.1 Stand-Alone Mode
The device operates in one of four operational modes determined by the Mode pins in Stand-alone mode. Sample rates outside the specified range for each mode are not supported.
4.1.2 Control Port Mode
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. sample rates and the required MCLK frequency, are illustrated in Tables 3-5. Table 3. Single-speed Mode Standard Frequencies Table 4. Double-speed Mode Standard Frequencies Table 1. CS4360 Stand-Alone Operational Mode Table 2. CS4360 Control Port Operational Mode
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4.3 Digital Interface Format
in Table 6, and 1 of 6 formats in Control Port mode, as illustrated in Table 8.
4.3.1 Stand-Alone Mode
between the LRCK, SCLK and SDIN, see Figures 15-17. Table 5. Quad-speed Mode Standard Frequencies
00 Left Justified, up to 24-bit Data 01 6
01 I2S, up to 24-bit Data 11 5
10 Right Justified, 16-bit Data 21 7
11 Right Justified, 24-bit Data 31 7
Table 6. Digital Interface Format - Stand-alone Mode
4.3.2 Control Port Mode
6.1.2). For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 15-17.
4.4 De-Emphasis Control
Notes: De-emphasis is only available in Single-speed Mode. Figure 15. Left Justified up to 24-Bit Data Figure 16. I2S, up to 24-Bit Data Figure 17. Right Justified Data Figure 18. De-emphasis Curve
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4.4.1 Stand-Alone Mode
The operational mode pins, M2 and M1, selects the 44.1 kHz de-emphasis filter. Please see section 4.1 for the desired de-emphasis control.
4.4.2 Control Port Mode
The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see section 6.1.3 for the desired de-emphasis control.
4.5 Recommended Power-up Sequence
4.5.1 Stand-Alone Mode
1) Hold RST low until the power supply and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default settings and VQ will remain low. 2) Bring RST high. The device will remain in a low power state with VQ low and will initiate the Stand- alone power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.5.2 Control Port Mode
1) Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default settings and VQ will remain low. 2) Bring RST high. The device will remain in a low power state with VQ low. 3) Load the desired register settings while keeping the PDN bit set to 1. 4) Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS when the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.6 for a complete description of pow- er-up timing.
4.6 Popguard ® Transient Control
The CS4360 uses a novel technique to minimize the effects of output transients during power-up and pow- er-down. This technology, when used with external DC-blocking capacitors in series with the audio out- puts, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when the RST pin or PDN bit is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.
4.6.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTAx and AOUTBx, are clamped to GND. Following a delay of approximately 1000 LRCK cycles, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach V Q and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient.
4.6.2 Power-down
To prevent transients at power-down, the device must first enter its power-down state. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTAx and AOUTBx. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.
4.6.3 Discharge Time
with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
4.7 Mute Control
circuits to prevent the clicks and pops that can occur in any single-ended single supply system. circuit. Please see the CDB4360 data sheet for a suggested mute circuit.
4.8 Grounding and Power Supply Arrangements
4.8.1 Capacitor Placement
pacitor should still be placed on each supply pin and referenced to analog ground.
4.8.2 Power Supply Sections
= 3.3 V; VD = VA = 5 V; then the logic level for all mode configuration inputs must equal 1.8 V.
4.9 Control Port Interface
ence problems, the control port pins should remain static if no operation is required. The control port operates in one of two modes: I²C or SPI. Notes: MCLK must be applied during all I²C communication. Table 7. Power Supply Control Sections
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4.9.1 Memory Address Pointer (MAP)
The MAP byte precedes the control port register byte during a write operation and is not available again until after a start condition is initiated. During a read operation the byte transmitted after the ACK will con- 4.9.1a INCR (Auto Map Increment) The device has MAP auto increment capability enabled by the I NCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. Default = ‘0’ 0 - Disabled 1 - Enabled 4.9.1b MAP0-3 (Memory Address Pointer) Default = ‘0000’
4.9.2 I²C Mode
In the I²C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL. There is no CS pin. Pin AD0 enables the user to alter the chip address (001000[AD0][R/W ]) and should be tied to VLC or GND as required, before powering up the device. If the device ever detects a high-to-low transition on the AD0/CS pin after power-up, SPI mode will be selected. 4.9.2a I²C Write To write to the device, follow the procedure below while adhering to the control port Switching Specifica- tions in section 3. 1) Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. 2) Wait for an acknowledge (ACK) from the device, then write to the memory address pointer, MAP. This byte points to the register to be written. 3) Wait for an acknowledge (ACK) from the device, then write the desired data to the register pointed to by the MAP. 4) If the INCR bit (see section 4.9.1a) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5) If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to repeat the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus. 76543210 INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0 00000000
desired registers are read, initiate a STOP condition to the bus.
4.9.3 SPI Mode
001000 AD0 W
Figure 19. I²C Write Figure 20. I²C Read
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2) The address byte on the CDIN pin must then be 00100000. 3) Write to the memory address pointer, MAP. This byte points to the register to be written. 4) Write the desired data to the register pointed to by the MAP. Figure 21. SPI Write
- REGISTER QUICK REFERENCE Addr Function 7 6 5 4 3 2 1 0 1h Mode Control 1 AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0 default 10000000 2h Invert Signal Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1 default 00000000 3h Mixing Control P1 Reserved Reserved Reserved Reserved P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0 default 00001001 4h Mixing Control P2 Reserved Reserved Reserved Reserved P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0 default 00001001 5h Mixing Control P3 Reserved Reserved Reserved Reserved P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0 default 00001001 6h Volume Control A1 A1_MUTE A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0 default 00000000 7h Volume Control B1 B1_MUTE B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0 default 00000000 8h Volume Control A2 A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0 default 00000000 9h Volume Control B2 B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0 default 00000000 0Ah Volume Control A3 A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0 default 00000000 0Bh Volume Control B3 B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0 default 00000000 0Ch Mode Control 2 SZC1 SZC0 CPEN PDN POPG FREEZE MCLKDIV SNGLVOL default 10 0 11000 0Dh Revision Indicator Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0 default 0000XXXX
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Note: All registers are read/write in I²C mode and write only in SPI, unless otherwise stated.
6.1 MODE CONTROL 1 (ADDRESS 01H)
6.1.1 AUTO-MUTE (AMUTE) BIT 7
to volume control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.
6.1.2 DIGITAL INTERFACE FORMAT (DIF)
Digital Interface Format and the options are detailed in Figures 15-17.
000 Left Justified, up to 24-bit data 01 5
001 I2S, up to 24-bit data 11 6
010 Right Justified, 16-bit data 21 7
011 Right Justified, 24-bit data 31 7
100 Right Justified, 20-bit data 41 7
101 Right Justified, 18-bit data 51 7
110 Reserved --
111 Reserved --
Table 8. Digital Interface Formats - Control Port Mode
6.1.3 DE-EMPHASIS CONTROL (DEM) BIT 2-3
Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re- sponse at 32-, 44.1- or 48-kHz sample rates. (See Figure 18.) Note: De-emphasis is only available in Single-speed Mode.
6.1.4 FUNCTIONAL MODE (FM) BIT 0-1
Default = 00 00 - Single-speed Mode (4- to 50-kHz sample rates) 01 - Double-speed Mode (50- to 100-kHz sample rates) 10 - Quad-speed Mode (100- to 200-kHz sample rates) 11 - Reserved Function: Selects the required range of input sample rates.
6.2 INVERT SIGNAL (ADDRESS 02H)
6.2.1 INVERT SIGNAL POLARITY (INV_XX) BIT 0-5
Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits invert the signal polarity for each of their respective channels. MIXING CONTROL PAIR 2 (CHANNELS A2 & B2) (ADDRESS 04H) MIXING CONTROL PAIR 3 (CHANNELS A3 & B3) (ADDRESS 05H) 76543210 Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1 00000000 76543210 Reserved Reserved Reserved Reserved PxATAPI3 PxATAPI2 PxATAPI1 PxATAPI0 00001001
32 DS517F2
6.3.1 ATAPI CHANNEL MIXING AND MUTING (ATAPI) BIT 0-3
Table 9 and Figure 22 for additional information. Note: All mixing functions occur prior to the digital volume control. Mixing only occurs in channel pairs.
0000 M U T E M U T E
0001 M U T E R
0010 M U T E L
0011 M U T E [ ( L + R ) / 2 ]
0100 R M U T E
0101 R R
0110 R L
0111 R [ ( L + R ) / 2 ]
1000 L M U T E
1001 L R
1010 L L
1011 L [ ( L + R ) / 2 ]
Table 9. ATAPI Decode Figure 22. ATAPI Block Diagram
6.4 VOLUME CONTROL (ADDRESSES 06H - 0BH)
6.4.1 MUTE (MUTE) BIT 7
for both channels in the pair.
6.4.2 VOLUME CONTROL (XX_VOL)
are equivalent to enabling the MUTE bit.
6.5 MODE CONTROL 2 (ADDRESS 0DH)
6.5.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC) BIT 6-7
When Immediate Change is selected all level c hanges will be implemented im mediately in one step. Table 10. Example Digital Volume Settings
34 DS517F2
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon- itored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp and Zero Cross Soft Ramp and Zero Cross dictates that signal level changes, either by attenuation changes or mut- ing, will occur in 1/8 dB steps and will be implemented on successive signal zero crossings. The 1/8 dB level changes will occur after timeout periods between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter zero crossings. The zero cross function is independently monitored and implemented for each channel.
6.5.2 CONTROL PORT ENABLE (CPEN)
Default = 0 0 - Disabled 1 - Enabled Function: The Control Port will become active and reset to the default settings when this function is enabled.
6.5.3 POWER DOWN (PDN) BIT 4
Default = 1 0 - Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, but the contents of the control registers will be retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation in Control Port mode can occur.
6.5.4 POPGUARD® TRANSIENT CONTROL (POPG)
Default = 1 0 - Disabled 1 - Enabled Function: The PopGuard® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to the quiescent voltage during power-on or power-off when this function is enabled. Please see section 4.6 for implementation details.
6.5.5 FREEZE CONTROLS (FREEZE) BIT 2
Default = 0 0 - Disabled 1 - Enabled Function: This function allows modifications to be made to the registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simulta- neously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
6.5.6 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)
Default = 0 0 - Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry.
6.5.7 SINGLE VOLUME CONTROL (SNGLVOL)
Default = 0 0 - Disabled 1 - Enabled Function: The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. When enabled, the volume on all channels is determined by the A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored.
6.6 REVISION REGISTER (READ ONLY) (ADDRESS 0DH)
6.6.1 REVISION INDICATOR (REV) [READ ONLY] BIT 0-3
Default = none etc. Function: This read-only register indicates the revision level of the device. 76543210 Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0
0000 XXXX
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- PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the spec- ified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-t o-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering So- ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 8. REFERENCES 1) CDB4360 Evaluation Board Datasheet 2) “The I²C Bus Specification: Version 2.1” Philips Semiconductors, January 2000. http://www.semiconductors.philips.com
- PACKAGE DIMENSIONS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters. 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW