CS4352_07 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
Multi-bit Delta-Sigma Modulator 24-Bit Resolution Supports Sample Rates up to 192 kHz 106 dB A-wt Dynamic Range -93 dB THD+N Integrated Line Driver 2 Vrms Output into 5 kΩ AC Load Analog Low-Pass Filter Stereo Mutes with Auto-Mute Function Low Clock-Jitter Sensitivity Low-Latency Digital Filtering Popguard® Technology for Control of Clicks and Pops Single-Ended Outputs +3.3 V Core, +9 to 12 V Analog, and +1.5 to
3.3 V Interface Power Supplies
Low Power Consumption 20-pin TSSOP, Lead-Free Assembly
Description
The CS4352 is a complete stereo digital-to-analog sys- tem including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-em- phasis, analog filtering, and on-chip 2 Vrms line-level driver. The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to re- sistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. The CS4352 is available in a 20-pin TSSOP package in both Commercial grade (-40°C to +85°C) and Automo- tive grade (-40°C to +105°C). The CDB4352 Customer Demonstration Board is also available for device evalu- ation and implementation suggestions. Please see “Ordering Information” on page 20 for complete details. These features are ideal fo r cost-sensitive, 2-channel audio systems including video game consoles, DVD players, A/V receivers, se t-top boxes, digital TVs and DVD Recorders, mini-component systems, and mixing consoles. PCM Serial Interface Interpolation Filter Serial Audio Input Left and Right Mute Controls
2 Vrms Line Level
1.5 V to 3.3 V Hardware Configuration Level Translator Hardware Control Multibit ∆Σ Modulator
3.3 V 9 V to 12 V
∆Σ Modulator Auto Speed Mode Detect DAC DAC External Mute ControlInternal Voltage Reference JUN '07 DS684F2 CS4352Confidential Draft 6/18/07
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- PIN DESCRIPTIONS Pin Name Pin # Pin Description SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. SCLK 2 Serial Clock (Input) - Serial clock for the serial audio interface. LRCK 3 Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. MCLK 4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. VD 5 Digital Power (Input) - Positive power supply for the digital section. GND 6 16 Ground (Input) - Ground reference. DIF0 DIF1 Digital Interface Format (Input) - Defines the required relationship between the Left/Right Clock, Serial Clock, and Serial Audio Data. DEM 9 De-emphasis (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for 44.1 kHz sample rates RST 10 Reset (Input) - Powers down the device and resets all internal registers to their default settings when enabled. VA 11 Low Voltage Analog Power (Input) - Positive power supply for the analog section. VBIAS 12 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC. VQ 13 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VA_H 17 High Voltage Analog Power (Input) - Positive power supply for the analog section. VL 20 Serial Audio Interface Power (Input) - Positive power for the serial audio interface BMUTEC AMUTEC 19 Mute Control (Output) - Control signal for optional mute circuit. AOUTB AOUTA Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteris- tics table. SDIN VL SCLK AMUTEC LRCK AOUTA MCLK VA_H VD GND GND AOUTB DIF1 BMUTEC DIF0 VQ DEM VBIAS RST VA 10 11
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- CHARACTERISTICS A ND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.) ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.) Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guar- anteed at these extremes. Parameters Symbol Min Typ Max Units DC Power Supply High Voltage Analog power Low Voltage Analog power Digital power Interface power VA_H VA VD VL 8.40 3.13 3.13 1.43 3.3 3.3 1.5 12.6 3.47 3.47 3.47 V V V V Ambient Operating Temperature (power applied) -CZZ -DZZ T A -40 -40 +85 +105 Parameters Symbol Min Max Units DC Power Supply High Voltage Analog power Low Voltage Analog power Digital power Interface power VA_H VA VD VL -0.3 -0.3 -0.3 -0.3 14.0 3.63 3.63 3.63 V V V V Input Current, Any Pin Except Supplies I in -± 1 0 m A Digital Input Voltage Digital Interface V IN-L -0.3 V L+ 0.4 V Ambient Operating Temperature (power applied) T A -55 +125 °C Storage Temperature T stg -65 +150 °C
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ) Test conditions (unless otherwise specified): TA = 25 °C, VA_H = 9 V, VA = 3.3 V, VD = 3.3 V GND = 0 V; VBIAS+ and VQ capacitors as shown in Figure 2 on page 10; input test signal is a 997 Hz sine wave at 0 dBFS; measure- ment bandwidth 10 Hz to 20 kHz. Notes: 1. One-half LSB of triangular PDF dither is added to data. Parameter Symbol Min Typ Max Unit All Speed Modes Fs = 48, 96, and 192 kHz Dynamic Range (Note 1) 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted 100 106 103 dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 24-bit 0 dB -20 dB -60 dB 16-bit 0 dB -20 dB -60 dB THD+N -93 -83 -43 -93 -75 -35 -89 -77 -37 dB dB dB dB dB dB Idle Channel Noise / Signal-to-noise ratio (A-wt) - 106 - dB Interchannel Isolation (1 kHz) - 99 - dB Analog Output - All Modes Full Scale Output Voltage 1.84 2.00 2.11 Vrms Common Mode Voltage V Q -4- V d c Max Current draw from an AOUT pin I OUTmax - 575 - µA Max Current draw from VQ I Qmax -1- µA Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C Output Impedance Z OUT -5 0- Ω AC-Load Resistance R L 5-- k Ω Load Capacitance C L -- 1 0 0 p F
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DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ) Test conditions (unless otherwise specified): TA = -40°C to 85°C, VA_H = 9 V, VA = 3.3 V, VD = 3.3 V GND = 0 V; VBIAS+ and VQ capacitors as shown in Figure 2 on page 10; input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz. Notes: 2. One-half LSB of triangular PDF dither is added to data. Parameter Symbol Min Typ Max Unit All Speed Modes Fs = 48, 96, and 192 kHz Dynamic Range (Note 2) 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted 106 103 dB dB dB dB Total Harmonic Distortion + Noise (Note 2) 24-bit 0 dB -20 dB -60 dB 16-bit 0 dB -20 dB -60 dB THD+N -93 -83 -43 -93 -75 -35 -89 -73 -33 dB dB dB dB dB dB Idle Channel Noise / Signal-to-noise ratio (A-wt) - 106 - dB Interchannel Isolation (1 kHz) - 99 - dB Analog Output - All Modes Full Scale Output Voltage 1.81 2.00 2.17 Vrms Common Mode Voltage V Q -4- V d c Max Current draw from an AOUT pin I OUTmax -5 7 5- µA Max Current draw from VQ I Qmax -1- µA Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C Output Impedance Z OUT -5 0- Ω AC-Load Resistance R L 5-- k Ω Load Capacitance C L - - 100 pF
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by Fs. Amplitude vs. frequency plots of the data in the table below are available in “Digital Filter Response Plots” on page 16.) Notes: 3. Response is clock-dependent and will scale with Fs. 4. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 5. De-emphasis is available only in Single-Speed Mode. Parameter Min Typ Max Unit Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz Passband (Note 3) to -0.01 dB corner to -3 dB corner .454 .499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB StopBand 0.547 - - Fs StopBand Attenuation (Note 4) 102 - - dB Total Group Delay (Fs = Output Sample Rate) - 9.4/Fs - s Intra-channel Phase Deviation - - ±0.56/Fs s Inter-channel Phase Deviation - - 0 s De-emphasis Error (Note 5)(Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz Passband (Note 3) to -0.01 dB corner to -3 dB corner .430 .499 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB StopBand .583 - - Fs StopBand Attenuation (Note 4) 80 - - dB Total Group Delay (Fs = Output Sample Rate) - 4.6/Fs - s Intra-channel Phase Deviation - - ±0.03/Fs s Inter-channel Phase Deviation - - 0 s Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz Passband (Note 3) to -0.01 dB corner to -3 dB corner .105 .490 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 dB StopBand .635 - - Fs StopBand Attenuation (Note 4) 90 - - dB Total Group Delay (Fs = Output Sample Rate) - 4.7/Fs - s Intra-channel Phase Deviation - - ±0.01/Fs s Inter-channel Phase Deviation - - 0 s
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Figure 1. Serial Input Timing
POWER AND THERMAL CHARACTERISTICS Notes: 6. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are based on highest FS and highest MCLK. Variance between speed modes is small. 7. Power down mode is defined as RST pin = Low with all clock and data lines held static low. All digital inputs have a weak pull-do wn which is only present during reset. Opposing this pull-down will slightly increase the power-down current (pull-down is equivalent to a 50 kΩ resistor per pin). 8. Valid with the recommended capacitor values on VQ and V BIAS as shown in the typical connection dia- gram in Section 3. Parameters Symbol Min Typ Max Units High-Level Input Voltage V L = 3.3 V VL = 2.5 V VL = 1.5 V VIH VIH VIH 2.0 1.7 1.05 V V V Low-Level Input Voltage V L = 3.3 V VL = 2.5 V VL = 1.5 V VIL VIL VIL 0.8 0.7 0.38 V V V Input Leakage Current I in -- ± 1 0 µA Input Capacitance - 8 - pF Maximum MUTEC Drive Current - 2 - mA MUTEC High-Level Output Voltage V OH -V A _ H- V MUTEC Low-Level Output Voltage V OL -0- V Parameters Symbol Min Typ Max Units Power Supplies Power Supply Current normal operation, V A_H = 12 V (Note 6) VA_H = 9 V VA= 3.3 V VD= 3.3 V Interface current VL= 3.3 V power-down state, all supplies (Note 7) IA_H IA_H IA ID IL Ipd 0.02 380 0.09 mA mA mA mA mA µA Power Dissipation (all supplies) (Note 6) VA_H = 12 V normal operation power-down (Note 7) VA_H = 9 V normal operation power-down (Note 7) 121 158 122 mW mW mW mW Power Supply Rejection Ratio (Note 8) (1 kHz) (60 Hz) PSRR - dB dB
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- TYPICAL CONNECTION DIAGRAM
optional resistor is present. Figure 2. Typical Connection Diagram
4.1 Sample Rate Range/Ope rational Mode Detect
each mode are not supported. Table 1. CS4352 Auto-Detect
4.2 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. dio sample rates and the required MCLK frequency, are illustrated in Tables 2-4. to “Switching Specifications - Serial Audio Interface” on page 8 for the maximum allowed clock frequencies. Table 2. Single-Speed Mode Standard Frequencies Table 3. Double-Speed Mode Standard Frequencies Table 4. Quad-Speed Mode Standard Frequencies
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4.3 Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats, as illustrated in Table 5. nel Serial Audio Interface: A Tutorial, available at www.cirrus.com. Table 5. Digital Interface Format Figure 3. I²S, up to 24-Bit Data Figure 4. Right-Justified Data Figure 5. Left-Justified up to 24-Bit Data
00 I²S, up to 24-bit Data 0 3
01 Right-Justified, 24-bit Data 1 4
10 Left-Justified, up to 24-bit Data 2 5
11 Right-Justified, 16-bit Data 3 4
4.4 De-Emphasis Control
pin turns off the de-emphasis filter. Note: De-emphasis is only available in Single-Speed Mode.
4.5 Recommended Power-Up Sequence
- Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
main low and VBIAS will be connected to VA.
- Bring RST high. The device will remain in a low power state with VQ low and will initiate the power-up
Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.6 Grounding and Power Supply Arrangements
4.6.1 Capacitor Placement
pacitor should still be placed on each supply pin. Note: All decoupling capacitors should be referenced to analog ground. The CDB4352 evaluation board demonstrates the optimum layout and power supply arrangements. Figure 6. De-Emphasis Curve
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4.7 Popguard Transient Control
The CS4352 uses a novel technique to minimize the effects of output transients during power-up and power- down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended, single-supply converters. It is activat- ed inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.
4.7.1 Power-Up
When the device is initially po wered-up, the audio outputs, AOUT A and AOUTB, are clamped to GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quies- cent voltage. Approximat ely 10,000 LRCK cycles late r, the outputs reach V Q and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quies- cent voltage, minimizing audible power-up transients.
4.7.2 Power-Down
To prevent audible transients at power-down, the device must first enter its power-down state. When this occurs, audio output ceases, and the internal output buffers are disconnected from AOUTA and AOUTB. In their place, a soft-start current sink is substitute d that allows the DC-blocking capacitors to slowly dis- charge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on.
4.7.3 Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be- fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to GND. The time that the dev ice must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
4.8 Mute Control
The Mute Control pins go active during power-up initia lization, reset, muting, or if the MCLK to LRCK ratio is incorrect. These pins are intended to be used as control for external mute ci rcuits to prevent the clicks and pops that can occur in any single-ended, single-supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min- imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. Please see the CDB4352 data sheet for a suggested mu te circuit for dual-supply systems. Alternately, the FET muting circuit from the CS4351 data sheet may be used as well. This FET circuit must be placed in series after the RC filter; otherwise noise may occur during muting conditions. Further ESD protection will need to be taken into consideration for the FET used.
4.9 Initialization and Powe r-Down Sequence Diagram
USER: Apply Power Wait State USER: Apply MCLK, SCLK, and LRCK MCLK/LRCK Ratio Detection USER: Remove LRCK or MCLK USER: change MCLK/LRCK ratio Analog Output is Generated USER: Apply RST USER: Apply MCLK, SCLK, LRCK, and release RST Power-Down State VQ and outputs low VQ and outputs ramp down VQ and outputs ramp up
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- DIGITAL FILTER RESPON SE PLOTS
Figure 7. Single-Speed Stopband Rejection Figure 8. Single-Speed Transition Band Figure 9. Single-Speed Transition Band (detail) Figure 10. Single-Speed Passband Ripple Figure 11. Double-Speed Stopband Rejection Figure 12. Double-Speed Transition Band
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- PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17- 1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right ch annels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Intra-channel Phase Deviation The deviation from linear phase within a given channel. Inter-channel Phase Deviation The difference in phase between channels.
- PACKAGE DIMENSIONS 1. “D” and “E1” are reference datums and do not inclu ded mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/in trusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re- duce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters. Parameters Symbol Min Typ Max Units Package Thermal Resistance 20L TSSOP θJA -7 2- ° C / W a t t 20L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW
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- ORDERING INFORMATION 9. REVISION HISTORY Release Changes PP1 Lowered VA_H minimum specification. Updated Idle channel noise specification to A-wt. Updated AOUT current draw specification. Updated VIL for VL=1.5V. F1 Updated performance specifications and limits based on statistical data. Added Automotive grade specifications and ordering information. Updated Commercial grade idle channel noise specification. Lowered V IL maximum specifcation. Updated power supply current specification. Updated MCLK maximum specification. Product Description Package Pb-Free Grade Temp Range Container Order # CS4352 20-pin, 192 kHz Stereo DAC with 2 Vrms Line Out 20-pin TSSOP YES Commercial -40° to +85° C Rail Tape & Reel CS4352-CZZ CS4352-CZZR Automotive -40° to +105° C Rail Tape & Reel CS4352-DZZ CS4352-DZZR CDB4352 CS4352 Evaluation Board - - - - CDB4352 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRI TICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN S UCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.