CS4349-DZZ

CS4349 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

 Advanced Multi-bit Delta-Sigma Architecture  101 dB Dynamic Range  -91 dB THD+N at 5.0 V  -84 dB THD+N at 3.3 V  24-Bit Conversion  Supports Audio Sample Rates Up to 192 kHz  Low-Latency Digital Filtering  Single-Ended Analog Output Architecture  Automatic Sample-Rate Range Detection  Popguard® Technology for Control of Clicks and Pops – Hardware Popguard Disable for Fast Startups  Supports All Standard Serial Audio Formats Including Time-Division Multiplexed (TDM)  +3.3 V or +5.0 V Analog Supply  +1.5 V to +5.0 V Logic Supplies for Serial Port  +3.3 V to +5.0 V Control Port Interface Control Port Mode Features  SPI™ and I²C ® Modes  ATAPI Mixing  Mute Control for Individual Channels  Digital Volume Control with Soft Ramp – 127.5 dB Attenuation – 1/2 dB Step Size – Zero Crossing Click-Free Transitions PCM Serial Interface Serial Audio Input Right Channel Output Left Channel Output Reset

3.3 V to 5 V

ConfigurationHardware or I2C/ SPI Control Data

1.5 V to 5 V

Multibit ΔΣ Modulator Multibit ΔΣ Modulator Level Translator Level Translator Amp Filter Amp Filter Left and Right Mute Controls External Mute Control DAC DAC AUGUST '07 DS782F1 CS4349

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Description

The CS4349 is a complete stereo digital-to-analog system including digital interpolatio n, 5th-order multi-bit delta- sigma digital-to-analog conversion, digital de-emphasis, volu me control, channel mixing, and analog filtering. The advantages of this architecture include ideal linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, tolerance to clock jitter, and a minimal set of external components. The CS4349 supports all standard digital audio interface formats, including TDM. The CS4349 is available in a 24-pin TSSOP package in both Commercial (-40° to +85°C) and Automotive grades (-40° to +105°C). The CDB4349 Customer Demonstration b oard is also available for device evaluation and imple- mentation suggestions. Please refer to “Ordering Information” on page 40 for complete ordering information. These features are ideal for cost-sensitive, two-channel audio systems, including DVD players and recorders, set- top boxes, digital TVs, mini-component systems, musical instruments and automotive audio systems.

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1. PIN DESCRIPTION Pin Name # Pin Description VLC 5 Control Interface Power (Input) - Positive power for the hardware/software control interface VD_FILT 6 Regulator Voltage (Output) - Filter connection for internal voltage regulator GND 7, 19 Ground (Input) - Ground reference VLS 9 Serial Audio Interface Power (Input) - Positive power for the serial audio interface SCLK 10 Serial Clock (Input) - Serial bit-clock for the serial audio interface SDIN 11 Serial Audio Data Input (Input) - Input for two’s complement serial audio data LRCK 12 Left/Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line TSTO 13 Test Output (Output) - This pin needs to be floating and not connected to any trace or plane. TSTO 14 23 Test Output (Output) - These pins need to be floating and not connected to any trace or plane. AOUTA AOUTB Analog Outputs (Output) - The full-scale output level is specified in “DAC Analog Characteristics - Commercial (-CZZ)” on page 9. AMUTEC BMUTEC

21 Mute Control (Output) - Control signals for optional mute circuit

VBIAS 17 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC VA 18 Analog Power (Input) - Positive power supply for the analog section VQ 20 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage RST 24 Reset (Input) - When pulled low, device will power down and reset all internal registers to their default settings. DIF2(AD1/CDOUT) RST DEM(AD0/CS)T S T O DIF0(SDA/CDIN) AOUTB DIF1(SCL/CCLK) BMUTEC VLC VQ VD_FILT GND GND VA POPGUARD(TSTO) VBIAS VLS AMUTEC SCLK AOUTA SDIN TSTO LRCK TSTO 8 17 12 13 241

AD1/CDOUT 1 Address Bit 1 / Se rial Control Data Out (I/O) - Chip address bit 1 in I²C Mode or data output in SPI Mode AD0/CS 2 Address Bit 0 / Chip Select (Input) - Chip address bit 0 in I²C Mode or Chip Select in SPI Mode SDA/CDIN 3 Serial Control Data In ( I/O) - Input/Output for I²C data. Input for SPI data SCL/CCLK 4 Serial Control Port Clock (Input) - Serial clock for the control port interface TSTO 8 Test Output (Output) - This pin needs to be floating and not connected to any trace or plane. Stand-Alone Definitions DIF0 DIF1 DIF2 Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial Clock, and Serial Audio Data DEM 2 De-emphasis (Input) - Selects the standard 15 μs/50 μs digital de-emphasis filter response for 44.1 kHz sample rates POPGUARD

8 Popguard Disable (Input/Output) - At RST this pin is an input to disable PopGuard when pulled high;

Otherwise leave floating. After RST is released this pin becomes TSTO.

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1. CHARACTERISTICS A ND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to ground.(Note 1) Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Parameters Symbol Min Typ Max Units DC Power Supply Analog power VA 4.75 5.0 5.25 V VA 3.14 3.3 3.46 V Serial Audio Interface power VLS 1.35 3.3 5.25 V Control Interface power VLC 3.14 3.3 5.25 V Ambient Operating Temperature (Power Applied) Commercial (-CZZ) T A -40 - +85 °C Automotive (-DZZ) T A -40 - +105 °C Parameters Symbol Min Max Units DC Power Supply Analog power VA -0.3 6.0 V Serial Audio Interface power VLS -0.3 6.0 V Control Interface power VLC -0.3 6.0 V Input Current (Note 2) Iin -± 1 0 m A Digital Input Voltage Serial Audio Interface V IN-LS -0.3 VLS+ 0.4 V Control Interface V IN-LC -0.3 VLC+ 0.4 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C

DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ) Test conditions (unless otherwise specified): VLS = VLC = 3.3 V; TA = 25° C; input test signal is a 997 Hz sine wave; Valid with the recommended capacitor values on VFILT, VQ, and VBIAS and output circuit as shown in the typical con- nection diagram in Figure 10 and Figure 17; Fs = 48 kHz, 96 kHz, and 192 kHz; measurement bandwidth 10 Hz to 20 kHz. Notes: 3. One-half LSB of triangular PDF dither is added to data. See Figure 3, Figure 4, and Figure 5 for details on THD+N performance. 4. R L and CL represent the minimum resistance and maximum capacitance required for the CS4349’s in- ternal op-amp to remain stable. See Figure 1 and Figure 2 for more details. Parameter Symbol Min Typ Max Unit VA = 5.0 V Dynamic Range (Note 3) 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 3) 24-bit 0 dB -20 dB -60 dB 16-bit 0 dB -20 dB -60 dB THD+N -91 -78 -38 -90 -72 -32 -85 -35 dB dB dB dB dB dB VA = 3.3 V Dynamic Range (Note 3) 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 3) 24-bit 0 dB -2 dB -20 dB -60 dB 16-bit 0 dB -20 dB -60 dB THD+N -86 -91 -78 -38 -83 -72 -32 -79 -35 dB dB dB dB dB dB dB VA = 5.0 to 3.3 V Interchannel Isolation (1 kHz) - 100 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 0.25 dB Gain Drift - -400 - ppm/°C Analog Output Full Scale Output Voltage 2.70 2.78 2.97 Vpp Quiescent Voltage V Q -0 . 5 • V A- V D C Max DC Current draw from an AOUT pin I OUTmax -1 0- μA Max Current draw from VQ I Qmax - 100 - μA Max AC-Load Resistance (Note 4) RL -3- k Ω Max Load Capacitance (Note 4) CL - 100 - pF Output Impedance Z OUT - 100 - Ω

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DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ) Test conditions (unless otherwise specified): VLS = 1.35 V to 5.25 V, VLC = 3.14 V to 5.25 V, TA = -40° C to 85° C, input test signal is a 997 Hz sine wave; Valid with the recommended capacitor values on VFILT, VQ, and VBIAS and output circuit as shown in the typical connection diagram in Figure 10and Figure 17; Fs = 48 kHz, 96 kHz, and 192 kHz; mea- surement bandwidth 10 Hz to 20 kHz. Parameter Symbol Min Typ Max Unit VA = 4.75 V to 5.25 V Dynamic Range (Note 3) 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 3) 24-bit 0 dB -20 dB -60 dB 16-bit 0 dB -20 dB -60 dB THD+N -91 -78 -38 -90 -72 -32 -85 -32 dB dB dB dB dB dB VA = 3.14 V to 3.46 V Dynamic Range (Note 3) 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 3) 24-bit 0 dB -2 dB -20 dB -60 dB 16-bit 0 dB -20 dB -60 dB THD+N -81 -91 -78 -38 -83 -72 -32 -50 -31 dB dB dB dB dB dB VA = 3.14 to 5.25 V Interchannel Isolation (1 kHz) - 100 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 0.25 dB Gain Drift - -400 - ppm/°C Analog Output Full Scale Output Voltage 2.63 2.78 3.05 Vpp Quiescent Voltage V Q -0 . 5 • V A- V D C Max DC Current draw from an AOUT pin I OUTmax -1 0- μA Max Current draw from VQ I Qmax -1 0 0- μA Max AC-Load Resistance (Note 4) RL -3- k Ω Max Load Capacitance (Note 4) CL -1 0 0- p F Output Impedance Z OUT -1 0 0- Ω

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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by Fs. Amplitude vs. Frequency plots of this data are available in the “Filter Plots” on page 36. Notes: 5. Response is clock dependent. 6. The Measurement Bandwidth is from stopband to 3 Fs. 7. De-emphasis is available only in Single-Speed Mode ; Only 44.1 kHz De-emphasis is available in Stand- Alone Mode. 8. Slow Roll-off interpolation filter is only available in Control Port Mode. Parameter Min Typ Max Unit Fast Roll-Off Passband (Note 5) -0.01 dB corner (Single Speed) 0 - .454 Fs -0.1 dB corner (Double Speed) 0 - .42 Fs -0.2 dB corner (Quad Speed) 0 - .27 Fs -3 dB corner (All Speed Modes) 0 - .499 Fs Frequency Response 10 Hz to 20 kHz Single Speed -0.01 - +0.01 dB Double Speed, Quad Speed -0.02 - +0.02 dB StopBand 0.547 - - Fs Stop-Band Attenuation (Note 6) 102 - - dB Total Group Delay (Fs = Output Sample Rate) - 9.4/Fs - s Intra-channel Phase Deviation - - ±0.56/Fs s Inter-channel Phase Deviation - - 0 s De-emphasis Error (Note 7) Fs = 32 kHz - - ±0.23 dB (Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB Fs = 48 kHz -- ± 0 . 0 9 d B Slow Roll-Off (Note 8) Passband (Note 5) -0.01 dB corner (Single Speed) 0 - 0.417 Fs -0.1 dB corner (Double Speed) 0 - .37 Fs -0.2 dB corner (Quad Speed) 0 - .27 Fs -3 dB corner (All Speed Modes) 0 - .499 Fs Frequency Response 10 Hz to 20 kHz Single Speed -0.01 - +0.01 dB Double Speed, Quad Speed -0.02 - +0.02 dB StopBand .583 - - Fs Stop-Band Attenuation (Note 6) 64 - - dB Total Group Delay (Fs = Output Sample Rate) - 6.5/Fs - s Intra-channel Phase Deviation - - ±0.14/Fs s Inter-channel Phase Deviation - - 0 s De-emphasis Error (Note 7) Fs = 32 kHz - - ±0.23 dB (Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB Fs = 48 kHz -- ± 0 . 0 9 d B

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE Inputs: Logic 0 = GND; Logic 1 = VLS; CL =2 0p F . Parameters Symbol Min Max Units 3.14 V ≤ VA ≤ 5.25 V and 1.35 V ≤ VLS ≤ 5.25 V RMCK Output Frequency (Note ) 7.680 55.3 MHz RMCK Output Duty Cycle 45 55 % Input Sample Rate Single-Speed Mode 30 54 Double-Speed Mode Fs 60 108 kHz Quad-Speed Mode 120 216 LRCK Duty Cycle (Non-TDM Mode) 40 60 % SDIN Setup Time Before SCLK Rising Edge t ds 1- n s SDIN Hold Time After SCLK Rising Edge t dh 1- n s 4.75 V ≤ VA ≤ 5.25 V and 3.14 V ≤ VLS ≤ 5.25 V SCLK Frequency -5 5 . 3 M H z SCLK High Time t sckh 6- n s SCLK Low Time t sckl 6- n s Non-TDM Mode (refer to Figure 6) LRCK Edge to SCLK Rising Edge t lcks 11 - ns SCLK Rising Edge to LRCK Edge t lckd 1- n s TDM Mode (refer to Figure 7) LRCK High Time t lrckh 6- n s SCLK Rising to LRCK Falling Edge t fsh 3- n s LRCK Rising Edge to SCLK Rising Edge t fss 1- n s 3.14 V ≤ VA < 4.75 V or 1.35 V ≤ VLS < 3.14 V SCLK Frequency -2 7 . 7 M H z SCLK High Time t sckh 11 - ns SCLK Low Time t sckl 11 - ns Non-TDM Mode (refer to Figure 6) LRCK Edge to SCLK Rising Edge t lcks 16 - ns SCLK Rising Edge to LRCK Edge t lckd 1- n s TDM Mode (refer to Figure 7) LRCK High Time t lrckh 25 - ns SCLK Rising to LRCK Falling Edge t fsh 8- n s LRCK Rising Edge to SCLK Rising Edge t fss 1- n s

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Inputs: Logic 0 = GND; Logic 1 = VLC; CL =2 0p F . Note: 9. Data must be held for sufficient ti me to bridge the transition time, tfc, of SCL. Figure 6. Serial Port Timing, Non-TDM Mode Figure 7. Serial Port Timing, TDM Mode Figure 8. Control Port Timing - I²C Format

Inputs: Logic 0 = GND; Logic 1 = VLC; CL =2 0p F . Notes: 10. t spi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

1. Data must be held for sufficient time to bridge the transition time of CCLK.
2. CDOUT should not be sampled during this time.

Figure 9. Control Port Timing - SPI Mode

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POWER AND THERMAL CHARACTERISTICS Notes: 14. Current consumption increases with increasing Fs within the range of a speed mode. Variance between speed modes is small. Typ and Max values are based on Fs = 48 kHz. 15. I LC measured with no external loading on pin 2 (SDA). 16. Power-down mode is defined as RST pin = Low with all clock and data lines held static. 17. Valid with the recommended capacitor values on VF ILT, VQ, and VBIAS+ as shown in the typical con- nection diagram in Figure 10. Parameters Symbol Min Typ Max Units High-Level Input Voltage VLC or VLS = 5.0 V V IH 0.7•VL -- V VLC or VLS = 3.3 V VIH 2.0 - - V VLS = 2.5 V VIH 1.7 - - V VLS = 1.5 V VIH 0.75•VL -- V High-Level Input Voltage VLC or VLS = 5.0 V V IL -- 0 . 3 5 • V L V VLC or VLS = 3.3 V VIL -- 0 . 8 V VLS = 2.5 V VIL -- 0 . 7 V VLS = 1.5 V VIL -- 0 . 2 5 • V L V Input Leakage Current I in -- ± 1 0 μA Input Capacitance - 8 - pF Maximum MUTEC Drive Current - 2 - mA MUTEC High-Level Output Voltage V OH -V A- V MUTEC Low-Level Output Voltage V OL -0- V Parameters Symbol Min Typ Max Units Power Supply Current - Normal Operation (Note 14) VA= 5.0 V I A -2 8 3 4 m A VA= 3.3 V I A -2 4 2 9 m A VLS = VLC =5.0 V (Note 15) ILS -46 m A VLS = VLC =3.3 V (Note 15) ILS -25 m A VLS = VLC = 5.0 V (Note 15) ILC -1 4 1 8 m A VLS = VLC = 3.3 V (Note 15) ILC -1 4 1 8 m A Power Supply Current - Power-Down State (Note 16) VA, VLS, VLC I pd -1 0 0- μA Power Dissipation - Normal Operation (Note 14) VA = VLC= VLS = 5.0 V - 230 290 mW VA = VLC= VLS = 3.3 V - 132 171 mW Power Dissipation - Power-Down State (Note 16) VA = VLC= VLS = 5.0 V - 0.5 - mW VA = VLC= VLS = 3.3 V - 0.33 - mW Power Supply Rejection Ratio (Note 17) (1 kHz) PSRR - 60 - dB (60 Hz) PSRR - 50 - dB

1. TYPICAL CONNECTI ON DIAGRAM

24 RST

2 DEM(AD0/CS)

8 POPGUARD(TSTO)

Figure 10. Typical Connection Diagram

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4.1 Sample Rate Range and Oversampling Mode Detect

Stand-Alone Mode, the sample rate range will be according to Table 1.

4.1.1 Sample Rate Auto-Detect

Table 1. Sample rates outside the specified range for each mode are not supported when Auto-Detect is referred to in Section 8.2.3. Sample rates outside the specified range for each mode are not supported. In Stand-Alone Mode, it is not possible to disable auto-detect of sample rates.

4.2 System Clocking

Table 1. CS4349 Auto-Detect

4.3 Digital Interface Format

Stand-Alone Mode and Table 3 on page 29 for Control Port Mode. The 2-Channel Serial Audio Interface: A Tutorial, available at www.cirrus.com. Figure 11. Left-Justified up to 24-Bit Data Figure 12. I²S, up to 24-Bit Data Figure 13. Right-Justified Data

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4.3.1 Time-Division Multiplex (TDM) Mode

CS4349 devices and the corresponding DIF[2:0] pin or register-bit settings required for each CS4349. Figure 15 shows the TDM data format for each of the four CS4349 devices shown in Figure 14. Figure 14. TDM Mode Connection Diagram Figure 15. TDM Mode Timing

4.4 De-Emphasis

Note: De-emphasis is only available in Single-Speed Mode.

4.5 Mute Control

to prevent the clicks and pops that can occur in any single-ended single-supply system. to achieve idle-channel noise and signal-to-noise ratios which are only limited by the external mute circuit.

4.6 Recommended Power-Up Sequence

4.6.1 Stand-Alone Mode

1. Hold RST low until the power supplies and configuration pins are stable, and the serial and left/right
2. Bring RST high. The device will remain in a low power state with VQ low for approximately 512 LRCK
3. The device will then in itiate the power up sequence which lasts approximately 50 µs when the

Figure 16. De-Emphasis Curve

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4.6.2 Control Port Mode

1. Hold RST low until the power supply is stable and the left/right clock is fixed to the appropriate frequency, as discussed in Section 4.2. In this state, the control port is reset to its default settings, VQ will remain low, and VBIAS will be connected to VA. 2. Bring RST high. The device will remain in a low-power state with VQ low. 3. Perform a control port write to a valid register prior to the completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1. 4. Set the PDN bit to 0. This will initiate the powe r-up sequence, which lasts approximately 50 µs when the Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of power-up timing.

4.7 Popguard Transient Control

The CS4349 uses a novel technique to minimize the effects of output transients during power-up and power- down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors.

4.7.1 Power-Up

When the device is initially po wered-up, the audio outputs, AOUT A and AOUTB, are clamped to GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quies- cent voltage. Approximat ely 10,000 LRCK cycles late r, the outputs reach V Q and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quies- cent voltage, minimizing audible power-up transients.

4.7.2 Power-Down

To prevent audible transients at power-down, the device must first enter its power-down state. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB. In their place, a soft-start current sink is substitute d that allows the DC-blocking capacitors to slowly dis- charge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on.

4.7.3 Discharge Time

To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be- fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to GND. The time that the dev ice must remain in the power-down state is related to the value of the DC-blocking capacitance and the output load. For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.

4.8 Analog Output and Filtering

The CS4349 requires a simple single-ended passive output design as shown in Figure 17.

4.9 Grounding and Power Supply Arrangements

GND pins of the CS4349 should be connected to the analog ground plane. unwanted coupling into the DAC.

4.9.1 Capacitor Placement

pacitor should still be placed on each supply pin. Note: All decoupling capacitors should be referenced to GND. The CDB4349 evaluation board demonstrates the optimum layout and power supply arrangements. Figure 17. Passive Single-Ended Output Filter

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5.1 Serial Port Format Selection

put data as shown in Table 2 and Figure 15.

5.2 De-Emphasis Control

pin turns off the de-emphasis filter.

5.3 Popguard Transient Control

placing a 47 kΩ resistor between POPGUARD(TSTO) and VLS.

000 Left-Justified, up to 24-bit data 0 12

001 I²S, up to 24-bit data 1 11

010 Right-Justified, 16-bit data 2 13

011 Right-Justified, 24-bit data 3 13

100 TDM slot 0 4 15

101 TDM slot 1 5 15

110 TDM slot 2 6 15

111 TDM slot 3 7 15

Table 2. Digital Interface Format - Stand-Alone Mode

1. CONTROL PORT OPERATION The control port is used to load all the internal register settings (see ”Register Description” on page 29). The oper- ation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port can operate in I²C or SPI mode.

6.1 MAP Auto Increment

The device has a MAP (memory addre ss pointer) auto-increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for consecutive writes or reads. If INCR is set to 1, MAP will auto increment afte r each byte is read or written, a llowing block reads or writes of con- secutive registers.

6.2 I²C Mode

In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL (see Figure 18 for the clock to data relationship). There is no CS pin. AD1 and AD0 enable the user to alter the chip address (10010[AD1][AD0][R/W ]) and should be tied to VLC or GND as required before powering-up the device. SPI Mode will be selected if the device ever detects a high-to-low transition on the AD0/CS pin after power-up.

6.2.1 I²C Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifica- tions in ”Switching Characteristics - Control Port - I²C Format” on page 14. 1. Initiate a START condition to th e I²C bus followed by the address byte. The upper five bits must be 10010. The sixth and seventh bit must match the settings of the AD1 and AD0 pins respectively, and the eighth must be 0 (the eighth bit of the address byte is the R/W bit). 2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written. 3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP. 4. If the INCR bit (see Section 6.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5. If the INCR bit is set to 0 and further I²C writes to ot her registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus.

6.2.2 I²C Read

To read from the device, follow the procedure below while adhering to the control port switching specifi- cations in ”Switching Characteristics - Control Port - I²C Format” on page 14. 1. Initiate a START condition to the I²C bus followed by the address byte. The upper 5 bits must be 10010. The sixth and seventh bits must match the setting of the AD1 and AD0 pins, respectively, and the eighth must be 1. The eighth bit of the address byte is the R/W bit. 2. After transmitting an acknowledg e (ACK), the device will then transmit the contents of the register pointed to by the MAP. The MAP register will contain the address of the last register written to the

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1. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
2. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.

then initiate a STOP condition to the bus.

1. If the INCR bit is set to 0 and further I²C reads fr om other registers are desired, it is necessary to

are desired, initiate a STOP condition to the bus.

6.3 SPI Mode

6.3.1 SPI Write

tions in ”Switching Characteristics - Control Port - SPI Format” on page 15.

1. The address byte on the CDIN pin must then be 10011110 (R/W =0 ) .
2. Write to the memory address pointer, MAP. Th is byte points to the register to be written.
3. Write the desired data to the register pointed to by the MAP.
4. If the INCR bit (see Section 6.1) is set to 1, repeat the previous step until all the desired registers are

written, then bring CS high.

1. If the INCR bit is set to 0 and furt her SPI writes to other registers are desired, it is necessary to bring

Figure 18. Control Port Timing, I²C Mode

6.3.2 SPI Read

Characteristics - Control Port - SPI Format” on page 15.

1. The address byte on the CDIN pin must then be 10011111 (R/W =1 ) .
2. CDOUT pin will then output the data from the register pointed to by the MAP, which is set during the
3. If the INCR bit (see Section 6.1) is set to 1, keep CS low and continue providing clocks on CCLK to

read from multiple consecutive registers. Bring CS high when reading is complete.

1. If the INCR bit is set to 0 and further SPI reads from other registers are desired, it is necessary to bring

6.4 Memory Address Pointer (MAP)

6.4.1 INCR (Auto Map Increment Enable)

6.4.2 MAP (Memory Address Pointer)

Figure 19. Control Port Timing, SPI Mode

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1. REGISTER QU ICK REFERENCE Addr Function 7 6 5 4 3 2 1 0 1h Device and RevID DeviceID4 DeviceID3 DeviceID2 DeviceID1 DeviceID0 RevID2 RevID1 RevID0 default 1 1 1 1 - - - - 2h Mode Control Reserved DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0 d e f a u l t 000 0 0 000 3h Volume, Mixing, and Inversion Control VOLB=A INVERTA INVERTB Reserved ATAPI3 ATAPI2 ATAPI1 ATAPI0 d e f a u l t 000 0 1 001 4h Mute Control AMUTE Reserved MUTEC A=B MUTE_A MUTE_B Reserved Reserved Reserved d e f a u l t 100 0 0 001 5h Channel A Volume Control VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 d e f a u l t 000 0 0 000 6h Channel B Volume Control VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 d e f a u l t 000 0 0 000 7h Ramp and Filter Control SZC1 SZC0 RMP_UP RMP_DN Reserved FILT_SEL Reserved Reserved d e f a u l t 101 1 0 001 8h Misc. Control PDN Reserved FREEZE POPG_EN Reserved Reserved Reserved Reserved d e f a u l t 000 1 1 100

8.1 Device and Revision ID - Register 01h

8.2 Mode Control - Register 02h

8.2.1 Digital Interface Forma t (DIF[2:0]) Bits 6-4

These bits select the interface format for the serial audio input. Interface Format and the options are detailed in Figures 11-13.

000 Left-Justified, up to 24-bit data 0 (Default) 11

001 I²S, up to 24-bit data 1 12

Table 3. Digital Interface Formats

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8.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2

8.2.3 Functional Mode (FM[1:0]) Bits 1-0

Selects the required range of input sample rates or auto speed mode.

8.3 Volume Mixing and Inversi on Control - Register 03h

8.3.1 Channel A Volume = Channe l B Volume (VOLB=A) Bit 7

the B Channel Volume Control Bytes. Volume Control Bytes, and the B Channel Bytes are ignored.

8.3.2 Invert Signal Polari ty (INVERT_A) Bit 6

When set to 1, this bit inverts the signal polarity of channel A. When set to 0 (default), this function is disabled. This function is only available for Left Justified, Right Justified 16, and Right Justified 24 data formats. Figure 20. De-Emphasis Curve

8.3.3 Invert Signal Polari ty (INVERT_B) Bit 5

When set to 1, this bit inverts the signal polarity of channel B. When set to 0 (default), this function is disabled. This function is only available for Left Justified, Right Justified 16, and Right Justified 24 data formats.

8.3.4 ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0

Table 4 and Figure 21 for additional information.

0000 M U T E M U T E

0001 M U T E b R

0010 M U T E b L

Table 4. ATAPI Decode Figure 21. ATAPI Block Diagram

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8.4 Mute Control - Register 04h

8.4.1 Auto-Mute (AMUTE) Bit 7

retained, and the Mute Control pin will go active during the mute period.

8.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5

When set to 0 (default), the AMUTEC and BMUTEC pins operate independently. when the requirements for both AMUTEC and BMUTEC are valid.

8.4.3 Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3

ramping due to the soft and zero cross function. When set to 0 (default), this function is disabled.

8.5 Channel A & B Volume C ontrol - Register 05h & 06h

attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12.

8.6 Ramp and Filter Co ntrol - Register 07h

8.6.1 Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6

When Immediate Change is selected all level changes will take effect immediately in one step. ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Table 5. Example Digital Volume Settings

34 DS782F1

Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut- ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.

8.6.2 Soft Volume Ramp-Up Af ter Error (RMP_UP) Bit 5

Function: When set to 1 (default), an un-mute will be performed after executing a filter mode change, after LRCK is lost, and after changing the Functional Mode. This un-mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate un-mute is performed in these instances. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.

8.6.3 Soft Ramp-Down Be fore Filter Mode Change (RMP_DN) Bit 4

Function: When set to 1 (default), a mute w ill be performed prior to executing a filter mode change. This mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate mute is performed prior to executing a filter mode change. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.

8.6.4 Interpolation Filter Select (FILT_SEL) Bit 2

Function: When set to 0 (default), the Interpolation Filter has a fast roll-off. When set to 1, the Interpolation Filter has a slow roll-off. The specifications for each filter can be found in the ”Combined Interpolation & On-Chip Analog Filter Re- sponse” on page 12, and response plots can be found in Figures 24 through 29.

8.7 Misc. Control - Register 08h

8.7.1 Power Down (PDN) Bit 7

Function: When set to 1, the entire device enters a low-power state, and the contents of the control registers is re- tained. The power-down bit defaults to ‘0’ on power-up.

8.7.2 Freeze Controls (FREEZE) Bit 5

Function: When set to 1, this function allows modifications to be made to the registers without the changes taking effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. When set to 0 (default), register changes take effect immediately.

8.7.3 Popguard Enable (POPG_EN) Bit 4

Function: When set to 1, (default) the Device init iates a ramping function as outlined in Section 4.7 on page 22 . When set to 0, the outputs step to VQ upon release of PDN. 76543210 PDN Reserved FREEZE POPG_EN Rese rved Reserved Reserved Reserved 00011100

36 DS782F1

Figure 22. Stopband Rejection (fast), all Modes Figure 23. Stopband Rejection (slow), all Modes Figure 24. Single-Speed (fast) Passband Detail Fi gure 25. Single-Speed (slow) Passband Detail Figure 26. Double-Speed (fast) Passband Detail Figure 27. Double-Speed (slow) Passband Detail

Figure 28. Quad-Speed (fast) Passband Detail Fi gure 29. Quad-Speed (slow) Passband Detail

38 DS782F1

10.PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17- 1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right ch annels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. Intra-Channel Phase Deviation The deviation from linear phase within a given channel. Inter-Channel Phase Deviation The difference in phase between channels.

11.PACKAGE DIMENSIONS 1. D” and “E1” are reference datums and do not inclu ded mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/in trusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re- duce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. THERMAL CHARACTERISTICS INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters. Parameters Symbol Min Typ Max Units Package Thermal Resistance Single-Layer PCB Multi-Layer PCB θJA - 70 105 -° C / W a t t 24L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

40 DS782F1

12.ORDERING INFORMATION 13.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order# CS4349 192 kHz Stereo DAC with 1 Vrms Single Ended Output 24-TSSOP YES Commercial -40° to +85°C Rail CS4349-CZZ Tape and Reel CS4349-CZZR Automotive -40° to +105°C Rail CS4349-DZZ Tape and Reel CS4349-DZZR CDB4349 Evaluation Board for CS4349 - - - - CDB4349 Release Changes Updated “DAC Analog Characteristics - Commercial (-CZZ)” on page 9. Updated “DAC Analog Characteristics - Automotive (-DZZ)” on page 10. Added Figure 3, Figure 4, and Figure 5 on page 11. Updated “Switching Specifications - Serial Audio Interface” on page 13. Updated “Digital Characteristics” on page 16. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRI TICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN S UCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor SPI is a trademark of Motorola, Inc.