CS4341_05 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
!101 dB Dynamic Range !-91 dB THD+N !+3.0 V or +5.0 V Power Supply !Low Clock-Jitter Sensitivity !Filtered Line-Level Outputs !On-Chip Digital De-Emphasis for 32, 44.1 and 48 kHz !ATAPI Mixing !Digital Volume Control with Soft Ramp – 94 dB Attenuation – 1 dB Step Size – Zero Crossing Click-Free Transitions !Popguard® Technology for Control of Clicks and Pops !33 mW with 3.0 V Supply
Description
The CS4341 is a complete stereo digital-to-analog sys- tem including digital interpolation, fourth-order Delta- Sigma digital-to-analog conversion, digital de-emphasis and switched capacitor analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high tolerance to clock jitter. The CS4341 accepts data at audio sample rates from 4 kHz to 100 kHz, consumes very little power, and oper- ates over a wide power supply range. The features of the CS4341 are ideal for DVD players, CD players, set- top box and automotive systems.
ORDERING INFORMATION
CS4341-KS 16-pin SOIC, -10 to 70 °C CS4341-CZZ, Lead Free 16-pin TSSOP , -10 to 70 °C CDB4341 Evaluation Board I Volume ControlInterpolation Filter ∆Σ DAC Analog Filter Control Port Volume ControlInterpolation Filter Analog Filter Serial Port SCL/CCLK MUTEC AD0/CS AOUTA AOUTB RST LRCK SDATA MCLK SDA/CDIN ∆Σ DAC External Mute Control SCLK Mixer DECEMBER '05 DS298F5 CS4341
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4.6 Popguard
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- CHARACTERISTICS AND SPECIFICATIONS (Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at TA = 25°C.) SPECIFIED OPERATING CONDITIONS (All voltages with respect to AGND = 0 V.) ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Notes: 1. Any pin except supplies. Parameters Symbol Min Nom Max Units DC Power Supply Nominal 3.3 V Nominal 5.0 V VA VA 2.7 4.75 3.3 5.0 3.6 5.5 V V Specified Operating Temperature -KS/CZZ (Power Applied) TA -10 - +70 °C Parameters Symbol Min Max Units DC Power Supply VA -0.3 6.0 V Input Current (Note 1) Iin -± 1 0 m A Digital Input Voltage V IND -0.3 VA+0.4 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C
ANALOG CHARACTERISTICS (CS4341-KS/CZZ) (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL =1 0k Ω, CL = 10 pF (see Figure 1).) Parameter VA = 5.0 V VA = 3.0 V Min Typ Max Min Typ Max Unit Single-Speed Mode Fs = 48 kHz Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 2) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -91 -78 -38 -90 -72 -32 -86 -94 -74 -34 -91 -72 -32 -89 dB dB dB dB dB dB Double-Speed Mode Fs = 96 kHz Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 2) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -91 -78 -38 -90 -72 -32 -86 -94 -74 -34 -91 -72 -32 -89 dB dB dB dB dB dB
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Notes: 2. One-half LSB of triangular PDF dither is added to data. Figure 1. Output Test Load Figure 2. Maximum Loading
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteris- tics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) Notes: 4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 5. De-emphasis is only available in Single-Speed Mode. Parameter Min Typ Max Unit Single-Speed Mode - (4 kHz to 50 kHz sample rates) Passband to -0.05 dB corner to -3 dB corner 0.4535 0.4998 Fs Fs Frequency Response 10 Hz to 20 kHz -0.02 - +0.08 dB StopBand 0.5465 - - Fs StopBand Attenuation (Note 4) 50 - - dB Group Delay - 9/Fs - s Passband Group Delay Deviation 0 - 20 kHz - ±0.36/Fs - s De-emphasis Error (Relative to 1 kHz) Fs = 32 kHz (Note 5) Fs = 44.1 kHz Fs = 48 kHz +0.2/-0.1 +0.05/-0.14 +0/-0.22 dB dB dB Double-Speed Mode - (50 kHz to 100 kHz sample rates) Passband to -0.1 dB corner to -3 dB corner 0.4621 0.4982 Fs Fs Frequency Response 10 Hz to 20 kHz -0.06 - +0.2 dB StopBand 0.577 - - Fs StopBand Attenuation (Note 4) 55 - - dB Group Delay - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz ±1.39/Fs ±0.23/Fs s s
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Figure 3. Single-Speed Stopband Rejection Figure 4. Single-Speed Transition Band Figure 5. Single-Speed Transition Band (Detail) Figure 6. Single-Speed Passband Ripple Figure 7. Double-Speed Stopband Rejection Figure 8. Double-Speed Transition Band
Figure 9. Double-Speed Transition Band (Detail) Figure 10. Double-Speed Passband Ripple
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Figure 11. Serial Input Timing (External SCLK)
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Notes: 8. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
- See “Rise Time for Control Port Clock” on page 21 for a recommended circuit to meet rise time
Figure 14. Control Port Timing - I²C Mode
Notes: 10. t spi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
- Data must be held for sufficient time to bridge the transition time of CCLK.
Figure 15. Control Port Timing - SPI Mode
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DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.) Notes: 13. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 14. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 15. Valid with the recommended capacitor values on FILT + and VQ as shown in Figure 16. Increasing the capacitance will also increase the PSRR. DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.) DIGITAL INTERFACE SPECIFICATIONS (AGND = 0 V; all voltages with respect to AGND.) Parameters Symbol Min Typ Max Units Normal Operation (Note 13) Power Supply Current VA = 5.0 V VA = 3.0 V IA IA mA mA Power Dissipation VA = 5.0 V VA = 3.0 V mW mW Power-down Mode (Note 14) Power Supply Current VA = 5.0 V VA = 3.0 V IA - µA µA Power Dissipation VA = 5.0 V VA = 3.0 V 0.3 0.09 mW mW All Modes of Operation Power Supply Rejection Ratio (Note 15) 1 kHz 60 Hz PSRR - dB dB VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink 0.45•VA 250 0.01 V kΩ mA Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink VA 250 0.01 V kΩ mA MUTEC Low-Level Output Voltage - 0 - V MUTEC High-Level Output Voltage - VA - V Maximum MUTEC Drive Current - 3 - mA Parameters Symbol Min Typ Max Units Input Leakage Current I in -- ± 1 0 µA Input Capacitance - 8 - pF Parameters Symbol Min Max Units 3.3 V Logic (3.0 V to 3.6 V DC Supply) High-Level Input Voltage V IH 2.0 - V Low-Level Input Voltage V IL -0 . 8 V 5.0 V Logic (4.75 V to 5.25 V DC Supply) High-Level Input Voltage V IH 2.0 - V Low-Level Input Voltage V IL -0 . 8 V
- PIN DESCRIPTION Pin Name # Pin Description RST 1 Reset (Input) - Powers down device and resets registers to their default settings. SDATA 2 Serial Audio Data (Input) - Input for two’s complement serial audio data. SCLK 3 Serial Clock (Input) -Serial clock for the serial audio interface. LRCK 4 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. MCLK 5 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. SCL/CCLK 6 Serial Control Port Clock (Input) - Serial clock for the control port interface. SDA/CDIN 7 Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Input for SPI data. AD0/CS 8 Address Bit / Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select the chip in SPI mode. FILT+ 9 Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling circuits. VQ 10 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. REF_GND 11 Reference Ground (Input) - Ground reference for the internal sampling circuits. AOUTB AOUTA Analog Outputs (Output) - The full-scale analog output level is specified in the Analog Characteristics table. AGND 13 Analog Ground (Input) VA 14 Power (Input) - Positive power for the analog, digital, and serial audio interface sections. MUTEC 16 Mute Control (Output) - Control signal for an optional mute circuit. 152 143 134 161 116 107 125 RST MUTEC SDATA AOUTA SCLK VA LRCK AGND MCLK AOUTB SCL/CCLK REF_GND SDA/CDIN VQ AD0/CS FILT+
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- TYPICAL CONNECTION DIAGRAM
Figure 16. Typical Connection Diagram
4.1 Sample Rate Range/Operational Mode
ratio (see section 4.2). Sample rates outside the specified range for each mode are not supported.
4.2 System Clocking
and the required MCLK frequency, are illustrated in Tables 2 and 3. *Requires MCLKDIV bit = 1 in the MCLK Control (address 00h) register.
4.2.1 Internal Serial Clock Mode
the MCLK/LRCK ratio and the Digital Interface Format selection (see Table 4). Table 1. CS4341 Speed Modes Table 2. Single-Speed Mode Standard Frequencies Table 3. Double-Speed Mode Standard Frequencies
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4.2.2 External Serial Clock Mode
4.3 Digital Interface Format
required relationship between LRCK, SCLK and SDATA, see Figures 17 through 19.
24 Bits
16 Bits
Table 4. Internal SCLK/LRCK Ratio Figure 17. CS4341 Formats 0-1 - I²S up to 24-Bit Data Figure 18. CS4341 Format 2 - Left Justified up to 24-Bit Data Figure 19. CS4341 Formats 3-6 - Right Justified
4.4 De-Emphasis
32, 44.1 or 48 kHz de-emphasis filter. Figure 20 shows the de-emphasis curve for F s equal to 44.1 kHz. rate, Fs. Please see section 6.2.3 for the desired de-emphasis control. De-emphasis is only available in Single-Speed Mode.
4.5 Power-Up Sequence
settings and VQ will remain low. 2) Bring RST high. The device will remain in a low power state with VQ low. 3) Load the desired register settings while keeping the PDN bit set to 1.
4.6 Popguard ® Transient Control
from choosing the appropriate DC-blocking capacitors.
4.6.1 Power-Up
itors to charge to the quiescent voltage, minimizing the power-up transient. Figure 20. De-Emphasis Curve
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4.6.2 Power-Down
To prevent transients at power-down, the device must first enter its power-down state by enabling RST or setting the PDN bit. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their pl ace, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.
4.6.3 Discharge Time
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the mi nimum power-down time will be approximately 0.4 seconds.
4.7 Mute Control
The Mute Control pin goes high during power-up initialization, reset, muting (see section 6.2.1 and 6.5.1) or if the MCLK to LRCK ratio is incorrect. This pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single-ended single supply system. Use of the Mute Control function is not mandator y but recommended for designs requiring the absolute minimum in extraneous clicks and pop s. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4341 data sheet for a suggested mute circuit.
4.8 Grounding and Powe r Supply Arrangements
As with any high resolution converter, the CS4341 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. Figure 16 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane. Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupl ing capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and should also be located on the same layer as the DAC. The CDB4341 evaluation board demonstrates the optimum layout and power supply arrangements.
4.9 Control Port Interface
The control port is used to load all the internal register settings (see section 6). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interfer- ence problems, the control port pins should remain static if no operation is required. The control port operates in one of two modes: I²C or SPI. Notes: MCLK must be applied during all I²C communication.
4.9.1 Rise Time for Control Port Clock
operation of the I²C bus as pin 6 is an input only.
4.9.2 Memory Address Pointer (MAP)
The device has a MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP.
4.9.3 I²C Mode
Figure 21. I²C Buffer Example
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Specifications in section 6. be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. 2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written. registers are written, then initiate a STOP condition to the bus. initiate a STOP condition to the bus. propriate register through the MAP. last register written to the MAP. vice. After all the desired registers are read, initiate a STOP condition to the bus. sired, initiate a STOP condition to the bus.
001000 AD0 W
Figure 22. I²C Write
4.9.4 SPI Mode
and data is clocked in on the rising edge of CCLK. Specifications in section 1. 2) The address byte on the CDIN pin must then be 00100000. 3) Write to the memory address pointer, MAP. This byte points to the register to be written. 4) Write the desired data to the register pointed to by the MAP. registers are desired, bring CS high. Figure 23. I²C Read Figure 24. Control Port Timing, SPI Mode
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- REGISTER QUICK REFERENCE Addr Function 7 6 5 4 3 2 1 0 0h MCLK Control Reserved Reserved Reserved Reserved Reserved Reserved MCLKDIV Reserved DEFAULT 00000000 1h Mode Control 2 AMUTE DIF2 DIF1 DIF0 DEM1 DEM1 POR PDN DEFAULT 10000011 2h Transition and Mixing Control A = B SCZ1 SCZ0 ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 DEFAULT 00000000 3h Channel A Volume Control MUTEA VOLA6 VOLA5 VOLA4 VOLA3 VOLA2 VOLA1 VOLA0 DEFAULT 00000000 4h Channel B Volume Control MUTEB VOLB6 VOLB5 VOLB4 VOLB3 VOLB2 VOLB1 VOLB0 DEFAULT 00000000
- REGISTER DESCRIPTION NOTE: All registers are read/write in I²C Mode and write only in SPI mode, unless otherwise stated.
6.1 MCLK CONTROL (ADDRESS 00H)
6.1.1 MCLK DIVIDE-BY-2 (MCLKDIV) BIT 1
Default = 0 0 - Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.
6.2 MODE CONTROL (ADDRESS 01H)
6.2.1 AUTO-MUTE (AMUTE) BIT 7
Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. The muting function is affected, similar to vol- ume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. 76543210 Reserved Reserved Reserved Reserved Reserved Reserved MCLKDIV Reserved 00000000 76543210 AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 POR PDN 10000011
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6.2.2 DIGITAL INTERFACE FORMAT (DIF) BIT 4-6
Digital Interface Format and the options are detailed in Figures 17 through 19.
6.2.3 DE-EMPHASIS CONTROL (DEM) BIT 2-3
NOTE: De-emphasis is only available in Single-Speed Mode.
6.2.4 POPGUARD
6.2.5 POWER DOWN (PDN) BIT 0
control registers are retained in this mode. Table 5. Digital Interface Format
6.3 TRANSITION AND MIXING CONTROL (ADDRESS 02H)
6.3.1 CHANNEL A VOLUME = CHANNEL B VOLUME (A = B) BIT 7
Default = 0 0 - Disabled 1 - Enabled Function: The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Vol- ume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are de- termined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled.
6.3.2 SOFT RAMP AND ZERO CROSS CONTROL (SZCX)
Default = 10 00 - Immediate Changes 01 - Changes On Zero Crossings 10 - Soft Ramped Changes 11 - Soft Ramped Changes On Zero Crossings Function: Immediate Changes When Immediate Changes is selected all level changes will take effect immediately in one step. Changes On Zero Crossings Changes on Zero Crossings dictates that signal level changes, either by attenuation changes or mut- ing, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independent- ly monitored and implemented for each channel. Soft Ramped Changes Soft Ramped Changes allows level changes, both muting and attenuation, to be implemented by in- crementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8 left/right clock periods. Soft Ramped Changes on Zero Crossings Soft Ramped Changes On Zero Crossings dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. 76543210 A = B SZC1 SZC0 ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 01001001
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6.3.3 ATAPI CHANNEL MIXING AND MUTING (ATAPI) BIT 0-4
Table 6 and Figure 25 for additional information.
00000 M U T E M U T E
00001 M U T E b R
00010 M U T E b L
00011 M U T E b [ ( L + R ) / 2 ]
10000 M U T E M U T E
10001 M U T E b R
10010 M U T E b L
10011 M U T E b L / 2
Table 6. ATAPI Decode
6.4 CHANNEL A VOLUME CO NTROL (ADDRESS 03H)
Same as CHANNEL B Volume Control.
6.5 CHANNEL B VOLUME CO NTROL (ADDRESS 04H)
6.5.1 MUTE (MUTE) BIT 7
ing the mute period if the Mute function is enabled for both channels. Figure 25. ATAPI Block Diagram
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6.5.2 VOLUME (VOLx) BIT 0-6
The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -90 dB. settings less than - 94 dB are equivalent to enabling the Mute bit. Table 7. Example Digital Volume Settings
- PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C.
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- PACKAGE DIMENSIONS
8.1 SOIC
DIM MIN NOM MAX MIN NOM MAX JEDEC #: MS-012 Controling Dimension is Millimeters e 16L SOIC (150 MIL BODY) PACKAGE DRAWING D HE b A c L ∝SEATING PLANE
8.2 TSSOP
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion /intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. 9. PACKAGE THERMAL RESISTANCE INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters Package Symbol Min Typ Max Units SOIC (for multi-layer boards) TSSOP (for multi-layer boards) θJA θJA °C/Watt °C/Watt 16L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW
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10.REFERENCES CDB4341 Evaluation Board Datasheet 11.REVISION HISTORY Revision Changes F4 Added lead-free packaging information F5 Corrected Dimension e in TSSOP Package Drawing value for NOM Millimeters from 0.065 to 0.65 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRI TICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN S UCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.