CS4340_05 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
!101 dB Dynamic Range !-91 dB THD+N !+3.0 V or +5.0 V Power Supply !Low Clock Jitter Sensitivity !Filtered Line-level Outputs !On-chip Digital De-emphasis for 32, 44.1 and 48 kHz !33 mW with 3V Supply !Popguard® Technology for Control of Clicks and Pops !Lead-free Packaging Available
Description
The CS4340 is a complete stereo digital-to-analog system including digital interpolation, fourth-order delta-sigma dig- ital-to-analog conversion, digital de-emphasis and switched capacitor analog filtering. The advantages of this architecture include: ideal differential linearity, no distor- tion mechanisms due to resistor matching errors, no linearity drift over time and temperature and a high toler- ance to clock jitter. The CS4340 accepts data at audio sample rates from 4 kHz to 100 kHz, consumes very little power, and oper- ates over a wide power supply range. The features of the CS4340 are ideal for DVD players, CD players, set-top box and automotive systems.
ORDERING INFORMATION
CS4340-DSZ 16-pin SOIC, Lead Free, -40 to 85 °C CS4340-KS 16-pin SOIC -10 to 70 °C CS4340-KSZ 16-pin SOIC, Lead Free, -10 to 70 °C CS4340-CZZ 16-pin TSSOP, Lead Free, -10 to 70 °C CDB4340 Evaluation Board I ∆Σ DAC Analog Filter Serial Input Interface Interpolation Filter Analog Filter MUTEC AOUTL AOUTR RST LRCK SDATA MCLK External Mute Control SCLK/DEM1 DAC Interpolation Filter De-emphasis DEM0 DIF0 DIF1 JULY '05 DS297F3
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4.6 Popguard
Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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- CHARACTERISTICS AND SPECIFICATIONS (Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at TA = 25°C.) SPECIFIED OPERATING CONDITIONS (All voltages with respect to AGND = 0 V.) ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Notes: 1. Any pin except supplies. Parameters Symbol Min Nom Max Units DC Power Supply Nominal 3.3V Nominal 5.0V VA VA 2.7 4.75 3.3 5.0 3.6 5.5 V V Specified Operating Temperature -KS/KSZ/CZZ (Power Applied) -DSZ TA TA -10 -40 -+ 7 0 +85 Parameters Symbol Min Max Units DC Power Supply VA -0.3 6.0 V Input Current (Note 1) Iin -± 1 0 m A Digital Input Voltage V IND -0.3 VA+0.4 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C
ANALOG CHARACTERISTICS (CS4340-KS/KSZ/CZZ) (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL =1 0k Ω, CL = 10 pF (see Figure 1).) Parameter VA = 5.0 V VA = 3.0 V Min Typ Max Min Typ Max Unit Single-Speed Mode Fs = 48 kHz Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 2) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -91 -78 -38 -90 -72 -32 -86 -94 -74 -34 -91 -72 -32 -89 dB dB dB dB dB dB Double-Speed Mode Fs = 96 kHz Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 2) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -91 -78 -38 -90 -72 -32 -86 -94 -74 -34 -91 -72 -32 -89 dB dB dB dB dB dB
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Notes: 2. One-half LSB of triangular PDF dither is added to data. Figure 1. Output Test Load Figure 2. Maximum Loading
ANALOG CHARACTERISTICS (CS4340-DSZ) (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL =1 0k Ω, CL = 10 pF (see Figure 1).) Parameter VA = 5.0 V VA = 3.0 V Min Typ Max Min Typ Max Unit Single-Speed Mode Fs = 48 kHz Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 2) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -91 -78 -38 -90 -72 -32 -86 -94 -74 -34 -91 -72 -32 -87 dB dB dB dB dB dB Double-Speed Mode Fs = 96 kHz Dynamic Range (Note 2) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted 101 dB dB dB dB Total Harmonic Distortion + Noise (Note 2) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -91 -78 -38 -90 -72 -32 -86 -94 -74 -34 -91 -72 -32 -87 dB dB dB dB dB dB
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ANALOG CHARACTERISTICS (CS4340-DSZ) (Continued) COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) Notes: 4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs. 5. De-emphasis is only available in Single-Speed Mode. Parameters Symbol Min Typ Max Units Dynamic Performance for All Modes Interchannel Isolation (1 kHz) - 102 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 - dB Gain Drift - ±100 - ppm/°C Analog Output Characteristics and Specifications Full Scale Output Voltage 0.6•VA 0.7•VA 0.8•VA Vpp Output Impedance - 100 - Ω Minimum AC-Load Resistance (Note 3) RL -3-k Ω Maximum Load Capacitance (Note 3) CL - 100 - pF Parameter Min Typ Max Unit Single-Speed Mode - (4 kHz to 50 kHz sample rates) Passband to -0.05 dB corner to -3 dB corner 0.4535 0.4998 Fs Fs Frequency Response 10 Hz to 20 kHz -0.02 - +0.08 dB StopBand 0.5465 - - Fs StopBand Attenuation (Note 4) 50 - - dB Group Delay - 9/Fs - s Passband Group Delay Deviation 0 - 20 kHz - ±0.36/Fs - s De-emphasis Error (Relative to 1 kHz) Fs = 44.1 kHz (Note 5) -- + 0 . 0 5 / - 0 . 1 4 d B Double-Speed Mode - (50 kHz to 100 kHz sample rates) Passband to -0.1 dB corner to -3 dB corner 0.4621 0.4982 Fs Fs Frequency Response 10 Hz to 20 kHz -0.06 - +0.2 dB StopBand 0.577 - - Fs StopBand Attenuation (Note 4) 55 - - dB Group Delay - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz ±1.39/Fs ±0.23/Fs s s
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Figure 9. Double-Speed Transition Band (Detail) Figure 10. Double-Speed Passband Ripple
Figure 11. Serial Input Timing (External SCLK)
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Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period.
- See section 4.2.1 for derived internal frequencies.
Figure 12. Internal Serial Mode Input Timing *The SCLK pulses shown are internal to the CS4340. Figure 13. Internal Serial Clock Generation
DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.) Notes: 8. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 9. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 10. Valid with the recommended capacitor values on FILT + and VQ as shown in Figure 14. Increasing the capacitance will also increase the PSRR. DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.) DIGITAL INTERFACE SPECIFICATIONS (AGND = 0 V; all voltages with respect to AGND.) Parameters Symbol Min Typ Max Units Normal Operation (Note 8) Power Supply Current VA = 5.0 V VA = 3.0 V IA IA mA mA Power Dissipation VA = 5.0 V VA = 3.0 V mW mW Power-down Mode (Note 9) Power Supply Current VA = 5.0 V VA = 3.0 V IA - µA µA Power Dissipation VA = 5.0 V VA = 3.0 V 0.3 0.09 mW mW All Modes of Operation Power Supply Rejection Ratio (Note 10) 1 kHz 60 Hz PSRR - dB dB VQ Nominal Voltage Output Impedance Maximum allowable DC current source/sink 0.45•VA 250 0.01 V kΩ mA Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink VA 250 0.01 V kΩ mA MUTEC Low-Level Output Voltage - 0 - V MUTEC High-Level Output Voltage - VA - V Maximum MUTEC Drive Current - 3 - mA Parameters Symbol Min Typ Max Units Input Leakage Current I in -- ± 1 0 µA Input Capacitance - 8 - pF Parameters Symbol Min Max Units 3.3 V Logic (3.0 V to 3.6 V DC Supply) High-Level Input Voltage V IH 2.0 - V Low-Level Input Voltage V IL -0 . 8 V 5.0 V Logic (4.75 V to 5.25 V DC Supply) High-Level Input Voltage V IH 2.0 - V Low-Level Input Voltage V IL -0 . 8 V
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- PIN DESCRIPTION Pin Name # Pin Description RST 1 Reset (Input) - Powers down device. SDATA 2 Serial Audio Data (Input) - Input for two’s complement serial audio data. SCLK 3 Serial Clock (Input) -Serial clock for the serial audio interface. DEM1 DEM0 De-emphasis Control (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for 44.1 kHz sample rate. LRCK 4 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. MCLK 5 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. DIF1 DIF0 Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial Clock and Serial Audio Data. FILT+ 9 Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling cir- cuits. VQ 10 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. REF_GND 11 Reference Ground (Input) - Ground reference for the internal sampling circuits. AOUTR AOUTL Analog Outputs (Output) - The full scale analog output level is specified in the Analog Charac- teristics table. AGND 13 Analog Ground (Input) VA 14 Power (Input) - Positive power for the analog, digital and serial audio interface sections. MUTEC 16 Mute Control (Output) - Control signal for an optional mute circuit. 152 143 134 161 116 107 125 RST MUTEC SDATA AOUTL SCLK/DEM1 VA LRCK AGND MCLK AOUTR DIF1 REF_GND DIF0 VQ DEM0 FILT+
- TYPICAL CONNECTION DIAGRAM
Figure 14. Typical Connection Diagram
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4.1 Sample Rate Range/Operational Mode
section 4.2). Sample rates outside the specified range for each mode are not supported.
4.2 System Clocking
4.2.1 Internal Serial Clock Mode
Interface Format selection (see Table 4). Table 1. CS4340 Speed Modes Table 2. Single-Speed Mode Standard Frequencies Table 3. Double-Speed Mode Standard Frequencies
SCLK mode is recommended for system clocking applications.
4.2.2 External Serial Clock Mode
to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
4.3 Digital Interface Format
SDIN, see Figures 15 through 18.
24 Bits
16 Bits
Table 4. Internal SCLK/LRCK Ratio
00 I2S, up to 24-bit data 01 5
01 Left Justified, up to 24-bit data 11 6
10 Right Justified, 24-bit Data 21 7
11 Right Justified, 16-bit Data 31 8
Table 5. Digital Interface Format - DIF1 and DIF0 Figure 15. CS4340 Format 0 - I2S up to 24-Bit Data Figure 16. CS4340 Format 1 - Left Justified up to 24-Bit Data
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4.4 De-Emphasis
The device includes on-chip digital de-emphasis. Figure 19 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. 44.1, or 48 kHz de-emphasis filter. Please see Table 6 for the desired de-emphasis control. Figure 17. CS4340 Format 2 - Right Justified, 24-Bit Data
00 Disabled 0 Disabled
Table 6. De-Emphasis Control Figure 19. De-Emphasis Curve
4.5 Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supply and configuration pins are stable, and the clocks are locked to the appropriate frequencies discussed in section 4.2. It is also recommended that reset be enabled if the analog supply drops below the minimum specified operati ng voltage to prevent power glitch related issues.
4.6 Popguard ® Transient Control
The CS4340 uses Popguard® technology to minimize the effects of output transients during power-up and power- down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended si ngle-supply converters. It is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside from choosing the appropriate DC- blocking capacitors.
4.6.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Fol- lowing a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent volt- age. Approximately 10,000 LRCK cycles later, the outputs reach V Q and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, min- imizing the power-up transient.
4.6.2 Power-down
To prevent transients at power-down, the device must first enter its power-down state by enabling RST. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly dis- charge. Once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on.
4.6.3 Discharge Time
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking capacitors have fully discharged before turning on the power or exiting the power-down state. If not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power- down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
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4.7 Mute Control
The Mute Control pin goes high during power-up initialization, reset, or if the MCLK to LRCK ratio is incorrect. The pin will also go high following the reception of 8192 consecutive audio samples of static 0 or -1 on both the left and right channels. A single sample of non -zero data on either channel will cause th e Mute Control pin to go low. This pin is intended to be used as a control for an external mu te circuit to prevent the clicks and pops that can occur in any single-ended single supply system. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. See the CDB4340 data sheet for a suggested mute circuit.
4.8 Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4340 requires careful attention to power supply and grounding arrange- ments if its potential performance is to be realized. Figure 14 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & AGND should be connected to the analog ground plane. Decoupling capacitors should be as close to the DAC as possible, with the lo w value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same layer as the DAC. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors , particularly the 0.1 µF, mu st be positioned to mini- mize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and should also be located on the same layer as the DAC. The CDB4340 evaluation bo ard demonstrates the optimum layout and power supply arrangements.
- PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C.
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- REFERENCES 1) CDB4340 Evaluation Board Datasheet
- PACKAGE DIMENSIONS
7.1 SOIC
DIM MIN NOM MAX MIN NOM MAX JEDEC #: MS-012 Controling Dimension is Millimeters e 16L SOIC (150 MIL BODY) PACKAGE DRAWING D HE b A c L ∝SEATING PLANE
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7.2 TSSOP
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion /intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters 16L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW
- PACKAGE THERMAL RESISTANCE Package Symbol Min Typ Max Units SOIC (for multi-layer boards) TSSOP (for multi-layer boards) θJA θJA °C/Watt °C/Watt