CS4334 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
lComplete Stereo DAC System: Interpolation, D/A, Output Analog Filtering l24-Bit Conversion l96 dB Dynamic Range l-88 dB THD+N lLow Clock Jitter Sensitivity lSingle +5 V Power Supply lFiltered Line Level Outputs lOn-Chip Digital De-emphasis lPopgaurd® Technology lFunctionally Compatible with CS4330/31/33
Description
The CS4334 family members are complete, stereo digi- tal-to-analog output systems including interpolation, 1-bit D/A conversion and output analog filtering in an 8-pin package. The CS4334/5/6/7/8/9 support all major audio data interface formats, and the individual devices differ only in the supported interface format. The CS4334 family is based on delta-sigma modulation, where the modulator output controls the reference volt- age input to an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The CS4334 family contains on-chip digital de-empha- sis, operates from a single +5V power supply, and requires minimal support circuitry. These features are ideal for set-top boxes, DVD players, SVCD players, and A/V receivers.
ORDERING INFORMATION
I LRCK 3 SDATA 1 DEM/SCLK MCLK VA AOUTL AOUTR Serial Input Interface Interpolator Interpolator De-emphasis Modulator DS Modulator DAC DAC Voltage Reference Analog Low-Pass Filter Analog Low-Pass Filter AGND DS SEP ‘99 DS248PP3
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Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com.
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- CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS (TA = 25 °C; Logic "1" = VA = 5 V; Logic "0" = AGND; Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified. Test load R L = 10 kW , C L = 10 pF (see Figure 1)) Notes: 1. One-half LSB of triangular PDF dither added to data. Parameter Base-rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit Dynamic Performance for CS4334/5/6/7/8/9-KS Specified Temperature Range T A -10 - 70 -10 - 70 °C Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -88 -73 -33 -86 -71 -31 -83 -68 -28 -81 -66 -26 -88 -70 -30 -86 -68 -28 -83 -65 -25 -81 -63 -23 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 94 - - 95 - dB Dynamic Performance for CS4334/5/6/7/8/9-BS Specified Temperature Range T A -40 - 85 -40 - 85 °C Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -88 -73 -33 -86 -71 -31 -82 -65 -25 -70 -63 -23 -88 -70 -30 -86 -68 -28 -82 -62 -22 -80 -60 -20 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 94 - - 95 - dB
ANALOG CHARACTERISTICS (Continued) Notes: 2. Filter response is not tested but is guaranteed by design. 3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 17-24) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 4. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. 5. De-emphasis is not available in High-Rate Mode. 6. Refer to Figure 2. Parameter Base-rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit Combined Digital and On-chip Analog Filter Response (Note 2) Passband (Note 3) to -0.05 dB corner to -0.1 dB corner to -3 dB corner .4780 .4996 .4650 .4982 Fs Fs Fs Frequency Response 10 Hz to 20 kHz -.01 - +.08 -.05 - +.2 dB Passband Ripple - - ±.08 - - ±.2 dB StopBand .5465 - - .5770 - - Fs StopBand Attenuation (Note 4) 50 - - 55 - - dB Group Delay tgd - 9/Fs - - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz - ±0.36/Fs - - ±1.39/Fs ±0.23/Fs s s De-emphasis Error Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz +1.5/+0 +.05/-.25 -.2/-.4 (Note 5) dB dB dB Parameters Symbol Min Typ Max Units dc Accuracy Interchannel Gain Mismatch - 0.1 0.4 dB Gain Error - ±5 - % Gain Drift - 100 - ppm/°C Analog Output Full Scale Output Voltage 3.25 3.5 3.75 Vpp Quiescent Voltage V Q -2 . 2-V D C Max AC-Load Resistance (Note 6) R L -3-k W Max Load Capacitance (Note 6) C L - 100 - pF
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Notes: 7. Refer to Figure 3. Max Power Dissipation is measured at VA=5.5V. Figure 1. Output Test Load Figure 2. Maximum Loading Figure 3. Power vs. Sample Rate
DIGITAL CHARACTERISTICS (TA = 25°C; VA = 4.75V - 5.5V) Notes: 8. Iin for CS433X LRCK is ±20mA max. ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.) Parameters Symbol Min Typ Max Units High-Level Input Voltage V IH 2.0 - - V Low-Level Input Voltage V IL -- 0 . 8 V Input Leakage Current (Note 8) I in -- ± 1 0 mA Input Capacitance - 8 - pF Parameters Symbol Min Max Units DC Power Supply VA -0.3 6.0 V Input Current, Any Pin Except Supplies I in -± 1 0 m A Digital Input Voltage V IND -0.3 VA+0.4 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Parameters Symbol Min Typ Max Units DC Power Supply VA 4.75 5.0 5.5 V
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SWITCHING CHARACTERISTICS (TA = -40 to 85°C; VA = 4.75V - 5.5V; Inputs: Logic 0 = 0V, Logic 1 = VA, CL = 20pF) Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% +/- 1/2 MCLK Period. 10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK ratio. (See figures 10-15) Parameters Symbol Min Typ Max Units Input Sample Rate Fs 2 - 100 kHz MCLK Pulse Width High MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width Low MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 256 or 128 31 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 256 or 128 31 - 1000 ns External SCLK Mode LRCK Duty Cycle (External SCLK only) 40 50 60 % SCLK Pulse Width Low t sclkl 20 - - ns SCLK Pulse Width High t sclkh 20 - - ns SCLK Period MCLK / LRCK = 512, 256 or 384 t sclkw --n s SCLK Period MCLK / LRCK = 128 or 192 t sclkw --n s SCLK rising to LRCK edge delay t slrd 20 - - ns SCLK rising to LRCK edge setup time t slrs 20 - - ns SDATA valid to SCLK rising setup time t sdlrs 20 - - ns SCLK rising to SDATA hold time t sdh 20 - - ns Internal SCLK Mode LRCK Duty Cycle (Internal SCLK only) (Note 9) - 50 - % SCLK Period (Note 10) t sclkw --n s SCLK rising to LRCK edge t sclkr -- ms SDATA valid to SCLK rising setup time t sdlrs --n s SCLK rising to SDATA hold time MCLK / LRCK = 512, 256 or 128 tsdh --n s SCLK rising to SDATA hold time MCLK / LRCK = 384 or 192 tsdh --n s tsclkw
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- TYPICAL CONNECTION DIAGRAM
8 Left Audio
Figure 7. Recommended Connection Diagram
provides a high tolerance to clock jitter. lows input sample rates up to 100 kHz.
3.1 Digital Interpolation Filter
3.2 Delta-Sigma Modulator
128 Fs in BRM (or 64 Fs in HRM).
3.3 Switched-Capacitor DAC
3.4 Analog Low-Pass Filter
and attenuate out-of-band noise. Figure 8. System Block Diagram
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4.1 Master Clock
MCLK, LRCK and SCLK must be synchronous. Table 1. Common Clock Frequencies
4.2 Serial Clock
modes. Refer to Figures 10-15 for data formats.
4.2.1 External Serial Clock Mode
4.2.2 Internal Serial Clock Mode
an external serial clock synchronized with LRCK. function. Refer to Figures 10 - 16 for details. clock interference from an external SCLK.
4.3 De-Emphasis
with changes in sample rate, Fs. only in the internal serial clock mode.
4.4 Initialization and Power-Down
ters the Power-Down State upon initial power-up.
4.5 Output Transient Control
4.6 Grounding and Power Supply
age as possible with the smallest capacitor closest.
4.7 Analog Output and Filtering
Figure 9. De-Emphasis Curve (Fs = 44.1kHz)
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Figure 10. CS4334 Data Format (I2S) Figure 11. CS4335 Data Format Figure 12. CS4336 Data Format
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Figure 16. CS4334/5/6/7/8/9 Initialization and Power-Down Sequence
4.8 Overall Base-Rate Frequency Response
Figure 17. Stopband Rejection Figure 18. Transition Band Figure 19. Transition Band Figure 20. Passband Ripple
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4.9 Overall High-Rate Frequency Response
Figure 21. Stopband Rejection Figure 22. Transition Band Figure 23. Transition Band Figure 24. Passband Ripple
4.10 Base Rate Mode Performance Plots
Figure 25. 0 dBFS FFT (BRM) Figure 26. -60 dBFS FFT (BRM) Figure 27. Idle Channel Noise FFT (BRM) Figure 28. Twin Tone IMD FFT (BRM) Figure 29. THD+N vs. Amplitude (BRM) Figure 30. THD+N vs. Frequency (BRM)
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4.11 High Rate Mode Performance Plots
Figure 31. 0 dBFS FFT (HRM) Figure 32. -60 dBFS FFT (HRM) Figure 33. Idle Channel Noise FFT (HRM) Figure 34. Twin Tone IMD FFT (HRM) Figure 35. THD+N vs. Amplitude (HRM) Figure 36. THD+N vs. Frequency (HRM)
- PIN DESCRIPTIONS No. Pin Name I/O Pin Function and Description 1S D A T A I Serial Audio Data Input - two’s complement MSB-first serial data is input on this pin. The data is clocked into the CS4334/5/6/7/8/9 via internal or external SCLK, and the channel is determined by LRCK. 2D E M / S C L K I De-Emphasis/External Serial Clock Input - used for de-emphasis filter control or exter- nal serial clock input.
3 LRCK I Left/Right Clock - determines which channel is currently being input on the Audio Serial
Data Input pin, SDATA. 4M C L K I Master Clock - frequency must be 256x, 384x, or 512x the input sample rate in BRM and either 128x or 192x the input sample rate in HRM. 5A O U T RO Analog Right Channel Output - typically 3.5 Vp-p for a full-scale input signal. 6A G N DI Analog Ground - analog ground reference is 0V. 7V A I Analog Power - analog power supply is nominally +5V. 8A O U T LO Analog Left Channel Output - typically 3.5 Vp-p for a full-scale input signal. SERIAL DATA INPUT SDATA AOUTL ANALOG LEFT CHANNEL OUTPUT DE-EMPHASIS / SCLK DEM/SCLK VA ANALOG POWER LEFT / RIGHT CLOCK LRCK AGND ANALOG GROUND MASTER CLOCK MCLK AOUTR ANALOG RIGHT CHANNEL OUTPUT
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- PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N)- The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range - The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for each channel at the converter' s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels. Gain Error - The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift - The change in gain value with temperature. Units in ppm/ °C. 7. REFERENCES 1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Con- vention of the Audio Engineering Society, Oc- tober 1992. 2) CDB4334/5/6/7/8/9 Evaluation Board Datasheet
- ORDERING INFORMATION: 9. FUNCTIONAL COMPATIBILITY CS4330-KS Þ CS4339-KS CS4331-KS Þ CS4334-KS CS4333-KS Þ CS4338-KS CS4330-BS Þ CS4339-BS CS4331-BS Þ CS4334-BS CS4333-BS Þ CS4338-BS Model Temperature Package Serial Interface CS4334-KS -10 to +70 °C 8-pin Plastic SOIC 16 to 24-bit, I2S CS4335-KS -10 to +70 °C 8-pin Plastic SOIC 16 to 24-bit, left justified CS4336-KS -10 to +70 °C 8-pin Plastic SOIC 24-bit, right justified CS4337-KS -10 to +70 °C 8-pin Plastic SOIC 20-bit, right justified CS4338-KS -10 to +70 °C 8-pin Plastic SOIC 16-bit, right justified CS4339-KS -10 to +70 °C 8-pin Plastic SOIC 18-bit, right justified, 32 F s Internal SCLK mode CS4334-BS -40 to +85 °C 8-pin Plastic SOIC 16 to 24-bit, I2S CS4335-BS -40 to +85 °C 8-pin Plastic SOIC 16 to 24-bit, left justified CS4336-BS -40 to +85 °C 8-pin Plastic SOIC 24-bit, right justified CS4337-BS -40 to +85 °C 8-pin Plastic SOIC 20-bit, right justified CS4338-BS -40 to +85 °C 8-pin Plastic SOIC 16-bit, right justified CS4339-BS -40 to +85 °C 8-pin Plastic SOIC 18-bit, right justified, 32 F s Internal SCLK mode
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- PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 µ 0° 8° 0° 8° JEDEC # : MS-012 8L SOIC (150 MIL BODY) PACKAGE DRAWING D HE e b A c L µSEATING PLANE
- Notes •