CS4334_04 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
/circle6 Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering /circle6 24-Bit Conversion /circle6 96 dB Dynamic Range /circle6 -88 dB THD+N /circle6 Low Clock Jitter Sensitivity /circle6 Single +5 V Power Supply /circle6 Filtered Line Level Outputs /circle6 On-Chip Digital De-emphasis /circle6 Popguard® Technology /circle6 Functionally Compatible with CS4330/31/33
Description
The CS4334 family members are complete, stereo digital-to-analog output systems including interpolation, 1-bit D/A conversion and output analog filtering in an 8-pin package. The CS4334/5/8/9 support all major audio data interface formats, and the individual devices differ only in the supported interface format. The CS4334 family is based on Delta-Sigma modulation, where the modulator output controls the reference volt- age input to an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The CS4334 family contains on-chip digital de-empha- sis, operates from a single +5V power supply, and requires minimal support circuitry. These features are ideal for set-top boxes, DVD players, SVCD players, and A/V receivers.
ORDERING INFORMATION
I LRCK 3 SDATA 1 DEM/SCLK MCLK VA AOUTL AOUTR Serial Input Interface Interpolator Interpolator De-emphasis Modulator Modulator DAC DAC Voltage Reference Analog Low-Pass Filter Analog Low-Pass Filter AGND JUL ‘04 DS248F3
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Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reli able. However, the infor- mation is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and co mplete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringe- ment, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, tra de secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for re sale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHO- RIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COM- PONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICA- TIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. I²C is a registered trademark of Philips Semiconductor. Purchase of I²C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies con- veys a license under the Phillips I²C Patent Rights to use those components in a standard I²C system. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard® are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com/
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- CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T A = 25°C.) SPECIFIED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.) ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameters Symbol Min Nom Max Units DC Power Supply VA 4.75 5.0 5.5 V Ambient Operating Temperature (Power Applied) -KS -BS/-DS T A -10 -40 +70 +85 Parameters Symbol Min Max Units DC Power Supply VA -0.3 6.0 V Input Current, Any Pin Except Supplies I in -± 1 0 m A Digital Input Voltage V IND -0.3 VA+0.4 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C
ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load R L = 10 kΩ, CL = 10 pF (see Figure 1). Fs for Base-Rate Mode = 48 kHz, Measurement Bandwidth 10 Hz to 20 kHz, unless other- wise specified; Fs for High-Rate Mode = 96 kHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise spec- ified.) Note: 1. One-half LSB of triangular PDF dither added to data. Parameter Base-Rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit Dynamic Performance for CS4334/5/8/9-KS Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -88 -73 -33 -86 -71 -31 -83 -68 -28 -81 -66 -26 -88 -70 -30 -86 -68 -28 -83 -65 -25 -81 -63 -23 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 94 - - 95 - dB Dynamic Performance for CS4334/5/8/9-BS/-DS Dynamic Range (Note 1) 18 to 24-Bit unweighted A-Weighted 16-Bit unweighted A-Weighted dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -88 -73 -33 -86 -71 -31 -82 -65 -25 -70 -63 -23 -88 -70 -30 -86 -68 -28 -82 -62 -22 -80 -60 -20 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 94 - - 95 - dB
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ANALOG CHARACTERISTICS (Continued) Notes: 2. Filter response is not tested but is guaranteed by design. 3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 15-22) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 4. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. 5. De-emphasis is not available in High-Rate Mode. 6. Refer to Figure 2. Parameter Base-Rate Mode High-Rate Mode Symbol Min Typ Max Min Typ Max Unit Combined Digital and On-chip Analog Filter Response (Note 2) Passband (Note 3) to -0.05 dB corner to -0.1 dB corner to -3 dB corner .4780 .4996 .4650 .4982 Fs Fs Fs Frequency Response 10 Hz to 20 kHz -.01 - +.08 -.05 - +.2 dB Passband Ripple - - ±.08 - - ±.2 dB StopBand .5465 - - .5770 - - Fs StopBand Attenuation (Note 4) 50 - - 55 - - dB Group Delay tgd - 9/Fs - - 4/Fs - s Passband Group Delay Deviation 0 - 40 kHz 0 - 20 kHz - ±0.36/Fs - - ±1.39/Fs ±0.23/Fs s s De-emphasis Error Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz +1.5/+0 +.05/-.25 -.2/-.4 (Note 5) dB dB dB Parameters Symbol Min Typ Max Units DC Accuracy Interchannel Gain Mismatch - 0.1 0.4 dB Gain Error - ±5 - % Gain Drift - 100 - ppm/°C Analog Output Full Scale Output Voltage 3.25 3.5 3.75 Vpp Quiescent Voltage V Q -2 . 2-V D C Max AC-Load Resistance (Note 6) R L -3-k Ω Max Load Capacitance (Note 6) C L - 100 - pF
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DIGITAL INPUT CHARACTERISTICS 8. I in for CS433X LRCK is ±20 µA max. Parameters Symbol Min Typ Max Units High-Level Input Voltage V IH 2.0 - - V Low-Level Input Voltage V IL -- 0 . 8 V Input Leakage Current (Note 8) I in -- ± 1 0 µA Input Capacitance - 8 - pF
Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% +/− 1/2 MCLK Period. 10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK ratio. (See figures 10-13) Parameters Symbol Min Typ Max Units Input Sample Rate Fs 2 - 100 kHz MCLK Pulse Width High MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width Low MCLK/LRCK = 512 10 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 384 or 192 21 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 256 or 128 31 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 256 or 128 31 - 1000 ns External SCLK Mode LRCK Duty Cycle (External SCLK only) 40 50 60 % SCLK Pulse Width Low t sclkl 20 - - ns SCLK Pulse Width High t sclkh 20 - - ns SCLK Period Base-Rate Mode MCLK / LRCK = 512, 256 or 384 tsclkw --n s SCLK Period High-Rate Mode MCLK / LRCK = 128 or 192 tsclkw --n s SCLK rising to LRCK edge delay t slrd 20 - - ns SCLK rising to LRCK edge setup time t slrs 20 - - ns SDATA valid to SCLK rising setup time t sdlrs 20 - - ns SCLK rising to SDATA hold time t sdh 20 - - ns Internal SCLK Mode LRCK Duty Cycle (Internal SCLK only) (Note 9) - 50 - % SCLK Period (Note 10) t sclkw --n s SCLK rising to LRCK edge t sclkr -- µs SDATA valid to SCLK rising setup time t sdlrs --n s SCLK rising to SDATA hold time MCLK / LRCK = 512, 256 or 128 tsdh --n s SCLK rising to SDATA hold time MCLK / LRCK = 384 or 192 tsdh --n s tsclkw
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Figure 4. External Serial Mode Input Timing Figure 5. Internal Serial Mode Input Timing
- The SCLK pulses shown are internal to the CS4334/5/8/9.
Figure 6. Internal Serial Clock Generation
- The SCLK pulses shown are internal to the CS4334/5/8/9.
- TYPICAL CONNECTION DIAGRAM
8 Left Audio
Figure 7. Recommended Connection Diagram
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provides a high tolerance to clock jitter. lows input sample rates up to 100 kHz.
3.1 Digital Interpolation Filter
3.2 Delta-Sigma Modulator
128 Fs in BRM (or 64 Fs in HRM).
3.3 Switched-Capacitor DAC
3.4 Analog Low-Pass Filter
and attenuate out-of-band noise. Figure 8. System Block Diagram
4.1 Master Clock
MCLK, LRCK and SCLK must be synchronous. Table 1. Common Clock Frequencies
4.2 Serial Clock
modes. Refer to Figures 10-13 for data formats.
4.2.1 External Serial Clock Mode
4.2.2 Internal Serial Clock Mode
an external serial clock synchronized with LRCK. function. Refer to Figures 10 - 14 for details.
4.3 De-Emphasis
with changes in sample rate, Fs. only in the internal serial clock mode. Figure 9. De-Emphasis Curve (Fs = 44.1kHz)
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4.4 Initialization and Power-Down
The Initialization and Power-Down sequence flow chart is shown in Figure 14. The CS4334 family en- ters the Power-Down State upon initial power-up. The interpolation filters and delta-sigma modula- tors are reset, and the internal voltage reference, one-bit digital-to-analog converters and switched- capacitor low-pass filters are powered down. The device will remain in the Power-Down mode until MCLK and LRCK are present. Once MCLK and LRCK are detected, MCLK occurrences are count- ed over one LRCK period to determine the MCLK/LRCK frequency ratio. Power is then ap- plied to the internal voltage reference. Finally, pow- er is applied to the D/A converters and switched- capacitor filters, and the analog outputs will ramp to the quiescent voltage, VQ.
4.5 Output Transient Control
The CS4334 family uses Popguard® technology to minimize the effects of output transients during power-up and power-down. This technique elimi- nates the audio transients commonly produced by single-ended single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make best use of this feature, it is necessary to un- derstand its operation. When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. After a short delay of approximately 1000 sample periods, each output begins to ramp to- wards its quiescent voltage, V Q. Approximately 10,000 sample cycles later, the outputs reach V Q and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to V Q, effectively blocking the quiescent DC voltage. To prevent transients at power-down, the device must first enter its power-down state. This is ac- complished by removing MCLK or LRCK. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. A soft-start current sink is substituted in place of AOUTL and AOUTR which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on. To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning off the power or exiting the power- down state. If full discharge does not occur, a tran- sient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. For exam- ple, with a 3.3µF capacitor, the time that the device must remain in the power-down state will be ap- proximately 0.4 seconds.
4.6 Grounding and Power Supply
As with any high resolution converter, the CS4334 family requires careful attention to power supply and grounding arrangements to optimize perfor- mance. Figure 7 shows the recommended power ar- rangement with VA connected to a clean +5V supply. For best performance, decoupling capaci- tors should be located as close to the device pack- age as possible with the smallest capacitor closest.
4.7 Analog Output and Filtering
The analog filter present in the CS4334 family is a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 15 - 22.
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Figure 13. CS4339 Data Format
Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence
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4.8 Overall Base-Rate Frequency Response
Figure 15. Stopband Rejection Figure 16. Transition Band Figure 17. Transition Band Figure 18. Passband Ripple
4.9 Overall High-Rate Frequency Response
Figure 19. Stopband Rejection Figure 20. Transition Band Figure 21. Transition Band Figure 22. Passband Ripple
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4.10 Base Rate Mode Performance Plots
Figure 23. 0 dBFS FFT (BRM) Figure 24. -60 dBFS FFT (BRM) Figure 25. Idle Channel Noise FFT (BRM) Figure 26. Twin Tone IMD FFT (BRM) Figure 27. THD+N vs. Amplitude (BRM) Figure 28. THD+N vs. Frequency (BRM)
4.11 High Rate Mode Performance Plots
Figure 29. 0 dBFS FFT (HRM) Figure 30. -60 dBFS FFT (HRM) Figure 31. Idle Channel Noise FFT (HRM) Figure 32. Twin Tone IMD FFT (HRM) Figure 33. THD+N vs. Amplitude (HRM) Figure 34. THD+N vs. Frequency (HRM)
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- PIN DESCRIPTIONS No. Pin Name I/O Pin Function and Description 1S D A T AI Serial Audio Data Input - two’s complement MSB-first serial data is input on this pin. The data is clocked into the CS4334/5/8/9 via internal or external SCLK, and the channel is determined by LRCK. 2D E M / S C L KI De-Emphasis/External Serial Clock Input - used for de-emphasis filter control or exter- nal serial clock input. 3L R C K I Left/Right Clock - determines which channel is currently being input on the Audio Serial Data Input pin, SDATA. 4M C L K I Master Clock - frequency must be 256x, 384x, or 512x the input sample rate in BRM and either 128x or 192x the input sample rate in HRM. 5A O U T RO Analog Right Channel Output - typically 3.5 Vp-p for a full-scale input signal. 6A G N DI Analog Ground - analog ground reference is 0V. 7V A I Analog Power - analog power supply is nominally +5V. 8A O U T L O Analog Left Channel Output - typically 3.5 Vp-p for a full-scale input signal. SERIAL DATA INPUT SDATA AOUTL ANALOG LEFT CHANNEL OUTPUT DE-EMPHASIS / SCLK DEM/SCLK VA ANALOG POWER LEFT / RIGHT CLOCK LRCK AGND ANALOG GROUND MASTER CLOCK MCLK AOUTR ANALOG RIGHT CHANNEL OUTPUT
- PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N)- The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Dynamic Range - The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise le vel and do not effect the measurement. This measurement technique has been accepted by th e Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels. Gain Error - The deviation from the nominal full s cale analog output for a full scale digital input. Gain Drift - The change in gain value with temperature. Units in ppm/ °C. 7. REFERENCES 1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4334/5/8/9 Evaluation Board Datasheet
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F3 July 2004 Removed CS4335-BS and CS4339-BS from the Ordering Information section. Table 2. Revision History
- PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.020 0.33 0.51 C 0.007 0.010 0.19 0.25 D 0.189 0.197 4.80 5.00 E 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 H 0.228 0.244 5.80 6.20 L 0.016 0.050 0.40 1.27 ∝ 0° 8° 0° 8° JEDEC # : MS-012 8L SOIC (150 MIL BODY) PACKAGE DRAWING D HE e b A c L ∝SEATING PLANE