CS4331-BS

CS4330 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

/c108 Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering /c108 18-Bit Resolution /c108 94 dB Dynamic Range /c108 0.003% THD /c108 Low Clock Jitter Sensitivity /c108 Single +3 V or +5 V Power Supply /c108 Filtered Line Level Outputs Linear Phase Filtering /c108 On-Chip Digital De-emphasis

Description

The CS4330, CS4331 and CS4333 are complete, stereo digital-to-analog output systems including interpolation, 1-bit D/A conversion and output analog filtering in an 8- pin package. These devices differ in the serial interface format used to input audio data. The CS4330, CS4331 and CS4333 are based on delta- sigma modulation, where the modulator output controls the reference voltage input to an ultra-linear analog low- pass filter. This architecture allows for infinite adjustment of sample rate between 2 kHz and 50 kHz while main- taining linear phase response simply by changing the master clock frequency. The CS4330, CS4331 and CS4333 contain on-chip dig- ital de-emphasis, operate from a single +3 V or +5 V power supply, and consume only 60mW of power with a 3 V power supply. These features make them ideal for portable CD players and other portable playback systems.

ORDERING INFORMATION

See page 21. I LRCK 3 SDATA 1 DEM/SCLK MCLK VA+ AOUTL AOUTR Serial Input Interface Interpolator Interpolator De-emphasis Delta-Sigma Modulator Delta-Sigma Modulator DAC DAC Voltage Reference Analog Low-Pass Filter Analog Low-Pass Filter AGND MAY ‘97 DS136F1

ANALOG CHARACTERISTICS (TA = 25°C; Logic "1" = VA+; Logic "0" = AGND; MCLK = 12.288 MHz; Full-Scale Output Sine Wave, 991 Hz; Input Sample Rate = 48 kHz; Input Data = 18 Bits; SCLK = 3.072 MHz; Measurement Bandwidth is 10 Hz to 20 kHz, unweighted; unless otherwise specified. Resistive load = 20 kΩ , capaci- tive load = 100 pF) CS4330/31/33-KS VA +5V CS4330/31/33-KS VA +3V CS4330/31/33-BS VA +5V only Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Units Specified Temperature Range T A -10 to 70 -10 to 70 -40 to +85 °C Resolution - - 18 - - 18 - - 18 Bits Dynamic Performance Dynamic Range (A-weighted) 90 94 - - 89 - 88 94 - dB Total Harmonic Distortion + Noise 0 dB Output, -20 dB Output, -60 dB Output THD+N -86 -72 -32 -81 -68 -28 -85 -67 -27 -80 -88 -86 -72 -32 -79 -66 -26 dB dB dB Deviation From Linear Phase (Note 1) - ± 0.5 -- ± 0.5 -- ± 0.5 -d e g Passband: to 0.05 dB corner (Note 2,3) 0 to 21.77 0 to 21.77 0 to 21.77 kHz Frequency Response 10 Hz to 20 kHz(Note 1) - ± 0.1 -- ± 0.1 -- ± 0.1 -d B Passband Ripple (Note 3) - - ±0.05 -- ±0.05 -- ±0.05 dB StopBand (Notes 2,3) 26.23 26.23 26.23 - - kHz StopBand Attenuation (Note 4) 60 - - 60 - - 60 - - dB Group Delay (Fs = Input Sample Rate) tgd - 16 / Fs - - 16 / Fs - - 16 / Fs - s Interchannel Isolation (1 kHz) - 90 - - 90 - - 90 - dB dc Accuracy Interchannel Gain Mismatch - 0.1 - - 0.1 - - 0.1 - dB Gain Drift - 250 - - 250 - - 250 - ppm/°C Analog Output Output Common Mode Voltage - 2.3 - - 1.3 - - 2.3 - VDC Minimum Resistive Load - 10 - - 10 - - 20 - kΩ Maximum Capacitive Load - 100 - - 100 - - 100 - pF Power Supplies Power Supply Current: normal operation power-down IA+ IA+ mA µA Power Dissipation normal operation power-down 140 0.3 160 0.06 140 0.3 160 mW mW Power Supply Rejection Ratio (1 kHz) PSRR - 50 - - 50 - - 50 - dB Notes: 1. Combined digital and analog filter characteristics. 2. The passband and stopband edges scale with frequency. For input sample rates, Fs, other than 48 kHz, the 0.05 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs. 3. Digital filter characteristics. 4. Measurement Bandwidth is 10 Hz to Fs (kHz) CS4330, CS4331, CS4333

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SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 2.7V - 5.5V; Inputs: Logic 0 = 0V, Logic 1 = VA+, CL = 20 pF) Switching characteristics are guaranteed by characterization. Parameter Symbol Min Typ Max Units Input Sample Rate Fs 2 - 50 kHz LRCK Duty Cycle (External SCLK only) (Note 5) 30 50 70 % MCLK Pulse Width High MCLK / LRCK = 512 10 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 512 15 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 384 21 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 384 21 - 1000 ns MCLK Pulse Width High MCLK / LRCK = 256 35 - 1000 ns MCLK Pulse Width Low MCLK / LRCK = 256 39 - 1000 ns External SCLK Mode SCLK Pulse Width Low t sclkl 20 - - ns SCLK Pulse Width High t sclkh 20 - - ns SCLK Period t sclkw (128)Fs -- n s SCLK rising to LRCK edge delay t slrd 20 - - ns SCLK rising to LRCK edge setup time t slrs 20 - - ns SDATA valid to SCLK rising setup time t sdlrs 20 - - ns SCLK rising to SDATA hold time t sdh 20 - - ns Internal SCLK Mode SCLK Period (Note 6) t sclkw SCLK -- n s SCLK rising to LRCK edge t sclkr - tsclkw 2 - µs SDATA valid to SCLK rising setup time t sdlrs SCLK rising to SDATA hold time MCLK / LRCK = 256 or 512 tsdh (512)Fs +15 -- n s SCLK rising to SDATA hold time MCLK / LRCK = 384 t sdh (384)Fs +15 -- n s Notes: 5. In Internal SCLK Mode, the Duty Cycle must be 50% ±1/2 MCLK Period. 6. The SCLK / LRCK ratio may be either 32, 48, or 64. CS4330, CS4331, CS4333 DS136F1 3

External Serial Mode Input Timing SDATA LRCK MCLK *INTERNAL SCLK 1 N N Internal Serial Clock Generation * The SCLK pulses shown are internal to the CS4330/31/33. N equals MCLK divided by SCLK SDATA **INTERNAL SCLK *LRCK sclkwt sdlrst sdht sclkrt Internal Serial Mode Input Timing * LRCK for CS4331 ** The SCLK pulses shown are internal to the CS4330/31/33. CS4330, CS4331, CS4333

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RECOMMENDED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground) Parameter Symbol Min Typ Max Units DC Power Supply: (3V mode) VA+ 2.7 3.0 4.0 V (5V mode) VA+ 4.75 5.0 5.5 V DIGITAL CHARACTERISTICS (TA = 25 °C; VA+ = 2.7V - 5.5V) Parameter Symbol Min Typ Max Units High-Level Input Voltage (VA+ = 5.5V) V IH 2.4 - - V (VA+ = 5.0V) V IH 2.0 - - V Low-Level Input Voltage V IL -- 0 . 8 V Input Leakage Current (Note 7) I in -- ±10 µA Notes: 7. Iin for CS4331 LRCK is ± 20 µA max. ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.) Parameter Symbol Min Max Units DC Power Supply: VA+ -0.3 6.0 V Input Current, Any Pin Except Supplies I in - ±10 mA Digital Input Voltage V IND -0.3 (VA+)+0.4 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. CS4330, CS4331, CS4333 DS136F1 5

Figure 1. Recommended Connection Diagram

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vides a high tolerance to clock jitter. variations in resistor values. quirements rather than anti-image filtering. nal at multiples of 128× the input sample rate. generations of 1-bit digital-to-analog converters. Figure 2. System Block Diagram

tion filter and the delta-sigma modulator. exit this mode. Refer to Figure 8. function. Refer to Figure 8. proportionally with changes in sample rate, Fs. only in the internal serial clock mode. Table 1. Common Clock Frequencies

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CS4330/31/33 may be either +5 or +3 V olts. Figure 3. De-Emphasis Curve (Fs = 44.1kHz)

Figure 4. CS4330 Data Format Figure 5. CS4331 Internal SCLK Data Format (I2S)

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Figure 8. CS4330/31/33 Initialization and Power-Down Sequence

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tude for a 1 kHz 20-bit dithered input signal. anniversary edition of AUDIO.TST. fundamental component of the signal. fundamental component of the signal. Figure 13. Frequency Response Figure 14. THD+N vs. Amplitude Figure 15. 0 dBFs FFT

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The CS4330, CS4331, CS4333 support multiple 2’s-complement data/clock formats. The required format is governed by the contents of the Con- figuration Register. The 5-bit register determines which serial data format is acceptable, the fre- quency of the Internal Serial Clock, on which edge of SCLK audio data must be valid, and the number of bits to be loaded into the input buffer. On initial power-up, the register is loaded with the default settings, and it is not necessary to write to the register if this format is appropriate. The default settings are shown in Figures 4-7. The 8-bit code includes a 3-bit preamble to pre- vent accidental access to the Configuration Register. Each bit of the code is read on the fall- ing edge of LRCK as shown in the Figures 21 and 22. The code 01000000 is considered to be an error condition and is ignored. The configura- tion routine requires that the SDATA pin is held high, as shown in Figures 21 and 22, to prevent accidental writing to the register. The Configura- tion Register is only accessible prior to entering the External Serial Clock Mode. For I 2S mode, the user must set B6 to 0, and B7 to 1. B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 Configuration Access Code 0 1 0 Access Allowed All other Codes Access Denied B4 B5 Internal SCLK Mode only Sets Internal SCLK/LRCK Ratio * 0 0 SCLK/LRCK = 32

01 R e s e r v e d

1 0 SCLK/LRCK = 64 1 1 SCLK/LRCK = 128 * The Internal SCLK will be 48 Fs, if the MCLK/LRCK ratio is 384×. B4 B5 External SCLK Mode only Selects Data Sampling edge of SCLK 1 0 Rising edge of SCLK 1 1 Falling edge of SCLK B6 Left or Right Justified Data in relation to LRCK transition

0 Left Justified

1 Right Justified

B8 Sets the number of Bits 0 18 Bits 1 16 BitsSchematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. For Our Free Review Service Call Applications Engineering. Call: (512) 445-7222 CS4330, CS4331, CS4333

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1)"An 18-Bit, 8-Pin Stereo Digital-to-Analog Kamath, and S.T. Dupuie. Paper presented at the 97th Convention of the Audio Engineering Soci- ety, November 1994. 2)"How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 3)"Multiplier-Free Interpolation for Oversampled Digital-to-Analog Conversion" by Jeffrey W. Scott. Paper presented at the 92nd Convention of the Audio Engineering Society, March 1992. 4)"An 18-Bit Stereo D/A Converter With Inte- grated Digital and Analog Filters" by Nav S. Sooch, Jeffrey W. Scott. Paper presented at the 91st Convention of the Audio Engineering Soci- ety, November 1991. 5)CDB4330/31/33 Evaluation board Data Sheet; DS136DB2 MAR’96 CS4330, CS4331, CS4333

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V A+ - Positive Analog Power, PIN 7. Positive analog supply. Nominally +5V or +3V . AGND - Analog Ground, PIN 6. Analog ground reference. Analog Outputs AOUTL - Analog Left Channel Output, PIN 8. Analog output for the left channel. Typically 3.7 Vpp for a full-scale input signal at V A+ = 5V and 1.85 Vpp at V A+ = 3V . AOUTR - Analog Right Channel Output, PIN 5. Analog output for the right channel. Typically 3.7 Vpp for a full-scale input signal at V A+ = 5V and 1.85 Vpp at V A+ = 3V . Digital Inputs MCLK - Master Clock Input, PIN 4. The frequency must be 256×, 384× , or 512× the input sample rate (Fs). LRCK - Left/Right Clock, PIN 3. This input determines which channel is currently being input on the Audio Serial Data Input pin, SDATA. SDATA - Audio Serial Data Input, PIN 1. Two’s complement MSB-first serial data is input on this pin. The data is clocked into the CS4330, CS4331, and CS4333 via internal or external SCLK and the channel is determined by LRCK. DEM/SCLK - De-emphasis / External serial clock input , PIN 2. A dual-purpose input used for de-emphasis filter control or external serial clock input. SERIAL DATA INPUT SDATA AOUTL ANALOG LEFT CHANNEL OUTPUT DE-EMPHASIS / SCLK DEM/SCLK VA+ ANALOG POWER LEFT / RIGHT CLOCK LRCK AGND ANALOG GROUND MASTER CLOCK MCLK AOUTR ANALOG RIGHT CHANNEL OUTPUT CS4330, CS4331, CS4333 DS136F1 19

Total Harmonic Distortion + Noise (THD+N) - The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range - The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFs signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels. Gain Error - The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift - The change in gain value with temperature. Units in ppm/°C. CS4330, CS4331, CS4333

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ORDERING INFORMATION : Model Temperature Package CS4330-KS -10 to +70°C 8-pin Plastic SOIC CS4331-KS -10 to +70°C 8-pin Plastic SOIC CS4333-KS -10 to +70°C 8-pin Plastic SOIC CS4330-BS -40 to +85°C 8-pin Plastic SOIC CS4331-BS -40 to +85°C 8-pin Plastic SOIC CS4333-BS -40 to +85°C 8-pin Plastic SOIC F G J I H B A MILLIMETERS INCHES MIN MAX MAXMINDIM H I J A B TYP1.27 0.050 TYP D 0 0.0100 0.25 E 0.070 0.0741.77 1.88 0.006 0.0100.15 0.25 8080 0.0300.0190.48 0.76 0.3190.302 0.203 0.2105.15 5.35 7.67 8.1 5.18 5.4 0.204 0.213 D C 8-Pin SOIC E F 0.33 0.51 0.020 G C 0.013 PACKAGE DIMENSIONS Note: The EIAJ package is not a standard JEDEC package size CS4330, CS4331, CS4333 DS136F1 21

• Notes •

• Demonstrates recommended layout and grounding arrangements
• CS8412 Receives AES/EBU, S/PDIF, & EIAJ-340 Compatible Digital Audio
• Digital and Analog Patch Areas
• Requires only a digital signal source and power supplies for a complete Digital-to-Analog-Converter system General Description The CDB4330/31/33 evaluation board is an excellent means for quickly evaluating the CS4330/31/33 18-bit, stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source and a power supply. Analog outputs are provided via RCA connec- tors for both channels. The CS8412 digital audio receiver I.C. provides the system timing necessary to operate the CS4330/31/33 and will accept AES/EBU, S/PDIF, and EIAJ-340 compatible audio data. The evaluation board may also be configured to accept external timing signals for op- eration in a user application during system development. ORDERING INFORMATION: CDB4330, CDB4331, CDB4333 Evaluation Board for CS4330 / CS4331 / CS4333 CDB4330 CDB4331 CDB4333 Digital Audio Input I/O for Clocks and Data CS8412 Digital Audio Interface CS4330/31/33 Analog Filter Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 Fax: (512) 445 7581 MAR ’96 DS136DB2 Copyright  Crystal Semiconductor Corporation 1996 (All Rights Reserved)

CDB4330/31/33 System Overview The CDB4330/31/33 evaluation board is an ex- cellent means of quickly evaluating the CS4330/31/33. The CS8412 digital audio inter- face receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system develop- ment. The CDB4330/31/33 schematic has been parti- tioned into 5 schematics shown in Figures 2 through 7. Each partitioned schematic is repre- sented in the system diagram shown in Figure 1. Notice that the the system diagram also includes the interconnections between the partitioned schematics. CS4330/31/33 Digital to Analog Converter A description of the CS4330/31/33 is included in the CS4330/31/33 data sheet. CS8412 Digital Audio Receiver The system receives and decodes the standard S/PDIF data format using a CS8412 Digital Audio Receiver, Figure 4. The outputs of the CS8412 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256Fs master clock. The operation of the CS8412 and a discussion of the digital audio in- terface are included in the 1994 Crystal Semiconductor Audio Data Book. During normal operation, the CS8412 operates in the Channel Status mode where the LED’s dis- play channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8412 to decode and supply the de-empha- sis bit from the digital audio interface for control of the CS4330/31/33 de-emphasis filter via pin 3, CC/F0, of the CS8412. When the Error Information Switch is activated, the CS8412 operates in the Error and Frequency information mode. The information displayed by the LED’s can be decoded by consulting the CS8412 data sheet. If the Error Information Switch is activated, and the CS4330/31/33 is in the internal serial clock mode, then it is likely that the de-emphasis control for the CS4330/31/33 will be erroneous and produce an incorrect audio output. Encoded sample frequency information can be displayed provided a proper clock is being ap- plied to the FCK pin of the CS8412. When an LED is lit, this indicates a "1" on the corre- sponding pin located on the CS8412. When an LED is off, this indicates a "0" on the corre- sponding pin. Neither the L or R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax, Fig- ure 6. It is not necessary to select the active input. However, both inputs can not be driven si- multaneously. CS8412 Data Format The CS8412 data format can be set with jumpers M0, M1, M2, and M3. These formats are shown in the CS8412 datasheet found in the 1994 Crys- tal Semiconductor Audio Data Book. The format selected must be compatible with the corre- sponding data format of the CS4330/31/33 shown in Figures 4-7 of the CS4330/31/33 datasheet. The default settings for M0-M3 on the evaluation board are given in Tables 2-4. The compatible data formats we have chosen for the CS8412 and CS4330/31/33 are: CS8412 format 6;CS4330 CS8412 format 2;CS4331 (External SCLK only) CS8412 format 5;CS4333 (External SCLK only) CDB4330, CDB4331, CDB4333

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Figure 7. The +5V input supplies power to the operates as a transmitter or receiver. CLK SOURCE jumper in the 8412 position. evaluation board for operation in this mode. the 1 position and J23 in the 0 position. ductions in radiated noise effects.

Table 2. CDB4330 Jumper Selectable Options Table 1. System Connections

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Table 3. CDB4331 Jumper Selectable Options Table 4. CDB4333 Jumper Selectable Options

Figure 1. System Block Diagram and Signal Flow

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Figure 2. CS4330/31/33 and Connections

Figure 3. Voltage Level Conversion and Power Down Circuitry

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Figure 4. CS8412 Digital Audio Receiver Connections

Figure 5. I/O Interface for Clocks and Data Figure 6. Digital Audio Input

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Figure 7. Power Supply

Figure 8. CDB4330/31/33 Component Side Silkscreen

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Figure 9. CDB4330/31/33 Component Side (top)

Figure 10. CDB4330/31/33 Solder Side (bottom)

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• Notes •

Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cir- rus.com.