CS4328-BP

CS4328 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

• Complete Stereo DAC System 8× Interpolation Filter 64× Delta-Sigma DAC Analog Post Filter
• Adjustable System Sampling Rates including 32kHz, 44.1kHz & 48kHz
• 120 dB Signal-to-Noise Ratio
• Low Clock Jitter Sensitivity
• Completely Filtered Line-Level Outputs Linear Phase Filtering Zero Phase Error Between Channels No External Components Needed
• Flexible Serial Interface for Either 16 or 18 bit Input Data General Description The CS4328 is a complete stereo digital-to-analog out- put system. In addition to the traditional D/A function, the CS4328 includes an 8× digital interpolation filter fol- lowed by a 64× oversampled delta-sigma modulator. The modulator output controls the reference voltage in- put to an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 1 kHz and 50 kHz while maintaining lin- ear phase response simply by changing the master clock frequency. The CS4328 also includes an extremely flexible serial port utilizing two select pins to support four different interface modes. The master clock can be either 256 or 384 times the input word rate, supporting various audio environ- ments. ORDERING INFORMATION: CS4328-KP 0 to 70 °C 28-pin Plastic DIP CS4328-KS 0 to 70 °C 28-pin Plastic SOIC CS4328-BP -40 to +85 °C 28-pin Plastic DIP CS4328-BS -40 to +85 °C 28-pin Plastic SOIC CDB4328 CS4328 Evaluation Board Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 http://www.crystal.com OCT ’93 DS62F3 18-Bit, Stereo D/A Converter for Digital Audio -VREF AOUTL SDATAI TST DIF1 DIF0 ACKI LRCK 28 BICK Voltage Reference VA+VA- AGND1 AOUTR CMPOCALI CALO 821 CMPI ACKO VD+ DGND Clock Osc/ Divider AGND2 AGND3 14 15 XTI XTO CKS RST Interpolator Interpolator Delta-SigmaModulatorDelta-Sigma Modulator Delta-SigmaModulatorDelta-Sigma Modulator S R A M Analog Low-Pass Filter Analog Low-Pass Filter DAC DAC Calibration Microcontroller MOSFET Output Stage MOSFET Output Stage Serial Input Interface Interpolator CS4328 Copyright  Crystal Semiconductor Corporation 1993 (All Rights Reserved)

• Definitions are at the end of this data sheet. Specifications are subject to change without notice. ANALOG CHARACTERISTICS (TA = 25°C for K grade, TA = -40 to +85 °C for B grade; VA+,VD+ = 5V; VA- = -5V; Logic "1" = VD+; Logic "0" = DGND; Full-Scale Output Sinewave, 991 Hz; Input Word Rate = 48 kHz; Input Data = 18 Bits; BICK = 3.072 MHz; RL = 10kΩ ; Measurement Bandwidth is 10 Hz to 20 kHz, un- weighted; unless otherwise specified.) Parameter* CS4328-K CS4328-B Symbol Min Typ Max Min Typ Max Units Specified Temperature Range T A 0+ 7 0 - 4 0 + 8 5 °C Resolution 16 - - 16 - - Bits Dynamic Performance Signal-to-Noise Ratio (A-weighted) (Note 1) SNR 120 - - 120 - - dB Total Harmonic Distortion + Noise (A-Weighted) THD+N 0 dB Output, - -93 -90 - -88 -85 dB -20 dB Output, - -77 -73 - -75 -70 dB -60 dB Output, - -37 -33 - -35 -30 dB Deviation From Linear Phase (Note 2) - - ± 0.5 - - ± 0.5 - deg Passband: to -3 dB corner (Notes 3, 4) - 0 to 23.5 0 to 23.5 kHz to 0.00025 dB corner (Notes 3, 4) 0 to 21.6 0 to 21.6 kHz Passband Ripple (Note 4) - - - 0.00025 - - 0.00025 dB StopBand (Note 3) - 26.4 - - 26.4 - - kHz StopBand Attenuation (Note 2) - 90 - - 90 - - dB Group Delay (IWR = Input Word Rate) tgd - 33/IWR - - 33/IWR - s Interchannel Isolation (1 kHz) - -100 -110 - -95 -105 - dB dc Accuracy Interchannel Gain Mismatch - - 0.1 - - 0.1 - dB Gain Error - - - ± 5- - ± 5% Gain Drift - - 150 - - 150 - ppm/ °C Offset Error (after calibration) - - - ± 1- - ± 1m V Analog Output Power Supplies Power Supply Current: VA+ IA+ - 40 55 - 40 55 mA VD+ ID+ - 50 60 - 50 60 mA Power Dissipation - - 650 850 - 650 850 mW Power Supply Rejection Ratio (1 kHz) PSRR - 50 - - 50 - dB Notes: 1. Idle channel, digital input all zeros. 2. Combined digital and analog filter characteristics. 3. The passband and stopband edges scale with frequency. For input word rates, IWR, other than 48 kHz, the 0.00025 dB passband edge is 0.45 ×IWR and the stopband edge is 0.55×IWR. 4. Digital filter characteristics. CS4328

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Parameter Symbol Min Typ Max Units High-Level Input Voltage V IH 70%VD+ - - V Low-Level Input Voltage V IL - - 30%VD+ V High-Level Output Voltage at Io = -20µAV OH 4.4 - - V Low-Level Output Voltage at Io = 20µAV OL -- 0 . 1 V Input Leakage Current (Note 5) I in -- 1 . 0 µA Note: 5. TST, DIF0 & DIF1 have internal pull-down devices, nominally 90kΩ . ABSOLUTE MAXIMUM RATINGS (AGND1-3, DGND = 0V, all voltages with respect to ground.) Parameter Symbol Min Max Units DC Power Supplies: Positive Digital VD+ -0.3 6.0 V Positive Analog VA+ -0.3 6.0 V Negative Analog VA- 0.3 -6.0 V |VA+ - VD+| - 0.4 V Input Current, Any Pin Except Supplies I in - ±10 mA Digital Input Voltage V IND -0.3 (VD+)+0.4 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C WARNING: Operation at or beyond these limits may result in permanent damage to the device Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND1, AGND2, AGND3, DGND = 0V; all voltages with respect to ground) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital VD+ 4.75 5.0 5.25 V Positive Analog VA+ 4.75 5.0 5.25 V Negative Analog VA- -4.75 -5.0 -5.25 V CS4328 DS62F3 3

(TA = 25 °C; VA+, VD+ = 5V ± 5%; VA- = -5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VD+, CL = 20 pF) Parameter Symbol Min Typ Max Units Master Clock Frequency using Internal Oscillator: CKS=H XTI/XTO 10.7 - 19.2 MHz CKS=L - 7.1 - 13.9 MHz Master Clock Frequency using External Clock: CKS=H XTI/XTO 0.384 - 19.2 MHz CKS=L - 0.256 - 13.9 MHz XTI/XTO Pulse Width Low - 21 - - ns XTI/XTO Pulse Width High - 21 - - ns BICK Pulse Width Low t bickl 30 - - ns BICK Pulse Width High t bickh 30 - - ns BICK Period t bickw 80 - - ns BICK rising to LRCK edge delay (Note 6) t blrd 35 - - ns BICK rising to LRCK edge setup time (Note 6) t blrs 35 - - ns SDATAI valid to BICK rising setup time (Note 6) t sbs 35 - - ns BICK rising to SDATAI hold time (Note 6) t bsh 35 - - ns RST Minimum Pulse Width Low 2 periods of XTI/XTO Note: 6. "BICK rising" refers to modes 0, 1, and 3. For mode 2, replace "BICK rising" with "BICK falling." bickht blrst blrdt sbst bsht bicklt SDATAI BICK LRCK bickht blrst blrdt sbst bsht bicklt SDATAI BICK LRCK MSB MSB-1 Serial Input Timing (Modes 0, 1, &3) Serial Input Timing (Mode 2) CS4328

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Figure 1. Typical Connection Diagram

22 ACKO

15 XTO

20 LRCKAudio

produces line-level outputs. capacitors are all that’s required. pin with the XTO pin left floating. must be synchronously derived from XTI/XTO. Table 1. Common Clock Frequencies

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ing from BICK coupling into VREF-. calibration the analog output is forced to zero. Table 2. Digital Input Formats Figure 2. RESET Cancellation Timing

16 Bit

18 Bit

Figure 5. Digital Input Format 3 Figure 4. Digital Input Format 2 Figure 3. Digital Input Formats 0 & 1 Figure 6. Digital Input Formats 0, 2 and 3 with 16 BICK Periods

8 DS62F3

moving the CS4328 to a muted state. put data propagates to the output of the DAC.

4096 LRCK cycles with 0 input data the output

located as near to the CS4328 as possible. short-circuit protected to 20mA. Figure 7. -50dB Muting Figure 8. -120 dB Muting

The following collection of CS4328 measure- ment plots (IWR = 48 kHz) were taken with an Audio Precision Dual Domain System One. All FFT plots are 16,384 point. Figure 9 shows the frequency response with a 48 kHz input word rate. The response is very flat out to half the input word rate. Figure 10 shows the muted noise with all zeros data into the CS4328. This plot is dominated by the noise floor of the System One. Figure 11 shows the unmuted noise. This data was taken by feeding the CS4328 continuous ze- ros, but pulling CALI low. This unmutes the output stage of the CS4328. This plot shows the noise shaping characteristics of the delta-sigma modulator combined with the analog filter. Figure 12 shows the A-weighted THD+N vs sig- nal amplitude for a dithered 1kHz input signal. Notice that there is no increase in distortion as the signal level decreases. This indicates very good low-level linearity, one of the key benefits of the delta-sigma technique. Figure 13 shows the fade-to-noise linearity test result using track 20 of the CBS CD-1. The in- put test signal is a dithered 500 Hz sine wave which gradually fades from -60 dB level to -120 dB. During the fading, the output level from the CS4328 is measured and compared to the ideal level. Notice the very close tracking of the out- put level to the ideal, even at low level inputs of -90 dB. The gradual shift of the plot away from zero at signal levels < -100 dB is caused by the background noise starting to dominate the meas- urement. Figure 14 shows the impulse response, taken from the single positive full scale value on track 17 of the CD-1 test disk. Notice the high degree of symmetry, indicating good phase linearity. Figure 15 shows a 16K FFT plot result, with a 1 kHz -90 dB dithered input. Notice the com- plete lack of distortion components and tones. Figure 16 shows a bandlimited, 10 Hz to 22 kHz, time domain plot of the CS4328 output with a 1 kHz, -90 dB dithered input. Notice the clear residual sine wave shape, in the presence of noise. Figure 17 shows the monotonicity test result plot. The input data to the CS4328 is +1 LSB, -1 LSB four times, then +2 LSB, -2 LSB four times and so on, until +10 LSB, -10 LSB. This data pattern is taken from track 21 of the CD-1 test disk. Notice the increasing staircase envelope, with no decreasing elements. Notice also the clear resolution of the LSB. For this test, one LSB is a 16-bit LSB. The following tests were done by filtering the analog output of the CS4328 with the System One analyzer 1 kHz notch filter to reduce the peak signal level. The resulting signal was then amplified and applied to the DSP module, avoid- ing distortion in the System One A/D converter. Figure 18 shows a 16K FFT Plot with a 1 kHz, 0 dB input. Notice the low order harmonic dis- tortion at < -100 dB. Figure 19 shows a 16K FFT Plot with a 1 kHz, -10 dB input. Notice the almost complete ab- sence of distortion, with a small residual 2nd harmonic at -110 dB. CS4328

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Figure 18. 1 kHz, 0 dB Input FFT Plot Figure 19. 1 kHz, -10 dB Input FFT Plot Figure 15. 1 kHz, -90 dB Input FFT Plot Figure 16. 1 kHz, -90 dB Input Time Domain Plot Figure 17. Monotonicity Test (16-bit data)

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hold results in data at a rate of 64× Fs. trum of the modulator output.

8 X S/H

Figure 20. CS4328 Architecture Figure 23. Spectrum After S/H Figure 22. 8X Interpolated Data Spectrum Figure 24. Modulator Output Spectrum Figure 21. Input Data Spectrum

analog filters with an input word rate of 48 kHz. produce a linear phase response. Figure 27. Deviation From Linear Phase Figure 25. Spectrum After Switched-Capacitor Filter Figure 26. Spectrum After Continuous Time Filter

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V A+ - Positive Analog Power, PIN 3. Positive analog supply. Nominally +5 volts. V A- - Negative Analog Power, PIN 5. Negative analog supply. Nominally -5 volts. AGND1, AGND2, AGND3 - Analog Grounds, PINS 1, 4, 25. Analog ground reference. VD+ - Positive Digital Power, PIN 16. Positive supply for the digital section. Nominally +5 volts. DGND - Digital Ground, PIN 17. Digital ground for the digital section. Analog Outputs VREF- - Voltage Reference Output, PIN 28. Nominally -3.68 volts. Normally connected to a 0.1µF ceramic capacitor in parallel with a 10µF or larger electrolytic capacitor. Note the negative output polarity. AOUTL - Analog Left Channel Output, PIN 2. Analog output for the left channel. Typically 4V peak-to-peak for a full-scale input signal. AOUTR - Analog Right Channel Output, PIN 26. Analog output for the right channel. Typically 4V peak-to-peak for a full-scale input signal. ANALOG GROUND AGND1 VREF- VOLTAGE REFERENCE OUTPUT ANALOG LEFT CHANNEL OUTPUT AOUTL CALI CALIBRATION INPUT ANALOG POWER VA+ AOUTR ANALOG RIGHT CHANNEL OUTPUT ANALOG GROUND AGND2 AGND3 ANALOG GROUND NEGATIVE ANALOG POWER VA- ACKI ANALOG CLOCK INPUT COMPARATOR OUTPUT CMPO NC NO CONNECT NO CONNECT NC ACKO ANALOG CLOCK OUTPUT COMPARATOR INPUT CMPI CALO CALIBRATION OUTPUT RESET RST LRCK LEFT/RIGHT CLOCK INPUT TEST TST BICK SERIAL BIT CLOCK INPUT CLOCK SELECT CKS SDATAI SERIAL DATA INPUT DIGITAL INPUT FORMAT 1 DIF1 DGND DIGITAL GROUND DIGITAL INPUT FORMAT 0 DIF0 VD+ DIGITAL POWER CRYSTAL OR CLOCK INPUT XTI XTO CRYSTAL OSCILLATOR OUTPUT CS4328

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XTI - Crystal or Clock Input, PIN 14. A crystal oscillator can be connected between this pin and XTO, or an external CMOS clock can be input on XTI. The frequency must be either 256× or 384× the input word rate based on the clock select pin, CKS. ACKI - Analog Clock Input, PIN 24. This is the master clock input for the analog section of the chip and must be 128× the input word rate. ACKI is typically connected to the Analog Clock Ouput pin, ACKO. CALI - Calibration Input, PIN 27. Input to the analog section that is used during offset calibration. Normally connected to the Calibration Output pin, CALO. CMPI - Comparator Input, PIN 8 Input to the digital section that is used during offset calibration. Normally connected to the Comparator Output pin, CMPO. LRCK - Left/Right Clock, PIN 20. This input determines which channel is currently being input on the Serial Data Input pin, SDA TAI. The format of LRCK is controlled by DIF0 and DIF1. BICK - Serial Bit Input Clock, PIN19. Clocks the individual bits of the serial data in from the SDA TAI pin. The edge used to latch SDA TAI is controlled by DIF0 and DIF1. SDATAI - Serial Data Input, PIN 18. Two’s complement MSB-first serial data of either 16 or 18 bits is input on this pin. The data is clocked into the CS4328 via the BICK clock and the channel is determined by the LRCK clock. The format for the previous two clocks is determined by the Digital Input Format pins, DIF0 and DIF1 DIF0,DIF1 - Digital Input Format, PINS 13, 12 These two pins select one of four formats for the incoming serial data stream. These pins set the format of the BICK and LRCK clocks with respect to SDATAI. The formats are listed in Table 2. CKS - Clock Speed Select, PIN 11. Selects the clock frequency input on the XTI pin. CKS low selects 256× the input word rate (LRCK frequency) while CKS high selects 384×. RST - Reset and Calibrate, PIN 9. When reset is low the filters and modulators are held in reset. When reset goes high, an offset calibration is initiated. CS4328 DS62F3 17

XTO - Crystal Oscillator Output, PIN 15. When a crystal oscillator is used, it is tied between this pin and XTI. When an external clock is input, this pin should be left floating. ACKO - Analog Clock Output, PIN 22. This output is 128× the input word rate (LRCK frequency). Normally connected to the Analog Clock Input pin, ACKI. CALO - Calibration Output, PIN 21. Used during offset calibration. Must be connected to the Calibration Input pin, CALI. CMPO - Comparator Output, PIN 6. Used during offset calibration. Must be connected to the Comparator Input pin, CMPI. Miscellaneous NC - No Connection, PINS 7, 23. These two pins are bonded out to test outputs. They must not be connected to any external component or any length of PC trace. TST -Test Input, PIN 10. Allows access to the CS4328 test modes, which are reserved for factory use. Must be tied to DGND. CS4328

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Total Harmonic Distortion + Noise - The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Signal-to-Noise Ratio - The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth with an input of all zeros. Frequency Response - A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels. Gain Error - The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift - The change in gain value with temperature. Units in ppm/°C. (AGND). Units in mV . CS4328 DS62F3 19

D B A L C 13.72 14.22 0.540 0.560 36.45 1.02 0.36 0.51 3.94 3.18 0.20 15.24 37.21 1.65 0.56 1.02 5.08 3.81 0.38 15° 1.435 0.040 0.014 0.020 0.155 0.125 0.600 0.008 1.465 0.065 0.022 0.040 0.200 0.150 0.015 15° 15.87 0.625 2.41 2.67 0.095 0.105 C eA D B SEATING PLANE A B1 e1 A1 L NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. NOM 13.97 36.83 1.27 0.46 0.76 4.32 0.25 2.54 NOM 0.550 1.450 0.050 0.018 0.030 0.170 0.010 0.100 eA SOIC MILLIMETERS INCHES MIN MAX MAXMIN 0.095 0.1052.41 2.67 0.008 0.0150.203 0.381 0.398 0.42010.11 10.67 0.0200.0130.510.33 0.016 0.0350.41 0.89 8°0°0° 8° MILLIMETERS INCHES MIN MAX MAX MINpins 0.4100.3909.91 10.4116 0.5100.49012.45 12.9520 0.6100.59014.99 15.5024 0.7100.69017.53 18.0328 0.0120.0050.127 0.300 1.14 0.040 DIM E E b L D e A A c 0.292 0.2987.42 7.57 D EE 1 e A Ab 1 A 2 c L µ µ 1.40 0.055 A 2 see table above NOM 2.54 0.280 10.41 0.46 NOM 10.16 12.70 15.24 17.78 7.49 1.27 2.29 2.542.41 NOM 0.100 0.011 0.410 0.018 NOM 0.400 0.500 0.600 0.700 0.295 0.050 0.1000.090 0.095

• Demonstrates recommended layout and grounding arrangements
• CS4328 Supports multiple input formats
• CS8412 Receives AES/EBU, S/PDIF, & EIAJ-340 Compatible Digital Audio
• Digital and Analog Patch Areas
• Operation with on-board CS8412 or externally supplied system timing General Description The CDB4328 evaluation board allows fast evaluation of the CS4328 18-bit, stereo D/A converter. The board provides an analog output interface via BNC connec- tors for both channels. Evaluation requires an analog signal analyzer, a digital signal source, and a power supply. Also included is a CS8412 digital audio receiver I.C., which will accept AES/EBU, S/PDIF, and EIAJ-340 compatible audio data. The CS8412 can provide the system timing necessary to operate the CS4328. The evaluation board may also be configured to accept external timing signals for operation in a user applica- tion during system development. ORDERING INFORMATION: CDB4328 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445 7222 Fax: (512) 445 7581 http://www.crystal.com AUG ’93 DS62DB2 CS4328 Evaluation Board CDB4328 Error Info/ Channel Status -15V GND +15V GND +5V L/R SCLK SDATA MCLK Power Supply Regulation and Conditioning AOUTR AOUTL Analog Patch Area Digital Patch Area CS4328 D/A Converter Offset Calibration Network Digital Audio Input Timing Signal Selector CS8412 Digital Audio Receiver Block Diagram

power supply filtering for the analog supplies. digital logic from the analog circuitry. initiates an offset calibration cycle. data, are also provided on the evaluation board. Figure 1. Power Supply and Reset Circuitry

22 DS62DB2

explanation of the different formats. tem that provides the serial data to the board. Figure 2. CS4328 DAC Connections

8412 SDA T A,SCLK, L/ R provided

Table 1. JP3 Selectable Options

master clock is to be used, U8 must be removed from it’s socket to prevent the two clock signals from interfering with one another. When 8412 is selected by JP3, the master clock for the CS4328 is provided by the MCK output of the CS8412. The CKS pin of the CS4328 can be pulled either high or low via JP2. This determines whether the master clock frequency has to be 384X or 256X the input word rate. Consult the CS4328 data sheet for the common master clock frequen- cies table. Analog Outputs The analog outputs are available at 2 BNC con- nectors labeled AOUTL and AOUTR. R5 and C18 remove the remaining very high frequency components from the left channel output signal while R6 and C19 do so for the right channel output signal. Digital Audio Standard Interface Included on the evaluation board is a CS8412 Digital Audio Interface Receiver. This device can receive and decode data according to the AES/EBU, S/PDIF, and EIAJ-340 interface standard. Figure 3 shows the schematic for the CS8412. The input is coupled to the device through a transformer that is included on the board. The input to the device can be configured to accept either professional or consumer input modes. Consult the CS8412 data sheet for an explanation of the two input modes. The LEDs, D4-D8, perform two functions. When S1 is in the Channel Status position, the LEDs display the channel status information for the channel selected by JP1. When S1 is in the Error Information position, the LEDs D4-D6, display encoded error information that can be decoded by consulting the CS8412 data sheet. Encoded sample frequency information is dis- played on LEDs D7-D9 provided a proper clock is being applied to the FCK pin of JP1. When an LED is lit, this indicates a "1" on the corre- sponding pin located on the CS8412. When an LED is off, this indicates a "0" on the corre- sponding pin. Neither the L or R option should be selected if the FCK pin of JP1 is being driven by a clock signal. Serial Output Interface The SDATA, SCLK, L/ R, and MCLK BNC connectors can also be used to provide a serial output interface for the CS8412. With JP3 in the 8412 position, the outputs from the CS8412 can be brought off the board to an external evalution system. This data can be configured in one of seven selectable formats. These formats are out- lined in the CS8412 data sheet. CDB5336/7/8/9 Interface to CDB4328 Many users find it informative to evaluate a combined ADC and DAC system connected to- gether yielding analog input and analog output. This can be accomplished by interconnecting a CDB5326/7/8/9 or CDB5336/7/8/9 to a CDB4328 evaluation board. The following in- formation contains several techniques to accomplish this goal. There are two general points which need to be mentioned. An analog input of ± 3.68 V will produce a full scale digital output from the CS5336/7/8/9 and the CS5326/7/8/9. A full scale digital input to the CS4328 will produce a full scale output of ± 2 V resulting in an overall loss of approximately 5.2 dB from input to output. Also it is recom- mended that the power connections for each board are brought directly from the power sup- ply and not in a "daisy-chain" manner from board to board. Connecting the CDB4328 to the CDB5336/7/8/9 can be accomplished using one of two methods: CDB4328

24 DS62DB2

56 Pin 19,

98 Pin 18,

12.288 MHz

8 AGND

Figure 3. CS8412 Digital Audio Receiver Connections

the trace at the SDA TA BNC connector and place a jumper between the SDA TA BNC and U8 pin 11. CMODE is set LOW for a master clock of 256 times the sample rate. P7 must have both the internal and external jumpers in- stalled. This will route the master clock to the EXTCLKIN BNC for connection to the CDB4328 MCLK. If a CS5336/8 is installed an additional modifi- cation is required to invert the SCLK prior to transmission to the CDB4328. This can be im- plemented as follows: cut the trace at the SCLK BNC and install a jumper between U7 pin 4 and the SCLK BNC. CDB5336/7/8/9 and CDB4328 Interconnection for Method 2 Shielded coaxial cables with BNC connectors should be used to make the following connec- tions: L/R to L/R, SCLK to SCLK, SDA TA to SDA TA, EXTCKIN to MCLK. CDB4328 Interfacing to the CDB5326/7/8/9 A method of interfacing the CDB5326/7/8/9 and the CDB4328 requires a direct interface through the EXTCLKIN, SCLK, SDA TA, and L/R BNC connectors. This technique requires modifica- tions to the CDB5326/7/8/9 to derive the proper clock frequencies. This is done by utilizing a

12.288 MHz clock and supplying a clock to the

CDB5326/7/8/9 at 6.144 MHz. CDB4328 Configuration The CS4328 must be set to receive data in for- mat 2 (DIF1 high and DIF0 low). Modify the jumpers located near pins 12 and 13 of the CS4328. JP2 sets the clock to sample frequency ratio (CKS) on the CS4328 and is set low for a 256 ratio. JP3 selects the source of SDA TA, SCLK and L/R that will be provided to the converter and should be removed to access the multiple clocks from the CDB5326/7/8/9. Remove the 12.288 MHz oscillator (U8). CDB5326/7/8/9 Configuration Remove the clock source jumper (P2). Remove the 6.144 MHz oscillator (U2) and replace with the 12.288 MHz oscillator from the CDB4328. Install a divide by 2 function on the CDB5326/7/8/9 digital patch area. Use a 74HC74 with the D input connected to the Q output. Connect the oscillator output to the 74HC74 clock input. Connect the Q output to U1 pin 23. Position P2 to connect the oscillator output to the EXTCLKIN. CDB5326/7/8/9 and CDB4328 Interconnection Shielded coaxial cables with BNC connectors should be used to make the following connec- tions: L/ R to L/R, SCLK to SCLK, SDA TA to SDA TA, EXTCLKIN to MCLK. CDB4328 DS62DB2 27

Figure 4. Top Ground Plane Layer (NOT TO SCALE)

28 DS62DB2

Figure 5. Bottom Trace Layer (NOT TO SCALE)

Figure 5. Silk Screen Layer (NOT TO SCALE)

30 DS62DB2

• Notes •

Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation