CS4327 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
/c108 20-Bit Conversion /c108 108 dB Signal-to-Noise-Ratio (EIAJ) /c108 100 dB Dynamic Range /c108 Single-Ended Outputs /c108 Complete Stereo DAC System - 128X Interpolation Filter - Delta-Sigma DAC - Analog Post Filter /c108 Low Clock Jitter Sensitivity /c108 Filtered Line-Level Outputs - Linear Phase Filtering - Zero Phase Error Between Channels /c108 Digital De-emphasis for 32 kHz, 44.1 kHz & 48 kHz
Description
The CS4327 is a complete stereo digital-to-analog out- put system. In addition to the traditional D/A function, the CS4327 includes a digital interpolation filter followed by an 128X oversampled delta-sigma modulator. The mod- ulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This architecture al- lows for infinite adjustment of sample rate between 1 and 50 kHz while maintaining linear phase response simply by changing the master clock frequency. The CS4327 also includes an extremely flexible serial port utilizing mode select pins to support multiple inter- face formats. The master clock can be either 256, 384, or 512 times the input sample rate, supporting various audio environments. ORDERING INFO CS4327-KS -10 to 70 °C 16-pin Plastic SSOP CDB4327 CS4327 Evaluation Board I DIF0 DIF1 DEM0 DEM1 VA+ VD+ LRCK SCLK SDATA AOUTL MCLK AGND Serial Input Interface De-emphasis Voltage Reference Interpolator Delta-Sigma Modulator DAC Analog Low-Pass Filter Interpolator Delta-Sigma Modulator DAC Analog Low-Pass Filter AOUTR DGND AUTO_MUTE 15 11 1 2 3 6 485 CMFILT16 DEC ‘97 DS190F1
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ANALOG CHARACTERISTICS (TA = 25 °C; Internal SCLK; Full-Scale Output Sine wave, 997 Hz; 12.288 MHz MCLK; Fs = 48 kHz; Input Data = 20 Bits; SCLK = 3.072 MHz; RL = 10 kΩ ; VD+ = VA+ = 5 V; Logic 1 = VD+, Logic 0 = DGND; Measurement Bandwidth is 10 Hz to 20 kHz, unweighted, unless otherwise spec- ified.) Notes: 1. Triangular PDF Dithered Data 2. Auto-mute enabled. See parameter definitions. 3. Group Delay for Fs = 48 kHz 25/48 kHz = 520 µs Parameter Symbol Min Typ Max Unit Specified Temperature Operating Range T A -10 - 70 °C Dynamic Performance Dynamic Range (Note 1) 20-Bit (A-Weighted) 18-Bit (A-Weighted) 16-Bit (A-Weighted) 100 100 dB dB dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 20-Bit 0 dB -20 dB -60 dB 18-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -87 -33 -93 -77 -37 -93 -77 -37 -93 -77 -37 dB dB dB dB dB dB dB dB dB Idle Channel Noise / Signal-to-Noise-Ratio (Note 2) - 108 - dBFS Interchannel Isolation (1 kHz) - -105 - dB Combined Digital and Analog Filter Characteristics Frequency Response 10 Hz to 20 kHz Fs = 48 kHz - ±0.1 - dB Deviation from linear phase - ±0.5 - deg Passband: to -0.1 dB corner 0 - 0.4535 Fs Passband Ripple - - ±0.002 dB StopBand 0.5465 - - Fs StopBand Attenuation 72 - - dB Group Delay (Note 3) - 25/Fs - s De-emphasis Error - - ±0.2 dB
ANALOG CHARACTERISTICS (Continued) POWER AND THERMAL CHARACTERISTICS (TA = 25 °C; Internal SCLK; Full-Scale Output Sine wave, 997 Hz; 12.288 MHz MCLK; Fs = 48 kHz; Input Data = 20 Bits; SCLK = 3.072 MHz; RL = 10 kΩ ; VD+ = VD+ = 5 V; Logic 1 = VD+, Logic 0 = DGND; Measurement Bandwidth is 10 Hz to 20 kHz, unweighted, unless otherwise specified.) Parameter Symbol Min Typ Max Unit dc Accuracy Interchannel Gain Mismatch - 0.1 - dB Gain Error - ±2 ±5 % Gain Drift - 200 - ppm/°C Analog Output Full Scale Output Voltage 0.95 1.0 1.05 Vrms Load Resistance 6 - - k Ω Load Capacitance - - 100 pF Output Common Mode Voltage - 2.3 - V Parameter Symbol Min Typ Max Unit Power Supply Current Normal Operation Power Down IA+ ID+ (IA+) + (ID+) (IA+) + (ID+) 300 mA mA mA µA Power Dissipation Normal Operation Power-down 185 1.5 215 mW mW Power Supply Rejection Ratio (1 kHz) PSRR - 60 - dB Allowable Junction Temperature - - 135 °C Junction to Ambient Thermal Impedance Θ JA - 120 - °C/W
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SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 5.0 V; Inputs: Logic 0 = 0 V, Logic 1 = VD+, C L = 20 pF) Parameter Symbol Min Typ Max Unit Input Sample Rate Fs 1 - 50 kHz MCLK Pulse Width High MCLK/LRCK = 512 10 - - ns MCLK Pulse Width Low MCLK/LRCK = 512 10 - - ns MCLK Pulse Width High MCLK/LRCK = 384 21 - - ns MCLK Pulse Width Low MCLK/LRCK = 384 21 - - ns MCLK Pulse Width High MCLK/LRCK = 256 31 - - ns MCLK Pulse Width Low MCLK/LRCK = 256 31 - - ns External SCLK Mode SCLK Pulse Width Low t sclkl 20 - - ns SCLK Pulse Width High t sclkh 20 - - ns SCLK Period t sclkw -- n s SCLK rising to LRCK edge delay t slrd 20 - - ns SCLK rising to LRCK edge setup time t slrs 20 - - ns SDATA valid to SCLK rising setup time t sdlrs 20 - - ns SCLK rising to SDATA hold time t sdh 20 - - ns Internal SCLK Mode SCLK Period SCLK/LRCK = 64 t sclkw -- n s SCLK rising to LRCK edge t sclkr -- n s SDATA valid to SCLK rising setup time t sdlrs -- n s SCLK rising to SDATA hold time MCLK/LRCK = 256 or 512 tsdh -- n s SCLK rising to SDATA hold time MCLK/LRCK = 384 t sdh -- n s tsclkw
*INTERNAL SCLK LRCK sclkwt sdlrst sdht sclkrt External Serial Mode Input Timing Internal Serial Mode Input Timing. * The SCLK pin must be terminated to ground. The SCLK pulses shown are internal to the CS4327
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DIGITAL CHARACTERISTICS (TA = 25 °C; VD+ = 5 V ±5%) ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameter Symbol Min Typ Max Unit High-Level Input Voltage V IH 2.0 - - V Low-Level Input Voltage V IL -- 0 . 8 V Input Leakage Current - - ±10.0 µA Digital Input Capacitance - 10 - pF Parameter Symbol Min Max Unit DC Power Supply: Positive Analog Positive Digital |VA+ - VD+| VA+ VD+ -0.3 -0.3 0.0 6.0 6.0 0.4 V V V Input Current, Any Pin Except Supplies I in -± 1 0 m A Digital Input Voltage V IND -0.3 (VD+) + 0.4 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Parameter Symbol Min Typ Max Unit DC Power Supply: Positive Analog Positive Digital |VA+ - VD+| VA+ VD+ 4.75 4.75 5.0 5.0 5.25 5.25 0.1 V V V
Figure 1. Typical Connection Diagram
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to variations in resistor values. defined by the master clock. Figure 2. Block Diagram
Table 1. Common Clock Frequencies formats, along with the associated figure number. format with the MSB-first in all four formats. Table 2. Digital Input Formats the number of data bits required. Figure 4. A very small offset will result if the 18 or 16-bit data is followed by static non-zero data. external and internal serial clock generation modes. is internally derived and synchronous with MCLK. an external serial clock synchronized with LRCK.
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Figure 3. Digital Input Format 0 and 1. Figure 4. Digital Input Format 2. Figure 5. Digital Input Format 3.
Table 3. De-Emphasis Filter Selection when MCLK and LRCK are restored.
1.8 V appears at the outputs, with approximately a
Figure 6. De-emphasis Filter Response
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Figure 7. CS4327 Combined Digital and Analog Filter Figure 8. CS4327 Combined digital and Analog Filter Figure 9. CS4327 Combined Digital and Analog Filter
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Grounding and Power Supply Decoupling As with any high resolution converter, the CS4327 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 1 shows the recommended power arrange- ments with VA+ connected to a clean +5 volt sup- ply. VD+ should be derived from VA+ through a 2 ohm resistor. VD+ should not be used to power additional digital circuitry. All mode pins which re- quire VD+ should be connected to pin 6 of the CS4327. All mode pins which require DGND should be connected to pin 5 of the CS4327. Pins 4 and 5, AGND and DGND, should be connected to- gether at the CS4327. DGND for the CS4327 should not be confused with the ground for the dig- ital section of the system. The CS4327 should be positioned over the analog ground plane near the digital / analog ground plane split. The analog and digital ground planes must be connected elsewhere in the system. The CS4327 evaluation board, CDB4327, demonstrates this layout technique. This technique minimizes digital noise and insures proper power supply matching and sequencing. Decoupling capacitors should be located as near to the CS4327 as possible. Performance Plots The following collection of CS4327 measurement plots were taken from the CDB4327 evaluation board using the Audio Precision Dual Domain Sys- tem One. Figure 13 shows the frequency response at a 48 kHz sample rate. The response is flat to 20 kHz ±0.1 dB as specified. Figure 14 shows THD+N versus signal amplitude for a 1 kHz 20-bit dithered input signal. Notice that the there is no increase in distortion as the signal level decreases. This indicates very good low-level linearity, one of the key benefits of delta-sigma digital to analog conversion. Figure 15 shows a 16k FFT of a 1 kHz full-scale in- put signal. The signal has been filtered by a notch filter within the System One to remove the funda- mental component of the signal. This minimizes the distortion created in the analyzer analog-to-dig- ital converter. This technique is discussed by Audio Precision in the 10th anniversary addition of AU- DIO.TST. Figure 16 shows a 16k FFT of a 1 kHz -20 dBFS in- put signal. The signal has been filtered by a notch filter within the System One to remove the funda- mental component of the signal. Figure 17 shows a 16k FFT of a 1 kHz -60 dBFS in- put signal. Figure 18 shows the fade-to-noise linearity. The in- put signal is a dithered 20-bit 500 Hz sine wave which fades from -60 to -120 dBFS. During the fade, the output from the CS4327 is measured and compared to the ideal level. Notice the very close tracking of the output level to the ideal, even at low level inputs. The gradual shift of the plot away from zero at signals levels < -110 dB is caused by the background noise starting to dominate the mea- surement.
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V A+ - Positive Analog Power, PIN 3. Positive analog supply. Nominally +5 volts. VD+ - Positive Digital Power, PIN 6. Positive supply for the digital section. Nominally +5 volts. AGND - Analog Ground, PIN 4. Analog ground reference. DGND - Digital Ground, PIN 5. Ground for the digital section. Analog Outputs AOUTR - Right Channel Analog Output, PIN 13. Analog output connection for the Right channel output. Nominally 1 Vrms for full-scale digital input signal. AOUTL - Left Channel Analog Output, PIN 14. Analog output connection for the Left channel outputs. Nominally 1 Vrms for full-scale digital input signal. CMFILT DIF0 AOUTL AOUTR AUTO_MUTE DIF1 SDATA SCLK MCLK LRCK VD+ DGND AGND VA+ DEM1 DEM0
MCLK - Clock Input, PIN 8. The frequency must be either 256x, 384x or 512x the input sample rate (Fs). LRCK - Left/Right Clock, PIN 7. This input determines which channel is currently being input on the Serial Data Input pin, SDATA. The format of LRCK is controlled by DIF0 and DIF1. SCLK - Serial Bit Input Clock, PIN 9. Clocks the individual bits of the serial data in from the SDATA pin. The edge used to latch SDATA is controlled by DIF0 and DIF1. SDATA - Serial Data Input, PIN 10. Two' s complement MSB-first serial data of either 16, 18 or 20 bits is input on this pin. The data is clocked into the CS4327 via the SCLK clock, and the channel is determined by the LRCK clock. The format for the previous two clocks is determined by the Digital Input Format pins, DIF0 and DIF1. DIF0, DIF1 - Digital Input Format, PINS 15, 11 These two pins select one of four formats for the incoming serial data stream. These pins set the format of the SCLK and LRCK clocks with respect to SDATA. The formats are listed in Table 2. DEM0, DEM1 - De-Emphasis Select, PINS 1, 2. Controls the activation of the standard 50/15 µs de-emphasis filter for either 32, 44.1 or 48 kHz sample rates. AUTO_MUTE - Automatic Mute on Idle Channel Input, PIN 12. When AUTO_MUTE is low the analog outputs are muted following an idle channel detection. Idle channel is defined as an input of static 1's or static 0's during 8192 consecutive LRCK cycles. Mute is canceled with the return of active channel input data. CMFILT - Common Mode Filter, PIN 16 Used to filter the common mode output voltage with a 1 µF capacitor. This pin is not intended to supply any current and should not be used for the generation of an external bias voltage.
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The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the rms analog output level with 1 kHz full scale digital input to the rms analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter' s output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. De-Emphasis Error A measure of the difference between the ideal de-emphasis filter and the actual de-emphasis filter response. Measured from 10 Hz to 20 kHz. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C.
E A D E1 SIDE VIEW END VIEW TOP VIEW Seating Plane N 13 2 Dimensions N MILLIMETERS MIN NOM MAX 6.90 7.20 7.50 9.90 10.20 10.50 Note DIM MILLIMETERS MIN NOM MAX A b D e E L N -- 2.13 0.05 0.15 0.25 1.62 1.75 1.88 0.22 0.30 0.38 see other table 5.00 5.30 5.60 7.40 7.80 8.20 0.63 0.90 1.03 see other table 0°4 ° 8 ° Note 2, 3 e 0.61 0.65 0.69 L INCHES MIN NOM MAX -- 0.084 0.0020.0060.010 0.064 0.0700.074 0.009 0.0120.015 see other table 0.197 0.2090.220 0.291 0.3070.323 0.025 0.0350.040 see other table 0° 4° 8° 0.024 0.0260.027 D INCHES MIN NOM MAX 0.272 0.283 0.295 0.390 0.4020.413 NOTES: 1. DIMENSIONS D AND E1 ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.20mm PER SIDE. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13mm TOTAL IN EXCESS OF b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION b BY MORE THAN 0.07mm AT LEAST MATERIAL CONDITION. 3. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25mm FROM LEAD TIPS.
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- Demonstrates recommended layout and grounding arrangements
- CS8412 Receives AES/EBU, S/PDIF, & EIAJ-340 Compatible Digital Audio
- Digital and Analog Patch Areas
- Requires only a digital signal source and power supplies for a complete Digital-to-Analog-Converter system General Description The CDB4327 evaluation board is an excellent means for quickly evaluating the CS4327 20-bit, stereo D/A converter. Evaluation requires an analog signal ana- lyzer, a digital signal source and a power supply. Analog outputs are provided via RCA connectors for both channels. The CS8412 digital audio receiver I.C. provides the system timing necessary to operate the CS4327 and will accept AES/EBU, S/PDIF, and EIAJ-340 compat- ible audio data. The evaluation board may also be configured to accept external timing signals for opera- tion in a user application during system development. ORDERING INFORMATION: CDB4327 Evaluation Board for CS4327 CDB4327 I/O for Clocks and Data CS8412 Digital Audio Interface CS4327 Analog Filter Copyright Cirrus Logic, Inc. 1997 (All Rights Reserved) Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com DEC ’95 DS190DB1
The CDB4327 evaluation board is an excellent means of quickly evaluating the CS4327. The CS8412 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equip- ment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB4327 schematic has been partitioned into 7 schematics shown in Figures 2 through 8. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the the system diagram also includes the inter- connections between the partitioned schematics. CS4327 Digital to Analog Converter A description of the CS4327 is included in the CS4327 data sheet. CS8412 Digital Audio Receiver The system receives and decodes the standard S/PDIF data format using a CS8412 Digital Audio Receiver, Figure 8. The outputs of the CS8412 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256Fs master clock. The operation of the CS8412 and a discussion of the digital audio in- terface are included in the 1994 Crystal Semiconductor Audio Data Book. During normal operation, the CS8412 operates in the Channel Status mode where the LED’s dis- play channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8412 to decode and supply the de-empha- sis bit from the digital audio interface for control of the CS4327 de-emphasis filter via pin 3, CC/F0, of the CS8412. When the Error Information Switch is activated, the CS8412 operates in the Error and Frequency information mode. The information displayed by the LED’s can be decoded by consulting the CS8412 data sheet. If the Error Information Switch is activated, the CC/F0 output has no re- lation to the de-emphasis bit and it is likely that the de-emphasis control for the CS4327 will be erroneous and produce an incorrect audio output. Encoded sample frequency information can be displayed provided a proper clock is being ap- plied to the FCK pin of the CS8412. When an LED is lit, this indicates a "1" on the corre- sponding pin located on the CS8412. When an LED is off, this indicates a "0" on the corre- sponding pin. Neither the L or R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax, Fig- ure 7. It is not necessary to select the active input. However, both inputs can not be driven simultaneously. Data Format The CS4327 must be configured to be compat- ible with the incoming data and can be set with DIF0 and DIF1. The CS8412 data format can be set with the M0, M1, M2 and M3. There are sev- eral data formats which the CS8412 can produce that are compatible with CS4327. Refer to Table 2 for one possibility. Power Supply Circuitry Power is supplied to the evaluation board by four binding posts, Figure 9. The +5 V olt input supplies power to the CS4327 (through V A+), the CS8412 (through V A+ and VD+), and the +5 V olt digital circuitry (through VD+). The +/- 12 V olt input supplies power to the analog filter cir- cuitry. CDB4327
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Input/Output for Clocks and Data The evaluation board has been designed to allow the interface to external systems via the 10-pin header, J1. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 6. The 74HC243 transceiver functions as an I/O buffer where the CLK SOURCE jumper determines if the transceiver operates as a transmitter or receiver. The transceiver operates as a transmitter with the CLK SOURCE jumper in the 8412 position. LRCK, SDATA, and SCLK from the CS8412 will be available on J1. J22 must be in the 0 position and J23 must be in the 1 position for MCLK to be an output and to avoid bus conten- tion on MCLK. The transceiver operates as a receiver with the CLK SOURCE jumper in the EXTERNAL posi- tion. LRCK, SDATA and SCLK on J1 become inputs. The CS8412 must be removed from the evaluation board for operation in this mode. There are 2 options for the source of MCLK in the EXT CLK source mode. MCLK can be an input with J23 in the 1 position and J22 in the 0 position. However, the recommended mode of operation is to generate MCLK on the evaluation board. MCLK becomes an output with LRCK, SCLK and SDATA inputs. This technique insures that the CS4327 receives a jitter free clock to maximize performance. This can be accom- plished by installing a crystal oscillator into U4, see Figure 8 (the socket for U4 is located within the footprint for the CS8412) and placing J22 in the 1 position and J23 in the 0 position. Analog Filter The design of the second-order Butterworth low- pass filter, Figure 5, is discussed in the CS4327 data sheet and the applications note "Design Notes for a 2-pole Filter." Grounding and Power Supply Decoupling The CS4327 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 2 shows the recommended power arrangements with V A+ connected to a clean +5 V olt supply. VD1+ is derived from V A+ through a 2 ohm resistor. VD1+ should not used for any additional digital circuitry. Ideally, all mode pins which require VD1+ should be connected to pin 6 of the CS4327 and all mode pins which require DGND should con- nected to pin 5 of the CS4327. AGND and DGND, Pins 4 and 5, are connected together at the CS4327. The evaluation board has separate analog and digital regions with individual ground planes. DGND for the CS4327 should not be confused with the ground for the digital section of the system (GND). The CS4327 is po- sitioned over the analog ground plane near the digital/analog ground plane split. These ground planes are connected elsewhere on the board. This layout technique is used to minimizing digi- tal noise and to insure proper power supply matching/sequencing. The decoupling capacitors are located as close to the CS4327 as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yield large reductions in radiated noise ef- fects. CDB4327 DS190DB1 23
Table 2. CDB4327 Jumper Selectable Options Table 1. System Connections
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Figure 1. System Block Diagram and Signal Flow
Figure 2. CS4327 and Connections
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Figure 5. 2-Pole Analog Filter Figure 6. I/O Interface for Clocks and Data
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Figure 7. Digital Audio Input
Figure 8. CS8412 and Connections
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Figure 9. Power Supply Connections
Figure 10. CDB4327 Component Side Silkscreen
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Figure 11. CDB4327 Component Side (top)
Figure 12. CDB4327 Solder Side (bottom)
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