CS43122 CIRRUS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 28
Technical content
Features
lUp to 192 kHz Sample Rates l122 dB Dynamic Range l-102 dB THD+N lSecond-Order Dynamic-Element Matching lLow Clock Jitter Sensitivity l102 dB Stop-band attenuation lSingle +5 V supply lSoft Mute Control lDigital De-Emphasis for 32, 44.1, and 48 kHz lExternal Reference Input lPin-compatible with the CS4396
Description
The CS43122 is a complete high performance 24 bit- 192 kHz stereo digital-to-analog conversion system. The device includes a digital interpolation filter followed by an oversampled 5 bit delta-sigma modulator which drives second generation dynamic-element-matching (DEM) selection logic. The output from the DEM block controls the input to a multi-element switched capacitor DAC/low- pass filter, with fully-differential outputs. This multi-bit ar- chitecture features significantly lower out-of-band noise and jitter sensitivity than traditional 1-bit designs, and the advanced second generation DEM guarantees low noise and distortion at all signal levels. The CS43122 is the optimal D/A converter solution for any application that requires the highest performance and best possible sound quality including high-end con- sumer and professional audio products such as Universal DVD players, A/V receivers, Outboard D/A Converters, CD Players, and Mixing Consoles.
ORDERING INFORMATION
CS43122-KS -10° to 70° C 28-pin SOIC CDB43122 Evaluation Board SCLK MCLK LRCK SDATA AOUTL+ AOUTR+ SERIAL INTERFACE AND FORMAT SELECT INTERPOLATION SOFT MUTE ΔΣ MODULATOR DYNAMIC DE-EMPHASIS SWITCHED AOUTL- AOUTR- FILT+ FILTER INTERPOLATION FILTER FILTER MULTI-BIT ΔΣ MODULATOR MULTI-BIT ELEMENT MATCHING LOGIC DYNAMIC ELEMENT MATCHING LOGIC CAPACITOR-DAC AND FILTER SWITCHED CAPACITOR-DAC AND FILTER VREF CMOUTFILT- VOLTAGE REFERENCE HARDWARE MODE CONTROL CLOCK DIVIDER (CONTROL PORT) (AD0/CS) M3 M2 (AD1/CDIN) (SCL/CCLK) M1 M0 (SDA/CDOUT) RESET MUTEC MUTE DEC ‘00 DS526PP2
Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some
- CHARACTERISTICS/SPECIFICATIONS ANALOG CHARACTERISTICS (TA = 25° C; Logic "1" = VD = 3 V; VA = 5.5 V;VREF=5.5 V Logic "0" = DGND;Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; SCLK = 3.072 MHz; Measurement Band- width 10 Hz to 20 kHz, unless otherwise specified. Test load = RL = 1kΩ , CL = 10 pF) Parameter Symbol Min Typ Max Unit Dynamic Performance - Operational Mode 1 (Fs = 48 kHz) Dynamic Range (Note 1) 24-Bit unweighted A-Weighted 16-Bit unweighted (Note 2) A-Weighted TBD TBD 119 122 dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB (Note 2) -20 dB -60 dB THD+N -102 -99 -59 -95 -75 -35 TBD TBD TBD dB dB dB dB dB dB
ANALOG CHARACTERISTICS (CONTINUED) Parameter Symbol Min Typ Max Unit Dynamic Performance - Operational Mode 0 (Fs = 48 kHz) Dynamic Range (Note 1) 24-Bit unweighted A-Weighted 16-Bit unweighted (Note 2) A-Weighted TBD TBD 117 120 dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB (Note 2) -20 dB -60 dB THD+N -100 -97 -55 -95 -75 -35 TBD TBD TBD dB dB dB dB dB dB Dynamic Performance - Operational Mode 1 (Fs = 96 kHz) Dynamic Range (Note 1) 24-Bit unweighted A-Weighted 40 kHz bandwidth unweighted 16-Bit unweighted (Note 2) A-Weighted TBD TBD TBD 117 120 114 dB dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB (Note 2) -20 dB -60 dB THD+N -100 -97 -55 -95 -75 -35 TBD TBD TBD dB dB dB dB dB dB Dynamic Performance - Operational Mode 2 (Fs = 192 kHz) Dynamic Range (Note 1) 24-Bit unweighted A-Weighted 40 kHz bandwidth unweighted 16-Bit unweighted (Note 2) A-Weighted TBD TBD TBD 117 120 114 dB dB dB dB dB Total Harmonic Distortion + Noise (Note 1) 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB (Note 2) -20 dB -60 dB THD+N -100 -97 -55 -95 -75 -35 TBD TBD TBD dB dB dB dB dB dB
ANALOG CHARACTERISTICS (CONTINUED) Notes: 1. Triangular PDF dithered data. 2. Performance limited by 16-bit quantization noise. 3. Valid with the recommended capacitor values on FILT+ and CMOUT as shown in Figure 1. Increasing the capacitance will also increase the PSRR. Parameter Symbol VD = 3 V VD = 5 V Unit Power Supplies Min Typ Max Min Typ Max Supply Current normal operation VA = 5 .0V normal operation power-down state IA ID ID + IA TBD - TBD mA mA µA Power Dissipation normal operation VA = 5 .0V power-down 166 0.3 TBD 205 0.3 TBD mW mW Power Supply Rejection Ratio (1 kHz) (Note 3) (120 Hz) PSRR - dB dB Parameter Symbol Min Typ Max Unit Analog Output Full Scale Differential Output Voltage TBD 1.33VREF TBD Vpp Common Mode Voltage - 0.5VREF - VDC Interchannel Gain Mismatch - 0.1 - dB Gain Drift - 100 - ppm/°C Differential DC Offset - 2.0 TBD mV AC-Load Resistance R L 1.0 - - k Ω Load Capacitance C L -- 1 0 0 p F Interchannel Isolation (1 kHz) - 90 - dB
ANALOG CHARACTERISTICS (Continued) Notes: 4. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 7-18) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 5. For Operational Mode 0, the Measurement Bandwidth is 0.5465 Fs to 1.4 Fs. For Operational Mode 1, the Measurement Bandwidth is 0.570 Fs to 1.4 Fs. For Operational Mode 2, the Measurement Bandwidth is 0.635 Fs to 1.3 Fs. 6. Group Delay for Fs=48 kHz 37/48 kHz=770µs 7. De-emphasis is available only in Operational Mode 0. Parameter Symbol Min Typ Max Unit Combined Digital and On-chip Analog Filter Response - Operational Mode 0 Passband (Note 4) to -0.1 dB corner to -3 dB corner 0.470 0.492 Fs Fs Frequency Response 10 Hz to 20 kHz -.020 - +0.015 dB Passband Ripple - - ±0.0001 dB StopBand .5465 - - Fs StopBand Attenuation (Note 5) 102 - - dB Group Delay (Note 6) tgd - 37/Fs - s De-emphasis Error (Note 7) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz ±0.10 ±0.10 ±0.13 dB dB dB Combined Digital and On-chip Analog Filter Response - Operational Mode 1 Passband (Note 4) to -0.1 dB corner to -3 dB corner 0.448 0.486 Fs Fs Frequency Response 10 Hz to 20 kHz -0.017 - 0.035 dB Passband Ripple - - ±0.0008 dB StopBand .570 - - Fs StopBand Attenuation (Note 5) 82 - - dB Group Delay tgd - 20/Fs - s Combined Digital and On-chip Analog Filter Response - Operational Mode 2 Passband (Note 4) to -0.1 dB corner to -3 dB corner 0.385 0.472 Fs Fs Frequency Response 10 Hz to 20 kHz 0 - +0.015 dB Passband Ripple - - ±0.00065 dB StopBand 0.635 - - Fs StopBand Attenuation (Note 5) 83 - - dB Group Delay tgd - 11/Fs - s
DIGITAL CHARACTERISTICS (TA = 25° C; VD = 3.0 V - 5.25 V) ABSOLUTE MAXIMUM RATINGS (AGND = 0 V, all voltages with respect to ground.) WARNING: WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (DGND = 0V; all voltages with respect to ground) Parameters Symbol Min Typ Max Units High-Level Input Voltage VD = 5 V VD = 3 V VIH 2.0 2.0 V V Low-Level Input Voltage VD = 5 V VD = 3 V VIL - 0.8 0.8 V V Input Leakage Current I in -- ± 1 0 µA Input Capacitance - 8 - pF Maximum MUTEC Drive Current - 3 - mA Parameter Symbol Min Max Unit DC Power Supply: Positive Analog Positive Digital Reference Voltage VA VD VREF -0.3 -0.3 -0.3 6.0 6.0 VA V V V Input Current, Any Pin Except Supplies I in -± 1 0 m A Digital Input Voltage V IND -0.3 (VD)+0.4 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Parameter Symbol Min Typ Max Unit DC Power Supply: Positive Digital Positive Analog Reference Voltage VD VA VREF 3.0 5.25 5.25 3.3 5.5 5.5 5.25 5.75 VA V V V Specified Temperature Range T A -10 - 70 °C
Figure 1. Serial Audio Input Timing
Notes: 8. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
2 Wire Mode
Figure 2. 2 Wire Mode Control Port Timing
Notes: 9. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
- Data must be held for sufficient time to bridge the transition time of CCLK.
Figure 3. SPI Control Port Timing
- TYPICAL CONNECTION DIAGRAM
Figure 4. Typical Connection Diagram
- REGISTER DESCRIPTION
3.1 MODE CONTROL REGISTER (ADDRESS 01H)
4.11 Differential DC offset calibration (CAL)
Default = 0 0 - Disabled 1 - Enabled Function: Enabling this function will initiate a calibration to minimize the differential DC offset. This function will be automatically reset following completion of the calibration sequence.
4.12 Soft Mute (MUTE)
Default = 0 0 - Disabled 1 - Enabled Function: The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cycles in Operational Mode 0, 2304 cycles in Operational Mode 1 and 4608 cycles in Operational Mode 2 . The bias voltage on the outputs will be retained and MUTEC will go low at the completion of the ramp period. The analog outputs will ramp to a normal state when this function transitions from the enabled to dis- abled state. The ramp requires 1152 left/right clock cycles in Operational Mode 0, 2304 cycles in Op- erational Mode 1 and 4608 cycles in Operational Mode 2 . The MUTEC will go high immediately on disabling of MUTE.
4.13 Mode Select (M4-M0)
Default = 00000 Function: The Mode Select pins determine the operational mode of the device as detailed in Tables 4-7. The options include: Selection of the Digital Interface Format which determines the required relationship between the Left/Right clock, serial clock and serial data as detailed in Figures 20-23 Selection of the standard 15µs/50µs digital de-emphasis filter response, Figure 28, which requires re- configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. Selection of the appropriate operational clocking mode to match the input sample rates. 76543210 CAL MUTE M4 M3 M2 M1 M0 PDN 00 000000
4.14 Power Down (PDN)
Default = 1 0 - Disabled 1 - Enabled Function: The analog and digital sections will be placed into a power-down mode when this function is enabled. This bit must be cleared to resume normal operation.
- PIN DESCRIPTION RST 1 Reset (Input) - The device enters a low power mode and all internal state machines registers are reset when low. When high, the device will be in a normal operation mode. DGND 6, 9 Digital Ground (Input) - Digital ground reference. VD 7, 8 Digital Power (Input) - Digital power supply. Typically 3.0 to 5.0 VDC. Reset RST VREF Voltage Reference See Description M4(AD0/CS ) FILT+ Reference Filter See Description M3(AD1/CDIN) FILT- Reference Ground See Description M2(SCL/CCLK) CMOUT Common ModeS Voltage See DescriptionM0(SDA/CDOUT) AOUTL- Differential Output Digital Ground DGND AOUTL+ Differential Output Digital Power VD VA Analog Power Digital Power VD AGND Analog Ground Digital Ground DGND AOUTR+ Differential Output Master Clock MCLK AOUTR- Differential Output Serial Clock SCLK AGND Analog Ground Left/Right Clock LRCK MUTEC Mute Control Serial Data SDATA C/H Control port/Hardware select See Description M1 MUTE Soft Mute
sample rates and the required master clock frequencies. in Hardware Mode. The options are detailed in Figures 20-23.
12 Left/Right Clock (Input) - The Left/Right clock determines which channel is cur-
the Mode Control Byte and the options are detailed in Figures 20-23.
13 Serial Audio Data (Input) - Two's complement MSB-first serial data is input on
and the options are detailed inin Figures 20-23. Table 1. Operational Mode 0 (16 to 55 kHz sample rates) Common Clock Table 2. Operational Mode 1 (45 to 105 kHz sample rates) Common Clock Table 3. Operational Mode 2 (95 to 200 kHz sample rates) Common Clock
MUTE 15 Soft Mute (Input) - The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cycles in Operational Mode 0, 2304 cycles in Operational Mode 1 and 4608 cycles in Operational Mode 2 . The bias voltage on the outputs will be retained and MUTEC will go active at the completion of the ramp period. The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled state. The ramp requires 1152 left/right clock cycles in Operational Mode 0, 2304 cycles in Operational Mode 1 and 4608 cycles in Oper- ational Mode 2 . The MUTEC will release immediately on setting MUTE = 1. The converter analog outputs will mute when enabled. The bias voltage on the outputs will be retained and MUTEC will go active during the mute period C/H 16 Control Port / Hardware Mode Select (Input) - Determines if the device will oper- ate in either the Hardware Mode or Control Port Mode. MUTEC 17 Mute Control (Output) - The Mute Control pin goes low during power-up initializa- tion, reset, muting, master clock to left/right clock frequency ratio is incorrect or power-down. This pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. AGND 18, 21 Analog Ground (Inputs) - Analog ground reference. AOUTR- , AOUTR+ AOUTL- , AOUTL+ 19, 20, 23, 24 Differential Analog Outputs (Outputs) - The full scale differential analog output level is specified in the Analog Characteristics specifications table. VA 22 Analog Power (Input) - Power for the analog and reference circuits. Typically 5.5 VDC. CMOUT 25 Common Mode Voltage (Output) - Filter connection for internal bias voltage, typ- ically 50% of VREF. Capacitors must be connected from CMOUT to analog ground, as shown in the Typical Connection Diagram. CMOUT has a typical source impedence of 25 kΩ and any current drawn from this pin will alter device performance. FILT- 26 Reference Ground (Input) - Ground reference for the internal sampling circuits. Must be connected to analog ground. FILT+ 27 Reference Filter (Output) - Positive reference for internal sampling circuits. Exter- nal capacitors are required from FILT+ to analog ground, as shown in the Typical Connection Diagram. The recommended values will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 120 Hz. FILT+ is not intended to supply external current. VREF 28 Voltage Reference Input (Input) - Analog voltage reference. Typically 5.5 VDC. M0, M1, M2, M3, M4 (Hardware Mode) 2, 3, 4, 5,14 Mode Select (Inputs) - The Mode Select pins determine the operational mode of the device as detailed in Tables 4-7. The options include; Selection of the Digital Interface Format which determines the required relation- ship between the Left/Right clock, serial clock and serial data as detailed in Fig- ures 20-23Selection of the standard 15µs/50µs digital de-emphasis filter response, Figure 28, which requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates. Selection of the appropriate clocking mode to match the input sample rates. AD0 / CS (Control Port Mode) 2 Address Bit 0 / Chip Select (Input) - In 2 wire mode, AD0 is a chip address bit. CS is used to enable the control port interface in SPI mode. The device will enter the SPI mode at anytime a high to low transition is detected on this pin. Once the device has entered the SPI mode, it will remain until either the part is reset or undergoes a power-down cycle.
(Control Port Mode)
3 Address Bit 1 / Control Data Input (Input) - In 2 Wire Mode, AD1 is a chip
address bit. CDIN is the control data input line for the control port interface in SPI mode. SCL/CCLK (Control Port Mode)
4 Serial Control Interface Clock (Input) - In 2 Wire Mode, SCL clocks the serial
control data into or from SDA/CDOUT. In SPI mode, CCLK clocks the serial data into AD1/CDIN and out of SDA/CDOUT. SDA/CDOUT (Control Port Mode)
5 Serial Control Data I/O (Input/Output) - In 2 Wire Mode, SDA is a data input/out-
put. CDOUT is the control data output for the control port interface in SPI mode. (Control Port Mode)
14 Mode Select (Input) - This pin is not used in Control Port Mode and must be termi-
nated to ground.
- APPLICATIONS
5.1 Recommended Power-up Sequence
1) Hold RST high until the power supplies, master clock, and left/right clock are stable. 2) Bring RST high. 6. CONTROL PORT INTERFACE The control port is used to load all the internal set- tings of the CS43122. The operation of the control port may be completely asynchronous to the audio sample rate. However, to avoid potential interfer- ence problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and “2 wire”, with the CS43122 operating as a slave device in both modes. If 2 wire operation is desired, AD0/CS should be tied to VD or DGND. If the CS43122 ever detects a high to low transition on AD0/CS af- ter power-up, SPI mode will be selected.
6.1 SPI Mode
In SPI mode, CS is the CS43122 chip select signal, CCLK is the control port bit clock, CDIN is the in- put data line from the microcontroller, CDOUT is the data output and the chip address is 0010000. The data is clocked on the rising edge of CCLK. Figure 5 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write in- dicator (R/W ). The next 8 bits form the Memory Address Pointer (MAP), which is set to 01h. The next 8 bits are the data which will be placed into the register designated by the MAP. 6.2 2 Wire Mode In 2 Wire M ode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 2. There is no CS pin. Pins AD0 and AD1 form the partial chip address and should be tied to VD or DGND as required. The 7-bit address field, which is the first byte sent to the CS43122, must be 00100(AD1)(AD0) where (AD1) and (AD0) match the setting of the AD0 and AD1 pins. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. If the op- eration is a read, then the contents of the register pointed to by the MAP will be output after the chip address.
6.3 Memory Address Pointer (MAP)
Figure 5. Control Port Timing, SPI mode
001000 ADDR
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. Figure 6. Control Port Timing, 2 wire Mode
Table 4. Operational Mode 0 (16 to 55 kHz) Digital Interface Format Options Table 5. Operational Mode 0 (16 to 55 kHz) De-Emphasis Options
11100 L e f t J u s t i f i e d u p t o 2 4 - b i t d a t a , F o r m a t 0
11110 R i g h t J u s t i f i e d 1 6 - b i t d a t a , F o r m a t 2
11111 R i g h t J u s t i f i e d 2 4 - b i t d a t a , F o r m a t 3
Table 6. Operational Mode 1 (45 to 105 kHz) Sample Rate Mode Options
11000 L e f t J u s t i f i e d u p t o 2 4 - b i t d a t a , F o r m a t 0
11010 R i g h t J u s t i f i e d 1 6 - b i t d a t a , F o r m a t 2
11011 R i g h t J u s t i f i e d 2 4 - b i t d a t a , F o r m a t 3
Table 7. Operational Mode 2 (95 to 200 kHz) Sample Rate Mode Options
- PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering So- ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 8. REFERENCES 1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB43122 Evaluation Board Datasheet
- PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX JEDEC #: MS-013 Controling Dimension is Millimeters 28L SOIC (300 MIL BODY) PACKAGE DRAWING D HE b A c L SEATING PLANE e
- Notes •