CS42436-DMZ

CS42436_06 CIRRUS | Alldatasheet

Document overview

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Technical content

Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved)http://www.cirrus.com AUGUST '06 DS647F1 108 dB, 192 kHz 6-In, 6-Out TDM CODEC

FEATURES

 Six 24-bit A/D, Six 24-bit D/A Converters  ADC Dynamic Range – 105 dB Differential – 102 dB Single-Ended  DAC Dynamic Range – 108 dB Differential – 105 dB Single-Ended  ADC/DAC THD+N – -98 dB Differential – -95 dB Single-Ended  Compatible with Industry-Standard Time Division Multiplexed (TDM) Serial Interface  DAC Sampling Rates up to 192 kHz  ADC Sampling Rates up to 96 kHz  Programmable ADC High-Pass Filter for DC Offset Calibration  Logarithmic Digital Volume Control  Hardware Mode or Software I²C® & SPI™  Supports Logic Levels Between 5 V and 1.8 V GENERAL DESCRIPTION The CS42436 CODEC provides six multi-bit analog-to- digital and six multi-bit digital-to-analog delta-sigma converters. The CODEC is capable of operation with ei- ther differential or single-ended inputs and outputs, in a 52-pin MQFP package. Six fully differential, or si ngle-ended, inputs are avail- able on stereo ADC1, ADC2, and ADC3. When operating in Single-ended Mode, an internal MUX be- fore ADC3 allows selection from up to four single-ended inputs. Digital volume control is provided for each ADC channel, with selectable overflow detection. All six DAC channels provide digital volume control and can operate with differential or single-ended outputs. An auxiliary serial input is available for an additional two channels of PCM data. The CS42436 is available in a 52-pin MQFP package in Commercial (-10° to +70°) and Automotive (-40° to +105°) grades. The CDB42436 Customer Demonstra- tion board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 61 for complete ordering information. The CS42436 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and automotive audio systems. Control Port & Serial Audio Port Supply =

1.8 V to 5 V

Level TranslatorLevel Translator TDM Serial Audio Input Digital Supply = 3.3 V Hardware Mode or I2C/SPI Software Mode Control Data Analog Supply =

3.3 V to 5 V

ADC1&2 High Pass Filter Differential or Single-Ended Analog Inputs 4Digital Filters *Optional MUX allows selection from up to 4 single-ended inputs. Multibit Oversampling ADC3 High Pass Filter 2Digital Filters 4:2* Auxilliary Serial Audio Input Volume Controls Digital Filters Multibit DAC1-3 and Analog Filters ΔΣ Modulators CS42436

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1. PIN DESCRIPTIONS - SOFTWARE MODE Pin Name # Pin Description SCL/CCLK 1 Serial Control Port Clock (Input) - Serial clock for the control port interface. SDA/CDOUT 2 Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Output for SPI data. AD0/CS 3 Address Bit [0]/ Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select the chip in SPI Mode. AD1/CDIN 4 Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I²C Mode. Input for SPI data. RST 5 Reset (Input) - The device enters a low-power mode and all internal registers are reset to their default settings when low. VLC 6 Control Port Power (Input) - Determines the required signal level for the control port interface. See “Digital I/O Pin Characteristics” on page 8. FS 7 Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. VD 8 Digital Power (Input) - Positive power supply for the digital section. DGND 9,18 Digital Ground (Input) - Ground reference for the digital section. VLS 10 Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter- faces. See “Digital I/O Pin Characteristics” on page 8. SCLK 11 Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs. MCLK 12 Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters. ADC_SDOUT 13 Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data. DAC_SDIN 14 DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data. AUX_LRCK 15 Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line. SCL/CCLK 14 15 16 17 18 19 20 21 22 23 24 25 52 51 50 49 48 47 46 45 44 43 42 41 VLS FS MCLK VLC AD1/CDIN TSTO AOUT5+ AOUT3+ AGND VA AUX_SDIN DAC_SDIN ADC_SDOUT AUX_SCLK AUX_LRCK AD0/CS AOUT4+ RST AOUT6+ AOUT3- AOUT2+ AOUT2- AOUT1- AOUT1+ DGND VD SCLK DGND VQ AOUT6- AOUT4- SDA/CDOUT AOUT5- TSTO TSTO TSTO FILT+ VA AGND AIN6+/AIN6A AIN6-/AIN6B AIN3+ AIN4- AIN4+ AIN5-/AIN5B AIN3- AIN5+/AIN5A AIN2- AIN2+ AIN1+ AIN1- 42436

AUX_SCLK 16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. AUX_SDIN 17 Auxiliary Serial Input (Input) - The 42436 provides an additional serial input for two’s comple- ment serial audio data. AOUT1 +,- AOUT2 +,- AOUT3 +,- AOUT4 +,- AOUT5 +,- AOUT6 +,- 20,19 21,22 24,23 25,26 28,27 29,30 Differential Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. Each positive leg of the differential outputs may also be used single-ended. TSTO 31,32 33,34 Test Out - These pins are outputs used for test purposes only. They must not be connected to any external trace or other connection. AGND 35,48 Analog Ground (Input) - Ground reference for the analog section. VQ 36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. VA 37,46 Analog Power (Input) - Positive power supply for the analog section. AIN1 +,- AIN2 +,- AIN3 +,- AIN4 +,- AIN5 +,- AIN6 +,- 39,38 41,40 43,42 45,44 50,49 52,51 Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula- tors. The full-scale input level is specified in the Analog Characteristics specification table. Single- ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled. Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to common mode. See below for a description of AIN5-AIN6 in Single-Ended Mode. AIN5 A,B AIN6 A,B 50,49 52,51 Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows selection between two channels for both analog inputs AIN and AIN (see Sections 7.6.6-7.6.8 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table. FILT+ 47 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir- cuits.

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1.1 Digital I/O Pin Characteristics

should adhere to the corresponding power rail and should not exceed the maximum ratings. Table 1. I/O Power Rails

1. PIN DESCRIPTIONS - HARDWARE MODE Pin Name # Pin Description SCL/CCLK 1 Serial Control Port Clock (Input) - Serial clock for the control port interface. SDA/CDOUT 2 Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Output for SPI data. AD0/CS 3 Address Bit [0]/ Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select the chip in SPI Mode. AD1/CDIN 4 Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I²C Mode. Input for SPI data. RST 5 Reset (Input) - The device enters a low-power mode and all internal registers are reset to their default settings when low. VLC 6 Control Port Power (Input) - Determines the required signal level for the control port interface. See “Digital I/O Pin Characteristics” on page 8. FS 7 Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. VD 8 Digital Power (Input) - Positive power supply for the digital section. DGND 9,18 Digital Ground (Input) - Ground reference for the digital section. VLS 10 Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter- faces. See “Digital I/O Pin Characteristics” on page 8. SCLK 11 Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs. MCLK 12 Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters. ADC_SDOUT 13 Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data. DAC_SDIN 14 DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data. AUX_LRCK 15 Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line. AIN5_MUX 14 15 16 17 18 19 20 21 22 23 24 25 52 51 50 49 48 47 46 45 44 43 42 41 VLS FS MCLK VLC ADC3_HPF FILT+ TSTO AOUT5+ AOUT3+ AGND VA AUX_SDIN DAC_SDIN ADC_SDOUT/ ADC3_SINGLE AUX_SCLK AUX_LRCK MFREQ AOUT4+ RST AOUT6+ AOUT3- VA AGND AOUT2+ AOUT2- AOUT1- AOUT1+ DGND VD SCLK DGND VQ AIN6+/AIN6A AIN6-/AIN6B AOUT6- AOUT4- AIN6_MUX AOUT5- TSTO TSTO TSTO AIN3+ AIN4- AIN4+ AIN5-/AIN5B AIN3- AIN5+/AIN5A AIN1+ AIN2- AIN2+ AIN1- 42436

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AUX_SCLK 16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. AUX_SDIN 17 Auxiliary Serial Input (Input) - The 42436 provides an additional serial input for two’s comple- ment serial audio data. AOUT1 +,- AOUT2 +,- AOUT3 +,- AOUT4 +,- AOUT5 +,- AOUT6 +,- 20,19 21,22 24,23 25,26 28,27 29,30 Differential Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. Each positive leg of the differential outputs may also be used single-ended. TSTO 31,32 33,34 Test Out - These pins are outputs used for test purposes only. They must not be connected to any external trace or other connection. AGND 35,48 Analog Ground (Input) - Ground reference for the analog section. VQ 36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. VA 37,46 Analog Power (Input) - Positive power supply for the analog section. AIN1 +,- AIN2 +,- AIN3 +,- AIN4 +,- AIN5 +,- AIN6 +,- 39,38 41,40 43,42 45,44 50,49 52,51 Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula- tors. The full-scale input level is specified in the Analog Characteristics specification table. Single- ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled. Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to common mode. See below for a description of AIN5-AIN6 in Single-Ended Mode. AIN5 A,B AIN6 A,B 50,49 52,51 Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows selection between two channels for both analog inputs AIN and AIN (see Sections 7.6.6-7.6.8 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table. FILT+ 47 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir- cuits.

1. TYPICAL CONNEC TION DIAGRAMS
2. See the ADC Input Filter section in the Appendix.
3. See the DAC Output Filter section in the Appendix.

Figure 1. Typical Connection Diagram (Software Mode)

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1. See the ADC Input Filter section in the Appendix.
2. See the DAC Output Filter section in the Appendix.

Figure 2. Typical Connection Diagram (Hardware Mode)

1. CHARACTERISTICS AN D SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) WARNING: Operation at or beyond these limit s may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Typical Analog input/out put performance will slightly degrade at VA = 3.3 V. 2. The ADC_SDOUT may not meet timing requirements in Double-Speed Mode. 3. Any pin except supplies. Transien t currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 4. The maximum over/under voltage is limited by the input current. Parameters Symbol Min Max Units DC Power Supply Analog (Note 1) VA 3.14 5.25 V Digital VD 3.14 3.47 V Serial Audio Interface (Note 2) VLS 1.71 5.25 V Control Port Interface VLC 1.71 5.25 V Ambient Temperature Commercial -CMZ Automotive -DMZ T A -10 -40 +70 +105 Parameters Symb ol Min Max Units DC Power Supply Analog Digital Serial Port Interface Control Port Interface VA VD VLS VLC -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 V V V V Input Current (Note 3) I in -± 1 0 m A Analog Input Voltage (Note 4) VIN AGND-0.7 VA+0.7 V Digital Input Voltage Serial Port Interface (Note 4) Control Port Interface VIND-S VIND-C -0.3 -0.3 VLS+ 0.4 VLC+ 0.4 V V Ambient Operating Temperature (power applied) TA -50 +125 °C Storage Temperature T stg -65 +150 °C

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ANALOG INPUT CHARACTERISTICS (COMMERCIAL) (Test Conditions (unless otherwise specified): TA =- 1 0 t o + 7 0°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 20 on page 50 and Figure 21 on page 50; Measurement Bandwidth is 10 Hz to 20 kHz.) Differential Single-Ended Parameter Min Typ Max Min Typ Max Unit Fs=48 kHz, 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 105 102 102 dB dB dB Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB 40 kHz bandwidth -1 dB -98 -82 -42 -90 -92 -95 -79 -39 -90 -89 dB dB dB dB ADC1-3 Interchannel Isolation - 90 - - 90 - dB ADC3 MUX Interchannel Isolation - 90 - - 90 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Gain Drift - ±100 - - ±100 - ppm/°C Analog Input Differential Input Impedance (Note 6) 18 - - - - - k Ω Single-Ended Input Impedance (Note 7) --- 1 8 -- k Ω Common Mode Rejection Ratio (CMRR) - 82 - - - - dB

ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE) (Test Conditions (unless otherwise specified): TA = -40 to +85°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 20 on page 50 and Figure 21 on page 50; Measurement Bandwidth is 10 Hz to 20 kHz.) Notes: 5. Referred to the typical full-scale voltage. 6. Measured between AINx+ and AINx-. 7. Measured between AINxx and AGND. Differential Single-Ended Parameter Min Typ Max Min Typ Max Unit Fs=48 kHz, 96 kHz Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 105 102 102 dB dB dB Total Harmonic Distortion + Noise -1 dB (Note 5) -20 dB -60 dB 40 kHz bandwidth -1 dB -98 -82 -42 -87 -90 -95 -79 -39 -87 -87 dB dB dB dB ADC1-3 Interchannel Isolation - 90 - - 90 - dB ADC3 MUX Interchannel Isolation - 85 - - 85 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Gain Drift - ±100 - - ±100 - ppm/°C Analog Input Differential Input Impedance (Note 6) 18 - - - - - k Ω Single-Ended Input Impedance (Note 7) --- 1 8 -- k Ω Common Mode Rejection Ratio (CMRR) - 82 - - - - dB

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ADC DIGITAL FILTER CHARACTERISTICS Notes: 8. Filter response is guaranteed by design. 9. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 26 to 33) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. Parameter (Notes 8, 9) Min Typ Max Unit Single-Speed Mode (Note 9) Passband (Frequency Response) to -0.1 dB corner 0 - 0.4896 Fs Passband Ripple - - 0.08 dB Stopband 0.5688 - - Fs Stopband Attenuation 70 - - dB Total Group Delay - 12/Fs - s Double-Speed Mode (Note 9) Passband (Frequency Response) to -0.1 dB corner 0 - 0.4896 Fs Passband Ripple - - 0.16 dB Stopband 0.5604 - - Fs Stopband Attenuation 69 - - dB Total Group Delay - 9/Fs - s High-Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB Hz Hz Phase Deviation @ 20 Hz - 10 - Deg Passband Ripple - - 0 dB Filter Settling Time - 10 5/Fs 0 s

ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL) (Test Conditions (unless otherwise specified): TA = -10 to +70°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale 997 Hz output sine wave (see Note 11) into passive filter in Figure 26 on page 54 and active filter in Fig- ure 26 on page 54; Measurement Bandwidth is 10 Hz to 20 kHz.) Parameter Differential Min Typ Max Single-Ended Min Typ Max Unit Fs = 48 kHz, 96 kHz, 192 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 102 108 105 105 102 dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -98 -85 -45 -93 -76 -36 -92 -95 -82 -42 -90 -73 -33 -89 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 100 - - 100 - dB Analog Output Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB Gain Drift - ±100 - - ±100 - ppm/°C Output Impedance - 100 - - 100 - Ω DC Current draw from an AOUT pin (Note 10) -- 1 0 - - 1 0 μA AC-Load Resistance (R L) (Note 12) 3-- 3 - - k Ω Load Capacitance (CL) (Note 12) - - 100 - - 100 pF

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ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE) (Test Conditions (unless otherwise specified): TA =- 4 0 t o + 8 5°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%; Full-scale 997 Hz output sine wave (see Note 11) in Figure 26 on page 54 and Figure 26 on page 54; Measure- ment Bandwidth is 10 Hz to 20 kHz.) Notes: 10. Guaranteed by design. The DC current draw repres ents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC-blocking capacitors. 11. One-half LSB of triangular PDF dither is added to data. 12. Guaranteed by design. See 3. R L and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integr ity. In this circuit topology, C L will effectively move the dominant po le of the two-pole amp in the ou tput stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. See “External Filters” on page 50 for a recommended output filter. Parameter Differential Min Typ Max Single-Ended Min Typ Max Unit Fs = 48 kHz, 96 kHz, 192 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 100 108 105 105 102 dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB -98 -85 -45 -93 -76 -36 -90 -95 -82 -42 -90 -73 -33 -87 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - 100 - - 100 - dB Analog Output Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB Gain Drift - ±100 - - ±100 - ppm/°C Output Impedance - 100 - - 100 - Ω DC Current draw from an AOUT pin (Note 10) - - 10 - - 10 μA AC-Load Resistance (R L) (Note 12) 3-- 3 - - k Ω Load Capacitance (CL) (Note 12) - - 100 - - 100 pF

Figure 3. Output Test Load Figure 4. Maximum Loading

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COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Notes: 13. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 34 to 45) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 14. Single- and Double-Speed Mode Measurement Bandwidth is from Stopband to 3 Fs. Quad-Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs. 15. De-emphasis is only available in Single-Speed Mode. Parameter (Notes 8, 13) Min Typ Max Unit Single-Speed Mode Passband (Frequency Response) to -0.05 dB corner to -3 dB corner 0.4780 0.4996 Fs Fs Frequency Response 10 Hz to 20 kHz -0.2 - +0.08 dB StopBand 0.5465 - - Fs StopBand Attenuation (Note 14) 50 - - dB Group Delay - 10/Fs - s De-emphasis Error (Note 15) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz +1.5/+0 +0.05/-0.25 -0.2/-0.4 dB dB dB Double-Speed Mode Passband (Frequency Response) to -0.1 dB corner to -3 dB corner 0.4650 0.4982 Fs Fs Frequency Response 10 Hz to 20 kHz -0.2 - +0.7 dB StopBand 0.5770 - - Fs StopBand Attenuation (Note 14) 55 - - dB Group Delay - 5/Fs - s Quad-Speed Mode Passband (Frequency Response) to -0.1 dB corner to -3 dB corner 0.397 0.476 Fs Fs Frequency Response 10 Hz to 20 kHz -0.2 - +0.05 dB StopBand 0.7 - - Fs StopBand Attenuation (Note 14) 51 - - dB Group Delay - 2.5/Fs - s

1. After powering up the CS42436, RST should be held low after the power supplies and clocks are settled.
2. See Table 7 on page 43 for suggested MCLK frequencies.
3. VLS is limited to nominal 2.5 V to 5.0 V operation only.
4. ADC does not meet timing spec ification for Quad-Speed Mode.

Figure 5. TDM Serial Audio Interface Timing

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Figure 6. Serial Audio Interface Slave Mode Timing

1. Data must be held for sufficient ti me to bridge the transition time, tfc, of SCL.

Figure 7. Control Port Timing - I²C Format

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1. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 8. Control Port Timing - SPI Format

DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) Notes: 24. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input to the DAC and AUX port, and a 1 kHz, -1 dB analog input to the ADC port sampled at the highest Fs for each speed mode. DAC outputs are open, unless otherwise specified. 25. I DT measured with no external loading on pin 2 (SDA). 26. Valid with the recommended capa citor values on FILT + and VQ. Increasing the capacitance will also increase the PSRR. 27. Power-Down Mode is defined as RST = LO with all clocks and data lines held static and no analog input. 28. Guaranteed by design. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through the electrolytic de-coupling capacitors. DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS Notes: 29. See “Digital I/O Pin Characteristics” on page 8 for serial and control port power rails. Parameters Symbol Min Typ Max Units Normal Operation (Note 24) Power Supply Current VA = 5.0 V VLS = VLC = VD = 3.3 V (Note 25) IA IDT 60.6 mA mA Power Dissipation VLS = VLC = VD = 3.3 V, VA = 5 V - 600 850 mW Power Supply Rejection Ratio 1 kHz (Note 26) 60 Hz PSRR - dB dB Power-Down Mode (Note 27) Power Dissipation VLS = VLC = VD = 3.3 V, VA = 5 V - 1.25 - mW VQ Characteristics Nominal Voltage Output Impedance DC Current Source/Sink (Note 28) 0.5•VA V kΩ μA FILT+ Nominal Voltage - VA - V Parameters (Note 29) Symbol Min Typ Max Units High-Level Output Voltage at I o=2 mA Serial Port Control Port V OH VLS-1.0 VLC-1.0 V V Low-Level Output Voltage at Io=2 mA Serial Port Control Port VOL 0.4 0.4 V V High-Level Input Voltage Serial Port Control Port V IH 0.7xVLS 0.7xVLC V V Low-Level Input Voltage Serial Port Control Port V IL 0.2xVLS 0.2xVLC V V Leakage Current I in -- ± 1 0 μA Input Capacitance (Note 21) - - 10 pF

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5.1 Overview

also implemented using multi-bit delta-sigma techniques. filters, and an on-chip voltage reference,. Digital Interface Formats” on page 34 for details. ADC). Note: QSM is only available in Software Mode (see “System Clocking” on page 33 for details). limited basis. See Table 2 for the default configuration in Hardware Mode. settings and options in Software Mode. Table 2. Hardware Configurable Settings

5.2 Analog Inputs

5.2.1 Line-Level Inputs

AINx+ and AINx- are the line-level differential analog inputs internally biased to VQ, approximately VA/2.

5.2.1.1 Hardware Mode

ation is only supported for ADC3. See Section 5.2.2.

5.2.1.2 Software Mode

page 50 for required external components). Table 2. Hardware Configurable Settings (Continued)

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5.2.2 ADC3 Analog Input

selects from up to four single-ended inputs. Figure 9. Full-Scale Input Figure 10. ADC3 Input Topology

5.2.3 Hardware Mode

Single-Ended Mode is selected using a pull-up on the ADC_SDOUT/ADC3_SINGLE pin during startup. Analog input selection is then ma de via the AINx_MUX pins. See Tables 3-4 for ADC3 set-up options. Refer to Figure 10 on page 28 for the internal ADC3 analog input topology.

5.2.4 Software Mode

lections. Refer to Figure 11 on page 31 for the internal ADC3 analog input topology.

5.2.5 High-Pass Filter and DC Offset Calibration

1. Running the CS42436 with the high-pass filter enabl ed until the filter settles. See the Digital Filter

Characteristics for filter settling time.

1. Disabling the high-pass filter and freezing the stored DC offset.

5.2.5.1 Hardware Mode

filter for ADC3 is enabled by driving the ADC3_HPF (pin 4) high.

5.2.5.2 Software Mode

bit in the register “ADC Control & DAC De-Emphasis (Address 05h)” on page 44. Table 3. AIN5 Analog Input Selection Table 4. AIN6 Analog Input Selection

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5.3 Analog Outputs

5.3.1 Initialization

The initialization and Power-Down sequence flow chart is shown in Figure 11 on page 31. The CS42436 enters a power-down state upon initial power-up. Th e interpolation and decima tion filters, delta-sigma modulators and control port registers are reset. The in ternal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and switched-capacitor low-pass filters are powered down. The device remains in the power-down state until the RST pin is brought high. The control port is acces- sible once RST is high, and the desired register settings can be loaded per the interface descriptions in the “Control Port Description and Timing” on page 35. In Hardware Mode operation, the Hardware Mode pins must be set up before RST is brought high. All fe atures will default to the Hardware Mode defaults as listed in Table 2. Once MCLK is valid, VQ will quickl y charge to VA/2, and the internal voltage reference, FILT+, will begin powering up to normal operation. Power is applied to the D/A converters and switched-capacitor filters, and the analog outputs are clamped to the quiescent voltage, VQ. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. After an approximate 2000 sample period delay, normal operation begins.

5.3.2 Line-Level Outputs and Filtering

The CS42436 contains on-chip buffer amplifiers capable of producing line-level differential as well as sin- gle-ended outputs on AOUT1-AOUT 6. These amplifiers are biased to a quiescent DC level of approxi- mately VQ. The delta-sigma conversion process produces high-frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low-pass filter. See “DAC Output Filter” on page 53 for recommended output filter. The active filter configuration accounts for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins. Also shown is a passive filter configuration which minimizes costs and the number of components. Figure 12 shows the full-scale analog output levels. All outputs are internally biased to VQ, approximately VA/2.

1. Audio signal generated per register settings.
2. Aout bias = VA/2 + last audio sample.
3. No audio signal generated.
4. No audio signal generated.

2000 LRCK delay

1. No audio signal generated.
2. Control Port Registers retain
3. No audio signal generated.
4. Control Port Registers reset

Figure 11. Audio Output Initialization Flow Chart

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5.3.3 Digital Volume Control

5.3.3.1 Hardware Mode

DAC Volume Control and Mute are not accessible in Hardware Mode.

5.3.3.2 Software Mode

rate specified by the SZC[1:0] bits.

5.3.4 De-Emphasis Filter

that utilize 50/15 μs pre-emphasis equalization as a means of noise reduction. (DAC_DEM)” on page 44 for de-emphasis control. Figure 12. Full-Scale Output

5.4 System Clocking

The CODEC serial audio interface ports operate as a slave andaccept externally generated clocks. an integer multiple of, and synchronous with, the system sample rate, Fs.

5.4.1 Hardware Mode

The allowable ratios include 256Fs and 512Fs in Single-Speed Mode and 256Fs in Double-Speed Mode.

5.4.2 Software Mode

5.5 CODEC Digital Interface

clocked into the DAC on the rising edge. TDM is the only interface supported in Hardware and Software Mode.

5.5.1 TDM

edge of SCLK. Each time slot is 32 bits wide, with the valid data sample left ‘justified within the time slot. Valid data lengths are 16, 18, 20, or 24. SCLK must operate at 256Fs. FS identifies the start of a new frame and is equal to the sample rate, Fs. Table 5. MCLK Frequency Settings Figure 13. De-Emphasis Curve

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and must be held valid for at least 1 SCLK period. Note: The ADC does not meet the timing requirements for proper operation in Quad-Speed Mode.

5.5.2 I/O Channel Allocation

5.6 AUX Port Digita l Interface Formats

not being used, it should be tied to AGND via a pull-down resistor.

5.6.1 Hardware Mode

5.6.2 Software Mode

5.6.3 I²S

Table 6. Serial Audio Interface Channel Allocations Figure 14. TDM Serial Audio Format Figure 15. AUX I²S Format

5.6.4 Left-Justified

5.7 Control Port Description and Timing

control port pins should remain static if no operation is required. selecting the desired AD0 bit address state.

5.7.1 SPI Mode

state. It may be externally pulled high or low with a 47 kΩ resistor, if desired. after each byte is read or written, allowing block reads or writes of successive registers. as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. Figure 16. AUX Left-Justified Format

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5.7.2 I²C Mode

In I²C Mode, SDA is a bidirectional da ta line. Data is clocke d into and out of the pa rt by the clock, SCL. CS42436 from the microcontroller after each transmitted byte. Figure 17. Control Port Timing in SPI Mode Figure 18. Control Port Timing, I²C Write

dition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send 10010xx0 (chip address & write operation). Send MAP byte, auto increment off. Send stop condition, aborting write. Send 10010xx1(chip address & read operation). Receive byte, contents of selected register. byte is separated by an acknowledge bit.

5.8 Recommended Power-Up Sequence

5.8.1 Hardware Mode

1. Hold RST low until the power supply, clocks and hardware control pins are stable. In this state, the

control port is reset to its default settings and VQ will remain low.

1. Bring RST high. The device will initially be in a low power state with VQ low.
2. The device will initiate the Hard ware Mode power up sequence. All features will default to the

pins. VQ will quick-charge to approximately VA/2 and the analog output bias will clamp to VQ.

1. Following approximately 2000 sample periods, the device is initialized and ready for normal operation.

Figure 19. Control Port Timing, I²C Read

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5.8.2 Software Mode

1. Hold RST low until the power supply and clocks are stable. In this state, the control port is reset to its default settings and VQ will remain low. 2. Bring RST high. The device will initially be in a low power state with VQ low. All features will default as described in the “Register Quick Reference” on page 39. 3. Perform a write operation to the Power Control register ( “Power Control (Address 02h)” on page 42) to set bit 0 to a ‘1’b. This will place the device in a power down state. 4. Load the desired register settings wh ile keeping the PDN bit set to ‘1’b. 5. Mute all DACs. Muting the DACs suppresses any nois e associated with the CODEC's first initialization after power is applied. 6. Set the PDN bit in the power control register to ‘0’b.Following approximately 2000 LRCK cycles, the de- vice is initialized and ready for normal operation. 7. After the CODEC is initialized, wait ~90 LRCK cycles (~1.9 ms @48 kHz) and then unmute the DACs. 8. Normal operation begins.

5.9 Reset and Power-Up

It is recommended that reset be activated if the analog or digital supplies drop below the recommended op- erating condition to prevent power-glitch-related issues. The delta-sigma modulators settle in a matter of mi croseconds after the analog section is powered, either through the application of power or by setting the RST pin high. However, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time delay of approximately 400 ms is requ ired after applying power to the devi ce or after exiting a reset state. During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.

5.10 Power Supply, Gr ounding, and PCB Layout

As with any high-resolution converter, the CS42436 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. Figures 1 and 2 show the recommended power arrangements, with VA connected to clean supplie s. VD, which powers the digital circuitry, may be run from the system logic supply. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42436 as pos- sible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42436 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+, VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and AGND. The CDB42438 evaluation board demo nstrates the optimum layout and power supply arrangements. For optimal heat dissipation from the package, it is recommended that the area directly under the part be filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the back- side ground is also recommended.

1. REGISTER QU ICK REFERENCE Software Mode register defaults are as shown. Note: The default value in all “Reserved” registers must be pre- served. Addr Function 76 5 4 3 2 1 0 01h ID Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0 p4 1 default 0 0 0 0 0 0 0 1 02h Power Con- trol PDN_ADC3 PDN_ADC2 PDN_ADC1 Reserved PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN p4 2 default 0 0 0 0 0 0 0 0 03h Functional Mode Reserved Reserved Reserved Reserved MFreq2 MFreq1 MFreq0 Reserved p4 3 default 1 1 1 1 0 0 0 0 04h Misc Control FREEZE AUX_DIF Reserved Reserved Reserved Reserved Reserved Reserved p4 3 default 0 0 1 1 0 1 10 05h ADC Control (w/DAC_DEM) ADC1-2_HPF FREEZE ADC3_HPF FREEZE DAC_DEM ADC1 SINGLE ADC2 SINGLE ADC3 SINGLE AIN5_MUX AIN6_MUX p4 4 default 0 0 0 0 0 0 0 0 06h Transition Control DAC_SNG VOL DAC_SZC1 DAC_SZC0 AMUTE MUTE ADC_SP ADC_SNG VOL ADC_SZC1 ADC_SZC0 p4 6 default 0 0 0 1 0 0 0 0 07h Channel Mute Reserved Reserved AOUT6 MUTE AOUT5 MUTE AOUT4 MUTE AOUT3 MUTE AOUT2 MUTE AOUT1 MUTE p4 7 default 0 0 0 0 0 0 0 0 08h Vol. Control AOUT1 AOUT1 VOL7 AOUT1 VOL6 AOUT1 VOL5 AOUT1 VOL4 AOUT1 VOL3 AOUT1 VOL2 AOUT1 VOL1 AOUT1 VOL0 p4 7 default 0 0 0 0 0 0 0 0 09h Vol. Control AOUT2 AOUT2 VOL7 AOUT2 VOL6 AOUT2 VOL5 AOUT2 VOL4 AOUT2 VOL3 AOUT2 VOL2 AOUT2 VOL1 AOUT2 VOL0 p4 7 default 0 0 0 0 0 0 0 0 0Ah Vol. Control AOUT3 AOUT3 VOL7 AOUT3 VOL6 AOUT3 VOL5 AOUT3 VOL4 AOUT3 VOL3 AOUT3 VOL2 AOUT3 VOL1 AOUT3 VOL0 p4 7 default 0 0 0 0 0 0 0 0 0Bh Vol. Control AOUT4 AOUT4 VOL7 AOUT4 VOL6 AOUT4 VOL5 AOUT4 VOL4 AOUT4 VOL3 AOUT4 VOL2 AOUT4 VOL1 AOUT4 VOL0 p4 7 default 0 0 0 0 0 0 0 0 0Ch Vol. Control AOUT5 AOUT5 VOL7 AOUT5 VOL6 AOUT5 VOL5 AOUT5 VOL4 AOUT5 VOL3 AOUT5 VOL2 AOUT5 VOL1 AOUT5 VOL0 p4 7 default 0 0 0 0 0 0 0 0 0Dh Vol. Control AOUT6 AOUT6 VOL7 AOUT6 VOL6 AOUT6 VOL5 AOUT6 VOL4 AOUT6 VOL3 AOUT6 VOL2 AOUT6 VOL1 AOUT6 VOL0 p4 7 default 0 0 0 0 0 0 0 0 0Eh Reserved Reserved Reserved Reserved Res erved Reserved Reserved Reserved Reserved default 0 0 0 0 0 0 0 0 0Fh Reserved Reserved Reserved Reserved Res erved Reserved Reserved Reserved Reserved default 0 0 0 0 0 0 0 0 10h DAC Chan- nel Invert Reserved Reserved INV_AOUT6 INV_AOUT5 IN V_AOUT4 INV_AOUT3 INV_AOUT2 INV_AOUT1 p4 8 default 0 0 0 0 0 0 0 0

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11h Vol. Control AIN1 AIN1 VOL7 AIN1 VOL6 AIN1 VOL5 AIN1 VOL4 AIN1 VOL3 AIN1 VOL2 AIN1 VOL1 AIN1 VOL0 p4 7 default 0 0 0 0 0 0 0 0 12h Vol. Control AIN2 AIN2 VOL7 AIN2 VOL6 AIN2 VOL5 AIN2 VOL4 AIN2 VOL3 AIN2 VOL2 AIN2 VOL1 AIN2 VOL0 p4 8 default 0 0 0 0 0 0 0 0 13h Vol. Control AIN3 AIN3 VOL7 AIN3 VOL6 AIN3 VOL5 AIN3 VOL4 AIN3 VOL3 AIN3 VOL2 AIN3 VOL1 AIN3 VOL0 p4 7 default 0 0 0 0 0 0 0 0 14h Vol. Control AIN4 AIN4 VOL7 AIN4 VOL6 AIN4 VOL5 AIN4 VOL4 AIN4 VOL3 AIN4 VOL2 AIN4 VOL1 AIN4 VOL0 p4 8 default 0 0 0 0 0 0 0 0 15h Vol. Control AIN5 AIN5 VOL7 AIN5 VOL6 AIN5 VOL5 AIN5 VOL4 AIN5 VOL3 AIN5 VOL2 AIN5 VOL1 AIN5 VOL0 p4 7 default 0 0 0 0 0 0 0 0 16h Vol. Control AIN6 AIN6 VOL7 AIN6 VOL6 AIN6 VOL5 AIN6 VOL4 AIN6 VOL3 AIN6 VOL2 AIN6 VOL1 AIN6 VOL0 p4 8 default 0 0 0 0 0 0 0 0 17h ADC Chan- nel Invert Reserved Reserved INV_A6 INV_ A5 INV_A4 INV_A3 INV_A2 INV_A1 p4 8 default 0 0 0 0 0 0 0 0 18h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 0 0 0 0 0 0 0 0 19h Status Reserved Reserved Reserved Reserved CLK Error ADC3 OVFL ADC2 OVFL ADC1 OVFL p4 9 default 0 0 0 X X X X X 1Ah Status Mask Reserved Reserved Reserved Reserved CLK Error_M ADC3 OVFL_M ADC2 OVFL_M ADC1 OVFL_M p4 9 default 0 0 0 0 0 0 0 0 Addr Function 76 5 4 3 2 1 0

1. REGISTER DESCRIPTION All registers are read/write except for the I.D. and Revision Register and In terrupt Status Register which are read only. See the following bit-definition tables for bit assignment information. The default state of each bit after a power- up sequence or reset is listed in each bit description.

7.1 Memory Address Pointer (MAP)

7.1.1 Increment (INCR)

Default = 1 Function: Memory address pointer auto increment control 0 - MAP is not incremented automatically. 1 - Internal MAP is automatically incremented after each read or write.

7.1.2 Memory Address Pointer (MAP[6:0])

Default = 0000001 Function: Memory address pointer (MAP). Sets the register address that will be read or written by the control port. 7.2 Chip I.D. and Revision Regist er (Address 01h) (Read Only) 7.2.1 Chip I.D. (CHIP_ID[3:0]) Default = 0000 Function: I.D. code for the CS42436. Permanently set to 0000.

7.2.2 Chip Revision (REV_ID[3:0])

Default = 0001 Function: CS42436 revision level. Revision A is coded as 0001. 76543210 INCR MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0 76543210 Chip_ID3 Chip_ID2 Chip_ID1 Chip_I D0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0

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7.3 Power Control (Address 02h)

7.3.1 Power Down ADC Pairs (PDN_ADCX)

Default = 0 0 - Disable 1 - Enable Function: When enabled, the respective ADC channel pair (A DC1 - AIN1/AIN2; ADC2 - AIN3/AIN4; and ADC3 - AIN5/AIN6) will remain in a reset state.

7.3.2 Power Down DAC Pairs (PDN_DACX)

Default = 0 0 - Disable 1 - Enable Function: When enabled, the respective DAC channel pair (DAC1 - AOUT1/AOUT2; DAC2 - AOUT3/AOUT4; and DAC3 - AOUT5/AOUT6) will remain in a reset state. It is advised that any change of these bits be made while the DACs are muted or the power down bit (PDN) is enabled to eliminate the possibility of audible artifacts.

7.3.3 Power Down (PDN)

Default = 0 0 - Disable 1 - Enable Function: The entire device will enter a low-powe r state when this function is enab led. The contents of the control registers are retained in this mode. 76543210 PDN_ADC3 PDN_ADC2 PDN_ADC1 Reserved PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN

7.4 Functional Mode (Address 03h)

7.4.1 MCLK Frequency (MFREQ[2:0])

Sets the appropriate frequency for the supplied MC LK. For TDM operation, SCLK must equal 256Fs. MCLK can be equal to or greater than SCLK.

7.5 MISCELLANEOUS CONTROL (Address 04h)

7.5.1 Freeze Controls (FREEZE)

enable the FREEZE bit, make all register changes, then disable the FREEZE bit.

7.5.2 Auxiliary Digital Interface Format (AUX_DIF)

are detailed in Figures 17-18. Table 7. MCLK Frequency Settings

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7.6 ADC Control & DAC De-E mphasis (Address 05h)

7.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE)

Default = 0 Function: When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset value will be frozen and contin ue to be subtracted from the conversion result. See “ADC Digital Filter Characteristics” on page 16.

7.6.2 ADC3 High Pass Filter Freeze (ADC3_HPF FREEZE)

Default = 0 Function: When this bit is set, the internal high-pass filter will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter Characteris- tics” on page 16.

7.6.3 DAC De-Emphasis Control (DAC_DEM)

Default = 0 0 - No De-Emphasis 1 - De-Emphasis Enabled (Auto-Detect Fs) Function: Enables the digital filter to maintain the standard 15 μs/50μs digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasi s will not be enabled, regardless of this register setting, at any other sample rate.

7.6.4 ADC1 Single-Ended Mode (ADC1 SINGLE)

Default = 0 0 - Disabled; Differential input to ADC1 1 - Enabled; Single-Ended input to ADC1 Function: When enabled, this bit allows the user to apply a si ngle-ended input to the positive terminal of ADC1. A +6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be driv- en to the common mode of the ADC. See Figure 21 on page 50 for a graphical description. 76543210 ADC1-2_HPF FREEZE ADC3_HPF FREEZE DAC_DEM ADC1 SINGLE ADC2 SINGLE ADC3 SINGLE AIN5_MUX AIN6_MUX

7.6.5 ADC2 Single-Ended Mode (ADC2 SINGLE)

Default = 0 0 - Disabled; Differential input to ADC2 1 - Enabled; Single-Ended input to ADC2 Function: When enabled, this bit allows the user to apply a si ngle-ended input to the positive terminal of ADC2. A +6 dB digital gain is automatically applied to the serial audio data of ADC2. The negative leg must be driv- en to the common mode of the ADC. See Figure 21 on page 50 for a graphical description.

7.6.6 ADC3 Single-Ended Mode (ADC3 SINGLE)

Default = 0 0 - Disabled; Differential input to ADC 1 - Enabled; Single-Ended input to ADC Function: When disabled, this bit removes the 4:2 multiplexer from the signal path of ADC3 allowing a differential input. When enabled, this bit allows the user to choose between four single-ended inputs to ADC3, using the AIN5_MUX and AIN6_MUX bits. See Figure 11 on page 31 and Figure 21 on page 50 for graphical descriptions. 7.6.7 Analog Input Ch. 5 Multiplexer (AIN5_MUX) Default = 0 0 - Single-Ended Input AIN5A 1 - Single-Ended Input AIN5B Function: ADC3 can accept single-ended input signals when the ADC3 SINGLE bit is enabled. The AIN5_MUX bit selects between two input channels (AIN5A or AIN5B) to be sent to ADC3 in Single-Ended Mode. This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 11 on page 31 for a graphical description. 7.6.8 Analog Input Ch. 6 Multiplexer (AIN6_MUX) Default = 0 0 - Single-Ended Input AIN6A 1 - Single-Ended Input AIN6B Function: ADC3 can accept a single-ended input signal when the ADC3 SINGLE bit is enabled. The AIN6_MUX bit selects between two input channels (AIN6A or AIN6B) to be sent to ADC3 in Single-Ended Mode. This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 11 on page 31 for a graphical description.

46 DS647F1

7.7 Transition Control (Address 06h)

7.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL)

Default = 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control reg- isters when this function is disabled. When enabled, the volume on all channels is determined by the AOUT1 and AIN1 Volume Control register and the other Volume Control registers are ignored.

7.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0])

Default = 00 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected, all volume-level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or mut- ing, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will oc- cur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implement- ed by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encoun ter a zero crossing. The zero cross function is inde- pendently monitored and implemented for each channel.

7.7.3 Auto-Mute (AMUTE)

Default = 1 0 - Disabled 1 - Enabled 76 54 3 21 0 DAC_SNGVOL DAC_SZC1 DAC_SZC0 AMUTE MUTE ADC_SP ADC_SNGVOL ADC_SZC1 ADC_SZC0

Function: The Digital-to-Analog converters of the CS42436 will mute the output following the reception of 8192 con- secutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]).

7.7.4 Mute ADC Serial Port (MUTE ADC_SP)

Default = 0 0 - Disabled 1 - Enabled Function: When enabled, the ADC Serial Port will be muted.

7.8 DAC Channel Mute (Address 07h)

7.8.1 Independent Channel Mute (AOUTX_MUTE)

Default = 0 0 - Disabled 1 - Enabled Function: The respective Digital-to-Analog converter outputs of the CS42436 will mute when enabled. The quies- cent voltage on the outputs will be retained. The muting function is affected by the DAC Soft and Zero Cross bits (DAC_SZC[1:0]).

7.9 AOUTX Volume Control (Addresses 08h-0D)

7.9.1 Volume Contro l (AOUTX_VOL[7:0])

Default = 00h Function: The AOUTx Volume Control registers allow independent setting of the signal levels in 0.5 dB increments from 0 dB to -127.5 dB. Volume settings are decoded as shown in Table 8. The volume changes are im- plemented as dictated by the Soft and Zero Cross bi ts (DAC_SZC[1:0]). All volume settings less than - 127.5 dB are equivalent to enabling the AOUTx_MUTE bit for the given channel. 76543210 Reserved Reserved AOUT6_MUTE AOUT5_MUTE AOUT4_MUTE AOUT3_MUTE AOUT2_MUTE AOUT1_MUTE 76543210 AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0

48 DS647F1

7.10 DAC Channel Invert (Address 10h)

7.10.1 Invert Signal Polarity (INV_AOUTX)

When enabled, these bits will invert the signal polarity of their respective channels.

7.11 AINX Volume Control (Address 11h-16h)

7.11.1 AINX Volume C ontrol (AINX_VOL[7:0])

bits (ADC_SZC[1:0]) from +24 to -64 dB. Levels are decoded in two’s complement, as shown in Table 9. Table 8. Example AOUT Volume Settings Table 9. Example AIN Volume Settings

7.12 ADC Channel Invert (Address 17h)

7.12.1 Invert Signal Polarity (INV_AINX)

Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels.

7.13 Status (Address 19h) (Read Only)

For all bits in this register, a “1” means the associated error condition has occurred at least once since the register was last read. A”0” means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always be “0” in this register.

7.13.1 CLOCK ERROR (CLK ERROR)

Default = x Function: Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes active during the error condition. See “System Clocking” on page 33 for valid clock ratios.

7.13.2 ADC Overflow (ADCX_OVFL)

Default = x Function: Indicates that there is an over-range condition anywhere in the CS42436 ADC signal path of each of the associated ADC’s.

7.14 Status Mask (Address 1Ah)

Default = 0000 Function: The bits of this register serve as a mask for the error sources found in the register “Status (Address 19h) (Read Only)” on page 49. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect status register. The bit positions align with the corresponding bits in the Status register. 76543210 Reserved Reserved INV_AIN6 INV_AIN5 INV_AIN4 INV_AIN3 INV_AIN2 INV_AIN1 765 4 3 2 1 0 Reserved Reserved Reserved Reserved CLK Error ADC3_OVFL ADC2_OVFL ADC1_OVFL 765 4 32 1 0 Reserved Reserved Reserved Reserved CLK Error_M ADC3_OV FL_M ADC2_OVFL_M ADC1_OVFL_M

50 DS647F1

8.1 ADC Input Filter

Figure 20. Single to Differential Active Input Filter Figure 21. Single-Ended Active Input Filter

8.1.1 Passive Input Filter

fore not be realized using a passive filter. Figure 22 illustrates the unity gain, passive input filter solution. In this topology the distortion performance is affected, but the dynamic range performance is not limited.

8.1.2 Passive Input Filter w/Attenuation

2.8 Vpp, or 1 Vrms (most consumer audio line-level outputs range from 1.5 to 2 Vrms). Figure 22. Passive Input Filter

52 DS647F1

Figure 23. Passive Input Filter w/Attenuation

8.2 DAC Output Filter

alog circuitry. Shown below is the recommended active and passive output filters. Figure 24. Active Analog Output Filter Figure 25. Passive Analog Output Filter

54 DS647F1

Figure 26. SSM Stopband Rejection Figure 27. SSM Transition Band Figure 28. SSM Transition Band (Detail) Figure 29. SSM Passband Ripple Figure 30. DSM Stopband Rejection F igure 31. DSM Transition Band

Figure 32. DSM Transition Band (Detail) Figure 33. DSM Passband Ripple

56 DS647F1

Figure 34. SSM Stopband Rejection Figure 35. SSM Transition Band Figure 36. SSM Transition Band (detail) Figure 37. SSM Passband Ripple Figure 38. DSM Stopband Rejection Figure 39. DSM Transition Band

58 DS647F1

11.PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measure- ment. This measurement te chnique has been accepted by the Au dio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms su m of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including di stortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the convert- er's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error

12.REFERENCES 1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices , Version 6.0, February 1998. 2. Cirrus Logic, Techniques to Measure and Maximize the Perf ormance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 1997. of the Audio Engineering Society, November 1988. 4. Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquis t Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Au- dio Engineering Society, October 1989. 5. Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Applica- tion Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 6. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 7. Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Ha- mashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, Oc- tober 1992. 8. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com

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13.PACKAGE INFORMATION

13.1 Thermal Characteristics

DIM MIN NOM MAX MIN NOM MAX * Nominal pin pitch is 0.65 mm Controlling dimension is mm. JEDEC Designation: MS022 Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance 2 Layer Board

4 Layer Board

θJA °C/Watt °C/Watt E D1D e L B A 52L MQFP PACKAGE DRAWING

14.ORDERING INFORMATION 15.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order # CS42436 6-in, 6-out, TDM CODEC for Surround Sound Apps 52L-MQFP YES Commercial -10° to +70° C Rail CS42436-C MZ Tape & Reel CS42436-C MZR Automotive -40° to +105° C Rail CS42436-D MZ Tape & Reel CS42436-D MZR CDB42438 CS42436 Evaluation Board - - - - - CDB424 38 Revision Changes A1 Initial Release A2 Corrected I²C Address in Section 5.7.2 on page 36. PP1 Initial Preliminary Product (PP) Release subject to legal notice below. Added pin numbers to “Typical Connection Diagram (Software Mode)” on page 11 and “Typical Con- nection Diagram (Hardware Mode)” on page 12. Changed ADC Double-Speed Mode parameters. See Note 2 on page 13 and Note 18 on page 21. Added ADC3 MUX Interchannel Isolation characteristic in “Characteristics and Specifications” beginning on page 13. Changed ADC Passband Ripple maximum specifications for SSM, DSM & QSM in section “Characteristics and Specifications” beginning on page 13. Changed DAC Frequency Response specifications for SSM, DSM & QSM in “Characteristics and Specifica- tions” beginning on page 13. Removed ADC Quad-Speed Mode feature. See Note 19 on page 21. Added section “De-Emphasis Filter” on page 32. Corrected section “TDM data is received most significant bit (MSB) first, on the second rising edge of the SCLK occurring after a an FS rising edge. All data is valid on the rising edge of SCLK. The AIN1 MSB is transmitted early, but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted on the falling edge of SCLK. Each time slot is 32 bits wide, with the valid data sample left ‘justified within the time slot. Valid data lengths are 16, 18, 20, or 24.” on page 33. Changed AIN1-6 Volume Control range from (+12 dB to -115.5 dB) to (+24 dB to -64 dB) in register “AINX Volume Control (AINX_VOL[7:0])” on page 48. Removed the register “Status Control (address 18h)”. See “CLOCK ERROR (CLK ERROR)” on page 49 and “ADC Overflow (ADCX_OVFL)” on page 49 for the Active Mode setting. PP2 Corrected Figures 21-23. Added “Ordering Information” on page 61. F1 Updated temperature and voltage specifications in the “Recommended Operating Conditions” on page 13. Added test conditions to the Analog Input and Analog Output Characteristics tables.

62 DS647F1

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