CS42428_05 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
! Eight 24-bit D/A, two 24-bit A/D Converters ! 114 dB DAC / 114 dB ADC Dynamic Range ! -100 dB THD+N ! System Sampling Rates up to 192 kHz ! Integrated Low-Jitter PLL for Increased System Jitter Tolerance ! PLL Clock or System Clock Selection ! 7 Configurable General-Purpose Outputs ! ADC High-Pass Filter for DC Offset Calibration ! Expandable ADC Channels and One-Line Mode Support ! Digital Output Volume Control with Soft Ramp ! Digital +/-15 dB Input Gain Adjust for ADC ! Differential Analog Architecture ! Supports Logic Levels between 1.8 V and 5 V General Description The CS42428 codec provides two analog-to-digital and eight digital-to-analog delta-sigma converters, as well as an integrated PLL. The CS42428 integrated PLL provides a low-jitter sys- tem clock. The internal stereo ADC is capable of independent channel gain control for single-ended or differential analog inputs. All eight channels of DAC pro- vide digital volume control and differential analog outputs. The general-purpose outputs may be driven high or low, or mapped to a variety of DAC mute con- trols or ADC overflow indicators. The CS42428 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD rece ivers, digital speaker and automotive audio systems. The CS42428 is available in a 64-pin LQFP package in both Commercial (-10° to 70° C) and Automotive (-40° to 85° C) grades. The CDB42428 Customer Dem- onstration board is also available for device evaluation. Refer to “Ordering Information” on page 71. PLL Internal Voltage Reference RST GPO1 AD0/CS SCL/CCLK SDA/CDOUT AD1/CDIN VLC AOUTA1+ AOUTA1- AOUTB1+ AOUTA3+ AOUTA3- AOUTA2- AOUTB2- AOUTA2+ AOUTB2+ AOUTB1- AOUTB3+ AOUTB3- AOUTA4+ AOUTA4- AOUTB4+ AOUTB4- AINL+ AINL- AINR+ AINR- FILT+REFGND VQ ADC#1 ADC#2 Digital Filter Digital Filter Gain & Clip Gain & Clip DAC_SCLK DAC_LRCK DAC_SDIN4 DAC_SDIN3 DAC_SDIN2 DAC_SDIN1 VLS DGND VDOMCK RMCK LPFLT INT Control Port DAC#1 DAC#2 DAC#3 DAC#4 DAC#5 DAC#6 DAC#7 DAC#8 Digital Filter Volume Control GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 MUTEC Mute Analog Filter VA AGND Mult/Div GPO Level Translator DAC Serial Audio Port ADC_SDOUT ADCIN1 ADCIN2 ADC_LRCK ADC Serial Audio Port ADC_SCLK Level Translator NOVEMBER '05 DS605F1 CS42428
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI
6.14 Mixing Control Pair 1 (Channels A1 & B1)(address 18h)
Mixing Control Pair 2 (Channels A2 & B2)(address 19h) Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah)
6.20 Interrupt Mode MSB (address 22h)
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- CHARACTERISTICS A ND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode) ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) WARNING: Operation at or beyond these limit s may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. 2. The maximum over/under voltage is limited by the input current. Parameter Symbol Min Typ Max Units DC Power Supply Analog Digital Serial Port Interface Control Port Interface VA VD VLS VLC 4.75 3.13 1.8 1.8 5.0 3.3 5.0 5.0 5.25 5.25 5.25 5.25 V V V V Ambient Operating Temperature (power applied) CS42428-CQZ CS42428-DQZ T A -10 -40 +70 +85 Parameters Symbol Min Max Units DC Power Supply Analog Digital Serial Port Interface Control Port Interface VA VD VLS VLC -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 V V V V Input Current (Note 1) I in -± 1 0 m A Analog Input Voltage (Note 2) VIN AGND-0.7 VA+0.7 V Digital Input Voltage Serial Port Interface (Note 2) Control Port Interface VIND-S VIND-C -0.3 -0.3 VLS+ 0.4 VLC+ 0.4 V V Ambient Operating Temperature(power applied) CS42428-CQZ CS42428-DQZ T A TA -20 -50 +85 +95 Storage Temperature Tstg -65 +150 °C
ANALOG INPUT CHARACTERISTICS (TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Full-scale input sine wave, 997 Hz.; PDN_PLL = 1; OMCK = 12.288 MHz; Single-Speed Mode DAC_SCLK = 3.072 MHz; Double-Speed Mode DAC_SCLK = 6.144 MHz; Quad-Speed Mode DAC_SCLK = 12.288 MHz.) Notes: 3. Referred to the typical full-scale voltage. 4. Measured between AIN+ and AIN- Parameter Symbol CS42428-CQZ Min Typ Max CS42428-DQZ Min Typ Max Unit Single-Speed Mode (Fs=48 kHz) Dynamic Range A-weighted unweighted 108 105 114 111 106 103 114 111 dB dB Total Harmonic Distortion + Noise (Note 3) -1 dB -20 dB -60 dB THD+N - -100 -91 -51 -94 -100 -91 -51 -92 dB dB dB Double-Speed Mode (Fs=96 kHz) Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 108 105 114 111 108 106 103 114 111 108 dB dB dB Total Harmonic Distortion + Noise (Note 3) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N -100 -91 -51 -97 -94 -100 -91 -51 -97 -92 dB dB dB dB Quad-Speed Mode (Fs=192 kHz) Dynamic Range A-weighted unweighted 40 kHz bandwidth unweighted 108 105 114 111 108 106 103 114 111 108 dB dB dB Total Harmonic Distortion+ Noise (Note 3) -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB THD+N -100 -91 -51 -97 -94 -100 -91 -51 -97 -92 dB dB dB dB Dynamic Performance for All Modes Interchannel Isolation -1 1 0- -1 1 0-d B Interchannel Phase Deviation - 0.0001 - - 0.0001 - Degree DC Accuracy Interchannel Gain Mismatch - 0.1 - - 0.1 - dB Gain Drift - +/-100 - - +/-100 - ppm/°C Offset Error HPF_FREEZE disabled HPF_FREEZE enabled 100 100 LSB LSB Analog Input Input Impedance (Differential) (Note 4) 17 - - 17 - - k Ω Common Mode Rejection Ratio CMRR - 82 - - 82 - dB
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A/D DIGITAL FILTER CHARACTERISTICS Notes: 5. The filter frequency response scales precisely with Fs. 6. Response shown is for Fs equal to 48 kH z. Filter characteristics scale with Fs. Parameter Symbol Min Typ Max Unit Single-Speed Mode (2 to 50 kHz sample rates) Passband (-0.1 dB) (Note 5) 0 - 0.47 Fs Passband Ripple -- ±0.035 dB Stopband (Note 5) 0.58 - - Fs Stopband Attenuation -95 - - dB Total Group Delay (Fs = Output Sample Rate) tgd -1 2 / F s- s Group Delay Variation vs. Frequency ∆tgd -- 0 . 0 µs Double-Speed Mode (50 to 100 kHz sample rates) Passband (-0.1 dB) (Note 5) 0 - 0.45 Fs Passband Ripple -- ±0.035 dB Stopband (Note 5) 0.68 - - Fs Stopband Attenuation -92 - - dB Total Group Delay (Fs = Output Sample Rate) tgd -9 / F s- s Group Delay Variation vs. Frequency ∆tgd -- 0 . 0 µs Quad-Speed Mode (100 to 192 kHz sample rates) Passband (-0.1 dB) (Note 5) 0 - 0.24 Fs Passband Ripple -- ±0.035 dB Stopband (Note 5) 0.78 - - Fs Stopband Attenuation -97 - - dB Total Group Delay (Fs = Output Sample Rate) tgd -5 / F s- s Group Delay Variation vs. Frequency ∆tgd -- 0 . 0 µs High-Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB (Note 6) Hz Hz Phase Deviation @ 20 Hz (Note 6) -1 0- D e g Passband Ripple --0 d B Filter Setting Time -1 0 5/Fs - s
ANALOG OUTPUT CHARACTERISTICS (TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measurement Bandwidth 10 Hz to 20 kHz unless otherwise specified.; Full-scale output 997 Hz sine wave, Test load RL = 3 kΩ, CL = 30 pF; PDN_PLL = 1; OMCK = 12.288 MHz; Single-Speed Mode, DAC_SCLK = 3.072 MHz; Double-Speed Mode, DAC_SCLK = 6.144 MHz; Quad-Speed Mode, DAC_SCLK = 12.288 MHz.) Notes: 7. One-half LSB of triangular PDF dither is added to data. 8. Performance limited by 16-bit quantization noise. Parameter Symbol CS42428-CQZ Min Typ Max CS42428-DQZ Min Typ Max Unit Dynamic performance for all modes Dynamic Range (Note 7) 24-bit A-Weighted unweighted 16-bit A-Weighted (Note 8) unweighted 108 105 114 111 106 103 114 111 dB dB dB dB Total Harmonic Distortion + Noise 24-bit 0 dB -20 dB -60 dB 16-bit 0 dB (Note 8) -20 dB -60 dB THD+N -100 -91 -51 -94 -74 -34 -94 -100 -91 -51 -94 -74 -34 -92 dB dB dB dB dB dB Idle Channel Noise/Signal-to-Noise Ratio (A-Weighted) - 114 - - 114 - dB Interchannel Isolation (1 kHz) -9 0 -- 9 0 -d B Analog Output Characteristics for all modes Unloaded Full-Scale Differential Output Interchannel Gain Mismatch -0 . 1 - - 0 . 1 - d B Gain Drift - 300 - - 300 - ppm/°C Output Impedance ZOUT - 150 - - 150 - Ω AC-Load Resistance RL 3- - 3 - - k Ω Load Capacitance CL - - 30 - - 30 pF
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D/A DIGITAL FILTER CHARACTERISTICS Notes: 9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 39 to 62) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 10. Single- and Double-Speed Mode Measurement Bandwidth is from stopband to 3 Fs. Quad-Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs. 11. De-emphasis is available only in Single-Speed Mode. Parameter Fast Roll-Off Slow Roll-Off UnitMin Typ Max Min Typ Max Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner 0.4535 0.4998 0.4166 0.4998 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 -0.01 - +0.01 dB StopBand 0.5465 - - 0.5834 - - Fs StopBand Attenuation (Note 10) 90 - - 64 - - dB Group Delay - 12/Fs - - 6.5/Fs - s Passband Group Delay Deviation 0 - 20 kHz - - ±0.41/Fs - ±0.14/Fs s De-emphasis Error (Note 11) Fs = 32 kHz (Relative to 1 kHz) Fs = 44.1 kHz Fs = 48 kHz ±0.23 ±0.14 ±0.09 ±0.23 ±0.14 ±0.09 dB dB dB Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner 0.4166 0.4998 0.2083 0.4998 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB StopBand 0.5834 - - 0.7917 - - Fs StopBand Attenuation (Note 10) 80 - - 70 - - dB Group Delay - 4.6/Fs - - 3.9/Fs - s Passband Group Delay Deviation 0 - 20 kHz - - ±0.03/Fs - ±0.01/Fs s Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz Passband (Note 9) to -0.01 dB corner to -3 dB corner 0.1046 0.4897 0.1042 0.4813 Fs Fs Frequency Response 10 Hz to 20 kHz -0.01 - 0.01 -0.01 - 0.01 dB StopBand 0.6355 - - 0.8683 - - Fs StopBand Attenuation (Note 10) 90 - - 75 - - dB Group Delay - 4.7/Fs - - 4.2/Fs - s Passband Group Delay Deviation 0 - 20 kHz - - ±0.01/Fs - ±0.01/Fs s
- After powering-up the CS42428, RST should be held low after the power supplies and clocks are set-
- See Table 1 on page 24 for suggested OMCK frequencies
- Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
- Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 48 is set to Multiply by 2.
- 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode.
Figure 1. Serial Audio Port Master Mode Timing Figure 2. Serial Audio Port Slave Mode Timing
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- Data must be held for sufficient ti me to bridge the transition time, tfc, of SCL.
- The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
- for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode
Figure 3. Control Port Timing - I²C Format
- Data must be held for sufficient time to bridge the transition time of CCLK.
Figure 4. Control Port Timing - SPI Format
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DC ELECTRICAL CHARACTERISTICS (TA = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode) Notes: 22. Current consumption increases with increasing FS and increasing OMCK. Max values are based on highest FS and highest OMCK. Variance between speed modes is negligible. 23. I LC measured with no external loading on the SDA pin. 24. Power-Down Mode is defined as RST pin = Low with all clock and data lines held static. 25. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 5. Parameter Symbol Min Typ Max Units Power Supply Current normal operation, VA = 5 V (Note 22) VD = 5 V VD = 3.3 V Interface current, VLC=5 V (Note 23) VLS=5 V power-down state (all supplies) (Note 24) IA ID ID ILC ILS Ipd 250 250 mA mA mA µA mA µA Power Consumption (Note 22) VA=5 V, VD=VLS=VLC=3.3 V normal operation power-down (Note 24) VA=5 V, VD=VLS=VLC=5 V normal operation power-down (Note 24) 587 1.25 866 1.25 650 960 mW mW mW mW Power Supply Rejection Ratio (Note 25) (1 kHz) (60 Hz) PSRR - dB dB VQ Nominal Voltage VQ Output Impedance VQ Maximum allowable DC current 2.7 0.01 V kΩ mA FILT+ Nominal Voltage FILT+ Output Impedance FILT+ Maximum allowable DC current 5.0 0.01 V kΩ mA
DIGITAL INTERFACE CHARACTERISTICS (For CQZ, TA = +25° C; For DQZ, TA = -40 to +85° C) Notes: 26. Serial Port signals include: RMCK, OMCK , ADC_SCLK, ADC_LRCK, DAC_SCLK, DAC_LRCK, ADC _SD OUT, DAC _SD IN1-4, ADCI N1/ 2 Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, INT, RST 27. When operating RMCK above 24.576 MHz, limit the loading on the signal to 1 CMOS load. Parameters (Note 26) Symbol Min Typ Max Units High-Level Input Voltage Serial Port Control Port VIH 0.7xVLS 0.7xVLC V V Low-Level Input Voltage Serial Port Control Port VIL 0.2xVLS 0.2xVLC V V High-Level Output Voltage at Io=2 mA (Note 27)Serial Port Control Port MUTEC, GPOx VOH VLS-1.0 VLC-1.0 VA-1.0 V V V Low-Level Output Voltage at I o=2 mA (Note 27) Serial Port, Control Port, MUTEC, GPOx VOL -- 0 . 4 V Input Leakage Current Iin -- ± 1 0 µA Input Capacitance -8- p F MUTEC Drive Current -3- m A
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- PIN DESCRIPTIONS Pin Name # Pin Description DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data. DAC_SCLK 2 DAC Serial Clock (Input/Output) - Serial clock for the DAC serial audio interface. DAC_LRCK 3 DAC Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the DAC serial audio data line. VD 4 51 Digital Power (Input) - Positive power supply for the digital section. DGND 5 52 Digital Ground (Input) - Ground reference. Should be connected to digital ground. VLC 6 Control Port Power (Input) - Determines the required signal level for the control port. SCL/CCLK 7 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up resistor to the logic interface voltage in I²C mode as shown in the Typical Connection Diagram. SDA/CDOUT 8 Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an external pull-up resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDOUT is the output data line for the control port interface in SPI mode. AD1/CDIN 9 Address Bit 1 (I²C)/Serial Control Data (SPI) (Input) - AD1 is a chip address pin in I²C mode; CDIN is the input data line for the control port interface in SPI mode. AD0/CS 10 Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS is the chip select signal in SPI mode. INT 11 Interrupt (Output) - The CS42428 will generate an interrupt condition as per the Interrupt Mask register. See “Interrupts” on page 37 for more details. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DAC_SDIN1 ADC_SCLK ADC_LRCK VD DGND VLC SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS INT RST AINR- AINR+ AINL+ AINL- VQ FILT+ REFGND AOUTB4- AOUTB4+ AOUTA4+ AOUTA4- VA AGND AOUTB3- AOUTB3+ AOUTA3+ AOUTA3- AOUTB2- AOUTB2+ AOUTA2+ AOUTA2- AOUTB1- AOUTB1+ AOUTA1+ AOUTA1- MUTEC AGND VA GPO7 GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 LPFLT NC NC VD DGND VLS NC RMCK ADC_SDOUT ADCIN2 ADCIN1 OMCK DAC_LRCK DAC_SCLK DAC_SDIN4 DAC_SDIN3 DAC_SDIN2 CS42428
RST 12 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. AINR- AINR+ Differential Right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators via the AINR+/- pins. AINL+ AINL- Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators via the AINL+/- pins. VQ 17 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. REFGND 19 Reference Ground (Input) - Ground reference for the internal sampling circuits. AOUTA1 +,- AOUTB1 +,- AOUTA2 +,- AOUTB2 +,- AOUTA3 +,- AOUTB3 +,- AOUTA4 +,- AOUTB4 +,- 36,37 35,34 32,33 31,30 28,29 27,26 22,23 21,20 Differential Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. VA 24 41 Analog Power (Input) - Positive power supply for the analog section. AGND 25 40 Analog Ground (Input) - Ground reference. Should be connected to analog ground. MUTEC 38 Mute Control (Output) - The Mute Control pin outputs high impedance following an initial power-on con- dition or whenever the PDN bit is set to a ‘1’, forcing the codec into power-down mode. The signal will remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. The use of external mute circuits are not manda- tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops. LPFLT 39 PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. GPO7 GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 General Purpose Output (Output) - These pins can be configured as general purpose output pins, an ADC overflow interrupt or Mute Control outputs according to the General Purpose Pin Control registers. VLS 53 Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces. RMCK 55 Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference (OMCK, pin 59) or the PLL which is locked to the incoming ADC_LRCK. ADC_SDOUT 56 ADC Serial Data Output (Output) - Output for two’s complement serial audio PCM data from the output of the internal and external ADCs. ADCIN1 ADCIN2 External ADC Serial Input (Input) - The CS42428 provides for up to two external stereo analog to digital converter inputs to provide a maximum of six channels on one serial data output line when the CS42428 is placed in One-Line Mode. OMCK 59 External Reference Clock (Input) - External clock reference that must be within the ranges specified in the register “OMCK Frequency (OMCK Freqx)” on page 48. ADC_LRCK 60 ADC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the ADC serial audio data line. ADC_SCLK 61 ADC Serial Clock (Input/Output) - Serial clock for the ADC serial audio interface.
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- TYPICAL CONNECTION DIAGRAMS
7 SCL/CCLK
55 RMCK
58 ADCIN1
57 ADCIN2
56 ADC_SDOUT
- See the ADC Input Filter section in the Appendix.
- See the DAC Output Filter section in the Appendix.
- See the PLL Filter section in the Appendix.
Figure 5. Typical Connection Diagram
27 MHz
- See the ADC Input Filter section in the Appendix.
- See the DAC Output Filter section in the Appendix.
- See the PLL Filter section in the Appendix.
Figure 6. Typical Connection Diagram using the PLL
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4.1 Overview
one data line. All functions are configured through a serial control port operable in SPI mode or in I²C mode. 5 and 6 show the recommended connections for the CS42428. Mode (QSM) supports input sample rates up to 192 kHz and uses an oversampling ratio of 32x. clock or an externally supplied clock attached to the OMCK pin can be used as the System Clock.
4.2 Analog Inputs
4.2.1 Line-Level Inputs
Figure 7. Full-Scale Analog Input
4.2.2 High-Pass Filter and DC Offset Calibration
- Running the CS42428 with the high-pass filter enabl ed until the filter settles. See the Digital Filter
Characteristics for filter settling time.
- Disabling the high-pass filter and freezing the stored DC offset.
4.3 Analog Outputs
4.3.1 Line-Level Outputs and Filtering
amplifiers are biased to a quiescent DC level of approximately VQ. pacitors. Figure 8 shows the full-scale analog output levels.
4.3.2 Interpolation Filter
on page 46 selects which filter is used. Filter response plots can be found in Figures 39 to 62. Figure 8. Full-Scale Output
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4.3.3 Digital Volume and Mute Control
Transition Control (address 0Dh)” on page 51. in the Pin Descriptions section for more information. Each of the GPO1-GPO7 can be programmed to provid e a hardware MUTE signal to individual circuits. bits in the register “General-Purpose Pin Control (addresses 29h to 2Fh)” on page 58.
4.3.4 ATAPI Specification
Figure 9. ATAPI Block Diagram (x = channel pair 1, 2, 3, 4)
4.4 Clock Generation
lock to the other source input.
4.4.1 PLL and Jitter Attenuation
components, optimal layout guidelines, and jitter-attenuation characteristics.
49.152 MHz
Figure 10. Clock Generation
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4.4.2 OMCK Syst em Clock Mode
that the FRC_PLL_LK bit is set to ‘0’ (See “Force PLL Lock (FRC_PLL_LK)” on page 49).
4.4.3 Master Mode
Register (See “Clock Control (address 06h)” on page 48).
4.4.4 Slave Mode
put frequencies are shown in Table 2. lected and desired speed mode. Table 1. Common OMCK Clock Frequencies
In Slave Mode, One-Line Mode #1 is supported; One-Line Mode #2 is not. in Table 1. Refer to Table 3 for required clock ratios.
4.5 Digital Interfaces
4.5.1 Serial Audio Interface Signals
found in register “Functional Mode (address 03h)” on page 43. made using bits DAC_SP M/S and ADC_SP M/S in register “Misc Control (address 05h)” on page 46. the sample rate, Fs, of the ADC_SP and the DAC_SP to be different, but must be multiples of each other. in two's complement binary form with the MSB first in all formats. ADC data are output on ADC_SDOUT. Table 4 on page 26 outlines the serial port channel allocations. Table 3. Slave Mode Clock Ratios
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Table 4. Serial Audio Port Channel Allocations
4.5.2 Serial Audio Interface Formats
Figure 11. Right-Justified Serial Audio Formats
64 Fs 48, 64, 128 Fs Single-Speed Mode
64 Fs 64 Fs Double-Speed Mode
64 Fs 64 Fs Quad-Speed Mode
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Figure 12. I²S Serial Audio Formats Figure 13. Left-Justified Serial Audio Formats
64 Fs 32, 48, 64, 128 Fs Single-Speed Mode
64 Fs 32, 64 Fs Double-Speed Mode
64 Fs 32, 64 Fs Quad-Speed Mode
Figure 14. One Line Mode #1 Serial Audio Format
128 Fs 128Fs double-speed mode
Figure 15. One Line Mode #2 Serial Audio Format
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4.5.3 ADCIN1/ADCIN2 Se rial Data Format
and wired to GND via a pull-down resistor. are wired to use the ADC_SP clocks, set this bit to ‘0’. Figure 16. ADCIN1/ADCIN2 Serial Audio Format
4.5.4 One-Line Mode (OLM) Configurations
4.5.4.1 OLM Config #1
One-Line Mode Configuration #1 can support up to 8 channels of DAC data, and 6 channels of ADC data. all channels for both the DAC and ADC. Set ADC_CLK_SEL = 0 Configure ADC_SDOUT to be clocked from the DAC_SP clocks. Set DAC_SP M/S = 1 Configure DAC Serial Port to Master Mode. Set ADC_SP M/S = 1 Configure ADC Serial Port to Master Mode. Set EXT ADC SCLK = 0 Identify external ADC clock source as SAI Serial Port. Figure 17. OLM Configuration #1
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4.5.4.2 OLM Config #2
DAC Serial Port sample frequency. Set ADC_CLK_SEL = 1 Configure ADC_SDOUT to be clocked from the ADC_SP clocks. Set DAC_SP M/S = 1 Set DAC Serial Port to Master Mode. Set ADC_SP M/S = 1 Set ADC Serial Port to Master Mode. Set EXT ADC SCLK = 1 Identify external ADC clock source as DAC Serial Port. Figure 18. OLM Configuration #2
4.5.4.3 OLM Config #3
rate of the ADC serial port. Set ADC_CLK_SEL = 1 Configure ADC_SDOUT to be clocked from the ADC_SP clocks. Set DAC_SP M/S = 1 Set DAC Serial Port to Master Mode. Set ADC_SP M/S = 0 or 1 Set ADC Serial Port to Master Mode or Slave Mode. Set EXT ADC SCLK = 0 Identify external ADC clock source as ADC Serial Port. Figure 19. OLM Configuration #3
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4.5.4.4 OLM Config #4
Set DAC_SP M/S = 0 or 1 Set DAC Serial Port to Master Mode or Slave Mode. Set ADC_SP M/S = 0 or 1 Set ADC Serial Port to Master Mode or Slave Mode. Set EXT ADC SCLK = 0 External ADCs are not used. Leave bit in default state. Figure 20. OLM Configuration #4
4.6 Control Port Description and Timing
should remain static if no operation is required. selecting the desired AD0 bit address state.
4.6.1 SPI Mode
state. It may be externally pulled high or low with a 47 kΩ resistor, if desired. after each byte is read or written, allowing block reads or writes of successive registers. as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. Figure 21. Control Port Timing in SPI Mode
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4.6.2 I²C Mode
In I²C mode, SDA is a bidirectional da ta line. Data is clocke d into and out of the pa rt by the clock, SCL. CS42428 from the microcontroller after each transmitted byte. dition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send 10011xx0 (chip address & write operation). Send MAP byte, auto increment off. Send stop condition, aborting write. Figure 22. Control Port Timing, I²C Write Figure 23. Control Port Timing, I²C Read
Send start condition. Send 10011xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
4.7 Interrupts
The CS42428 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin on the host microcontroller. The INT pin may be set to be active low, active high or active low with no active pull-up transistor. This last mode is used for active low, wired-OR hook-ups, with multiple periph- erals connected to the microcontroller interrupt input pin. Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see “Interrupt Status (address 20h) (Read Only)” on page 56). Each source may be masked off through mask register bits. In addition, each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option of level-sensitive or edge-sensitive modes within the microcontroller, many different configurations are pos- sible, depending on the needs of the equipment designer.
4.8 Reset and Power-Up
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be activated if the analog or digital supplies drop below the recommended operating condition to prevent power-glitch-related issues. When RST is low, the CS42428 enters a low-power mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RST is high, the control port becomes opera- tional, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control Register will then cause the part to leave the low-power state and begin operation. If the in- ternal PLL is selected as the clock source, the serial audio outputs will be enabled after the PLL has settled (see “Power Control (address 02h)” on page 43 for more details). The delta-sigma modulators settle in a matter of micros econds after the analog se ction is powered, either through the application of power or by setting the RST pin high. However, the voltage reference will take much longer to reach a final value due to the presen ce of external capacitance on the FILT+ pin. A time delay of approximately 80 ms is required after applying power to the device or after exiting a reset state. During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.
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4.9 Power Supply, Gr ounding, and PCB Layout
As with any high-resolution converter, the CS42428 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. Figure 5 and 6 show the recommended power arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD. For applications where the output of the PLL is requir ed to be low jitter, use a separate, low-noise analog +5 V supply for VA, decoupled to AGND. In addition, a separate region of analog ground plane around the FILT+, VQ, LPFLT, REFGND, AGND, and VA pins is recommended. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42428 as pos- sible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42428 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and REFGND. The CDB42428 evaluation board demonstrates the optimum lay- out and power supply arrangements.
- REGISTER QU ICK REFERENCE Addr Function 7 6 5 4 3 2 1 0 01h ID Chip_ID3 Chip_ID2 Chip_ID1 Chip_I D0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0 page 42 default 11 1 1 X X XX 02h Power Con- trol Reserved PDN_PLL PDN_ADC PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN page 43 default 0 0 00000 1 03h Functional Mode DAC_FM1 DAC_FM0 ADC_FM1 ADC_FM0 Reserved ADC_CLK SEL DAC_DEM Reserved page 43 default 0 0 00000 0 04h Interface Formats DIF1 DIF0 ADC_OL1 ADC_OL0 DAC_OL1 DAC_OL0 Reserved CODEC_RJ16 page 45 default 0 1 00000 0 05h Misc Control Ext ADC SCLK HiZ_RMCK Reserved FREEZE FILTSEL HPF_ FREEZE DAC_SP M/S ADC_SP M/S page 46 default 0 0 00000 0 06h Clock Con- trol RMCK_DIV1 RMCK_DIV0 OMCK Freq1 OMCK Freq0 PLL_LRCK SW_CTRL1 SW_CTRL0 FRC_PLL_LK page 48 default 0 0 00000 0 07h OMCK/PLL_ CLK Ratio RATIO7 RATIO6 RATIO5 RATIO4 RATIO3 RATIO2 RATIO1 RATIO0 page 49 default XX X X X X XX 08h Clock Status Reserved Reserved Reserved Reserved Active_CLK PLL_CLK2 PLL_CLK1 PLL_CLK0 page 50 default XX X X X X XX 09h- 0Ch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default X X X X X X X X 0Dh Volume Control Reserved SNGVOL SZC1 SZC0 AMUTE Reserved RAMP_UP RAMP_DN page 51 default 0 0 00100 0 0Eh Channel Mute B4_MUTE A4_MUTE B3_MUTE A3_MUTE B2_MUTE A2_MUTE B1_MUTE A1_MUTE page 52 default 0 0 00000 0 0Fh Vol. Control A1_VOL7 A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0 page 53 default 0 0 00000 0 10h Vol. Control B1_VOL7 B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0 page 53 default 0 0 00000 0 11h Vol. Control A2_VOL7 A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0 page 53 default 0 0 00000 0 12h Vol. Control B2_VOL7 B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0 page 53 default 0 0 00000 0
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13h Vol. Control A3_VOL7 A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0 page 53 default 0 0 00000 0 14h Vol. Control B3_VOL7 B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0 page 53 default 0 0 00000 0 15h Vol. Control A4_VOL7 A4_VOL6 A4_VOL5 A4_VOL4 A4_VOL3 A4_VOL2 A4_VOL1 A4_VOL0 page 53 default 0 0 00000 0 16h Vol. Control B4_VOL7 B4_VOL6 B4_VOL5 B4_VOL4 B4_VOL3 B4_VOL2 B4_VOL1 B4_VOL0 page 53 default 0 0 00000 0 17h Channel Invert INV_B4 INV_A4 INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1 page 53 default 0 0 00000 0 18h Mixing Ctrl Pair 1 P1_A=B Reserved Reserved P1_ATAPI4 P1_ATAPI3 P1_ATAPI2 P1_ATAPI1 P1_ATAPI0 page 53 default 0 0 00100 1 19h Mixing Ctrl Pair 2 P2_A=B Reserved Reserved P2_ATAPI4 P2_ATAPI3 P2_ATAPI2 P2_ATAPI1 P2_ATAPI0 page 53 default 0 0 00100 1 1Ah Mixing Ctrl Pair 3 P3_A=B Reserved Reserved P3_ATAPI4 P3_ATAPI3 P3_ATAPI2 P3_ATAPI1 P3_ATAPI0 page 53 default 0 0 00100 1 1Bh Mixing Ctrl Pair 4 P4_A=B Reserved Reserved P4_ATAPI4 P4_ATAPI3 P4_ATAPI2 P4_ATAPI1 P4_ATAPI0 page 53 default 0 0 00100 1 1Ch ADC Left Ch. Gain Reserved Reserved LGAIN5 LGAIN4 LGAIN3 LGAIN2 LGAIN1 LGAIN0 page 55 default 0 0 00000 0 1Dh ADC Right Ch. Gain Reserved Reserved RGAIN5 RGAIN4 RGAIN3 RGAIN2 RGAIN1 RGAIN0 page 55 default 0 0 00000 0 1Eh Interrupt Control SP_SYNC Reserved DE-EMPH1 DE-EMPH0 INT1 INT0 Reserved Reserved page 55 default 0 0 00000 0 1Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 0 0 00000 0 20h Interrupt Status UNLOCK Reserved Reserved Reserved Reserved Reserved OverFlow Reserved page 56 default XX X X X X XX 21h Interrupt Mask UNLOCKM Reserved Reserved Reserved Reserved Reserved OverFlowM Reserved page 57 default 0 0 00000 0 22h Interrupt Mode MSB UNLOCK1 Reserved Reserved Reserved Reserved Reserved OF1 Reserved page 57 default 0 0 00000 0 Addr Function 7 6 5 4 3 2 1 0
UNLOCK0 Reserved Reserved Reserved Reserved Reserved OF0 Reserved page 57 default 0 0 00000 0 24h- 27h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 0 0 00000 0 28h MUTEC Reserved Reserved MCPolarity M_AOUTA1 M_AOUTB1 M_AOUTA2 M_AOUTB2 M_AOUTA3 M_AOUTB3 M_AOUTA4 M_AOUTB4 page 57 default 0 0 01111 1 29h GPO7 Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 58 default 0 0 00000 0 2Ah GPO6 Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 58 default 0 0 00000 0 2Bh GPO5 Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 58 default 0 0 00000 0 2Ch GPO4 Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 58 default 0 0 00000 0 2Dh GPO3 Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 58 default 0 0 00000 0 2Eh GPO2 Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 58 default 0 0 00000 0 2Fh GPO1 Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 58 default 0 0 00000 0 Addr Function 7 6 5 4 3 2 1 0
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- REGISTER DESCRIPTION All registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, Clock Status and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment informa- tion. The default state of each bit after a power-up sequence or reset is listed in each bit description.
6.1 Memory Address Pointer (MAP)
6.1.1 INCREMENT (INCR)
Default = 1 Function: Memory Address Pointer auto increment control 0 - MAP is not incremented automatically. 1 - Internal MAP is automatically incremented after each read or write.
6.1.2 MEMORY ADDRESS POINTER (MAPX)
Default = 0000001 Function: Memory Address Pointer (MAP). Sets the register address that will be read or written by the control port. 6.2 Chip I.D. and Revision Register (address 01h) (Read Only) 6.2.1 CHIP I.D. (CHIP_IDX) Default = 1111 Function: I.D. code for the CS42428. Permanently set to 1111.
6.2.2 CHIP REVISION (REV_IDX)
Default = xxxx Function: CS42428 revision level. Revision C1 is coded as 0101 Revision C is coded as 0011. 76543210 INCR MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0 76543210 Chip_ID3 Chip_ID2 Chip_ID1 CHIP_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0
6.3 Power Control (address 02h)
6.3.1 POWER DOWN PLL (PDN_PLL)
Default = 0 Function: When enabled, the PLL is held in a reset state. It is advised that any change of this bit be made while the DACs are muted or the power-down bit (PDN) is enabled to eliminate the possibility of audible artifacts.
6.3.2 POWER DOWN ADC (PDN_ADC)
Default = 0 Function: When enabled the stereo analog to digital converter will remain in a reset state. It is advised that any change of this bit be made while the DACs are muted or the power-down bit (PDN) is enabled to elim- inate the possibility of audible artifacts.
6.3.3 POWER DOWN DAC PAIRS (PDN_DACX)
Default = 0 Function: When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.
6.3.4 POWER DOWN (PDN)
Default = 1 Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation can occur.
6.4 Functional Mode (address 03h)
6.4.1 DAC FUNCTIONAL MODE (DAC_FMX)
Default = 00 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 192 kHz sample rates) 11 - Reserved Function: Selects the required range of sample rates for all converters clocked from the DAC serial port (DAC_SP). Bits must be set to the corresponding sample rate range when the DAC_SP is in Master or Slave Mode. 76543210 Reserved PDN_PLL PDN_ADC PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN 76543210 DAC_FM1 DAC_FM0 ADC_FM1 ADC_FM0 Rese rved ADC_SP SEL DAC_DEM Reserved
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6.4.2 ADC FUNCTIONAL MODE (ADC_FMX)
to the corresponding sample rate range when the ADC_SP is in Master or Slave Mode.
6.4.3 ADC CLOCK SOURCE SELECT (ADC_CLK SEL)
0 - ADC_SDOUT clocked from the DAC_SP. 1 - ADC_SDOUT clocked from the ADC_SP. Selects the desired clocks for the ADC serial output.
6.4.4 DAC DE-EMPHASIS CONTROL (DAC_DEM)
Interrupt Control (address 1Eh) register to set the appropriate sample rate.
0 X XX No De-Emphasis
Table 5. DAC De-Emphasis
6.5 Interface Formats (address 04h)
6.5.1 DIGITAL INTERFACE FORMAT (DIFX)
the Digital Interface Format and the options are detailed in Figures 11-13.
6.5.2 ADC ONE_LINE MODE (ADC_OLX)
6.5.3 DAC ONE_LINE MODE (DAC_OLX)
00 Left-Justified, up to 24-bit data 0 13
01 I²S, up to 24-bit data 1 12
10 Right-Justified, 16-bit or 24-bit data 2 11
11 Reserved --
Table 6. Digital Interface Formats
00 DIF: take the DIF setting from reg04h[7:6] --
01 One-Line #1 3 14
10 One-Line #2 4 15
Table 7. ADC One-Line Mode Table 8. DAC One-Line Mode
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6.5.4 CODEC RIGHT-JUSTIFIED BITS (CODEC_RJ16)
Default = 0 Function: This bit determines how many bits to use during Right-Justified Mode for the DAC and ADC. By de- fault, the DAC and ADC will be in RJ24 bits, but can be set to RJ16 bits. 0 - 24 bit mode. 1 - 16 bit mode.
6.6 Misc Control (address 05h)
6.6.1 EXTERNAL ADC SCLK SELECT (EXT ADC SCLK)
Default = 0 Function: This bit identifies the SCLK source for the external ADCs attached to the ADCIN1/2 ports when using One-Line Mode of operation. 0 - ADC_SCLK is used as external ADC SCLK. 1 - DAC_SCLK is used as external ADC SCLK.
6.6.2 RMCK HIGH IMPEDANCE (HIZ_RMCK)
Default = 0 Function: This bit is used to create a high-impedance output on RMCK when the clock signal is not required.
6.6.3 FREEZE CONTROLS (FREEZE)
Default = 0 Function: This function will freeze the previous output of, and allow modifications to be made to, the Volume Control (address 0Fh-16h), Channel Invert (address 17h), and Mixing Control Pair (address 18h-1Bh) registers without the changes taking effect until the FREEZE is disabled. To make multiple changes in these control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. 76543210 Ext ADC SCLK HiZ_RMCK Reserved F REEZE FILT_SEL HPF_FREEZE DAC_SP M/S ADC_SP M/S
6.6.4 INTERPOLATION FI LTER SELECT (FILT_SEL)
Default = 0 Function: This feature allows the user to select whether the DAC interpolation filter has a fast- or slow roll-off. For filter characteristics, please See “D/A Digital Filter Characteristics” on page 10. 0 - Fast roll-off. 1 - Slow roll-off.
6.6.5 HIGH-PASS FILTER FREEZE (HPF_FREEZE)
Default = 0 Function: When this bit is set, the internal high-pass filter for the selected channel will be disabled. The current DC offset value will be frozen and continue to be subtracted from the conversion result. See “A/D Dig- ital Filter Characteristics” on page 8.
6.6.6 DAC SERIAL PORT MAST ER/SLAVE SELECT (DAC_SP M/S)
Default = 0 Function: In Master Mode, DAC_SCLK and DAC_LRCK are outputs. Internal dividers will divide the master clock to generate the serial clock and left/right clock. In Slave Mode, DAC_SCLK and DAC_LRCK become inputs. If the DAC_SP is in Slave Mode, DAC_LRCK must be present for proper device operation.
6.6.7 ADC SERIAL PORT MAST ER/SLAVE SELECT (ADC_SP M/S)
Default = 0 Function: In Master Mode, ADC_SCLK and ADC_LRCK are outputs. Internal dividers will divide the master clock to generate the serial clock and left/right clock. In Slave Mode, ADC_SCLK and ADC_LRCK become inputs. If the ADC_SP is in Slave Mode, ADC_LRCK must be present for proper device operation. To use the PLL to lock to ADC_LRCK, the ADC_SP must be in Slave Mode. When using the PLL to lock to LRCK, if ADC_SDOUT is configured to be clocked by the ADC_SP, both ADC_SCLK and ADC_LRCK must be present. If ADC_SDOUT is configured to be clocked by the DAC_SP, only the ADC_LRCK signal must be applied.
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6.7 Clock Control (address 06h)
6.7.1 RMCK DIVIDE (RMCK_DIVX)
Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor.
6.7.2 OMCK FREQUENCY (OMCK FREQX)
Sets the appropriate frequency for the supplied OMCK.
6.7.3 PLL LOCK TO LRCK (PLL_LRCK)
(ADC_LRCK) while the ADC_SP is in Slave Mode.
00 Divide by 1
01 Divide by 2
10 Divide by 4
11 Multiply by 2
Table 9. RMCK Divider Settings
11 R e s e r v e d
Table 10. OMCK Frequency Settings
6.7.4 MASTER CLOCK SOURCE SELECT (SW_CTRLX)
unlocked, RMCK will equal OMCK, but all internal and serial port timings are not valid. unlocked when the FRC_PLL_LK bit is set to ‘1’b, RMCK will not equal OMCK.
6.7.5 FORCE PLL LOCK (FRC_PLL_LK)
properly apply de-emphasis filtering.
6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only)
6.8.1 OMCK/PLL_CLK RATIO (RATIOX)
example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h. 0 0 X Manual setting, MCLK sourced from PLL. 0 1 X Manual setting, MCLK sourced from OMCK. Auto switch, MCLK sourced from PLL. Auto switch, MCLK sourced from OMCK. Table 11. Master Clock Source Select
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6.9 Clock Status (address 08h) (Read Only)
6.9.1 SYSTEM CLOCK SELECTION (ACTIVE_CLK)
This bit identifies the source of the internal system clock (MCLK).
6.9.2 PLL CLOCK FREQUENCY (PLL_CLKX)
termine the absolute frequency of the PLL clock. Note: These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b. Table 12. PLL Clock Frequency Detection
6.10 Volume Transition Control (address 0Dh)
6.10.1 SINGLE VOLUME CONTROL (SNGVOL)
Default = 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the A1 Channel Volume Control register and the other Volume Control registers are ignored.
6.10.2 SOFT RAMP AND ZERO CROSS CONTROL (SZCX)
Default = 00 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected, all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level-change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon- itored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. 76543210 Reserved SNGVOL SZC1 SZC0 AMUTE MUTE ADC_SP RAMP_UP RAMP_DN
52 DS605F1
6.10.3 AUTO-MUTE (AMUTE)
Default = 1 0 - Disabled 1 - Enabled Function: The digital-to-analog converters of the CS42428 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained, and the MUTEC pin will go active during the mute period. The muting function is af- fected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]).
6.10.4 SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP)
Default = 0 0 - Disabled 1 - Enabled Function: An un-mute will be performed after executing a filter mode change, after a MCLK/LRCK ratio change or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is affect- ed, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]). When disabled, an immediate un-mute is performed in these instances. Note: For best results, it is recommended that this bit be used in conjunction with the RMP_DN bit.
6.10.5 SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN)
Default = 0 0 - Disabled 1 - Enabled Function: A mute will be performed prior to executing a filter mode or de-emphasis mode change. When this feature is enabled, this mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]). When disabled, an immediate mute is performed prior to executing a filter mode or de-emphasis mode change. Note: For best results, it is recommended that this bit be used in conjunction with the RMP_UP bit.
6.11 Channel Mute (address 0Eh)
6.11.1 INDEPENDENT CHAN NEL MUTE (XX_MUTE)
Default = 0 0 - Disabled 1 - Enabled Function: The digital-to-analog converter outputs of the CS42428 will mute when enabled. The quiescent volt- age on the outputs will be retained. The muting function is affected, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]). 76543210 B4_MUTE A4_MUTE B3_MUTE A3_MUTE B2_MUTE A2_MUTE B1_MUTE A1_MUTE
6.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h)
6.12.1 VOLUME CONTROL (XX_VOL)
-127 dB are equivalent to enabling the MUTE bit for the given channel.
6.13 Channel Invert (address 17h)
6.13.1 INVERT SIGNAL POLARITY (INV_XX)
When enabled, these bits will invert the signal polarity of their respective channels.
6.14.1 CHANNEL A VOLUME = CHANNEL B VOLUME (PX_A=B)
Control registers are ignored when this function is enabled. Table 13. Example Digital Volume Settings
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6.14.2 ATAPI CHANNEL-MIXING AND MUTING (PX_ATAPIX)
ATAPI functions are applied per A-B pair. Refer to Table 14 and Figure 9 for additional information.
00000 M U T E M U T E
00001 M U T E b R
00010 M U T E b L
00011 M U T E b [ ( L + R ) / 2 ]
10000 M U T E M U T E
10001 M U T E b R
10010 M U T E b L
10011 M U T E [ ( a L + b R ) / 2 ]
Table 14. ATAPI Decode
6.15 ADC Left Channel Gain (address 1Ch)
6.15.1 ADC LEFT CHANNEL GAIN (LGAINX)
6.16 ADC Right Channel Gain (address 1Dh)
6.16.1 ADC RIGHT CHANNEL GAIN (RGAINX)
6.17 Interrupt Control (address 1Eh)
6.17.1 SERIAL PORT SYNC HRONIZATION (SP_SYNC)
Table 15. Example ADC Input Gain Settings
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6.17.2 DE-EMPHASIS SELECT BITS (DE-EMPHX)
Default = 00 00 - Reserved 01 - De-Emphasis for 32 kHz sample rate. 10 - De-Emphasis for 44.1 kHz sample rate. 11 - De-Emphasis for 48 kHz sample rate. Function: Used to specify which de-emphasis filter to apply when the “Force PLL Lock (FRC_PLL_LK)” on page 49 is enabled.
6.17.3 INTERRUPT PIN CONTROL (INTX)
Default = 00 00 - Active high; high output indicates interrupt condition has occurred 01 - Active low; low output indicates an interrupt condition has occurred 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. 11 - Reserved Function: Determines how the interrupt pin (INT) will indicate an interrupt condition.
6.18 Interrupt Status (address 20h) (Read Only)
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the reg- ister was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always be “0” in this register.
6.18.1 PLL UNLOCK (UNLOCK)
Default = 0 Function: PLL unlock status bit. This bit will go high if the PLL becomes unlocked.
6.18.2 ADC OVERFLOW (OVERFLOW)
Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS42428 ADC signal path. 76543210 UNLOCK Reserved Reserved Reserved Reserved Reserved OverFlow Reserved
6.19 Interrupt Mask (address 21h)
Default = 00000000 Function: The bits of this register serve as a mask for the interrupt sources found in the register “Interrupt Status (address 20h) (Read Only)” on page 56. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Interrupt Status register. Interrupt Mode LSB (address 23h) Default = 00000000 Function: The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends on the INT(1:0) bits located in the register “Interrupt Control (address 1Eh)” on page 55. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved
6.21 Mutec Pin Control (address 28h)
6.21.1 MUTEC POLARITY SELECT (MCPOLARITY)
Default = 0 0 - Active low 1 - Active high Function: Determines the polarity of the MUTEC pin. 76543210 UNLOCKM Reserved Reserved Reserved Reserved Reserved OverFlowM Reserved 76543210 UNLOCK1 Reserved Reserved Reserved Reserved Reserved OF1 Reserved UNLOCK0 Reserved Reserved Reserved Reserved Reserved OF0 Reserved 76543210 Reserved Reserved MCPolarity M_AOUTA1 M_AOUTB1 M_AOUTA2 M_AOUTB2 M_AOUTA3 M_AOUTB3 M_AOUTA4 M_AOUTB4
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6.21.2 CHANNEL MUTES SELECT (M_AOUTXX)
Default = 11111 0 - Channel mute is not mapped to the MUTEC pin 1 - Channel mute is mapped to the MUTEC pin Function: Determines which channel mutes will be mapped to the MUTEC pin. If no channel mute bits are mapped, then the MUTEC pin is driven to the “active” state as defined by the POLARITY bit. These Channel Mute Select bits are “ANDed” together in order for the MUTEC pin to go active. This means that if multiple Channel Mutes are selected to be mapped to the MUTEC pin, all corresponding chan- nels must be muted before the MUTEC will go active.
6.22 General-Purpose Pin Control (addresses 29h to 2Fh)
6.22.1 MODE CONTROL (MODEX)
Default = 00 00 - Reserved 01 - Mute Mode 10 - GPO/Overflow Mode 11 - GPO, Drive High Mode Function: Mute Mode - The pin is configured as a dedicated mute pin. The muting function is controlled by the Function bits. GPO, Drive Low / ADC Overflow Mode - The pin is configured as a general-purpose output driven low or as a dedicated ADC overflow pin indicating an over-range condition anywhere in the ADC signal path for either the left or right channel. The Functionx bits determine the operation of the pin. When configured as a GPO with the output driven low, the driver is a CMOS driver. When configured to iden- tify an ADC Overflow condition, the driver is an open drain driver requiring a pull-up resistor. GPO, Drive High Mode - The pin is configured as a general purpose output driven high.
6.22.2 POLARITY SELECT (POLARITY)
Default = 0 Function: Mute Mode - If the pin is configured as a dedicated mute output pin, the polarity bit determines the polarity of the mapped pin according to the following 0 - Active low 1 - Active high GPO, Drive Low / ADC Overflow Mode - If the pin is configured as a GPO, Drive Low / ADC Overflow Mode pin, the polarity bit is ignored. It is recommended that in this mode this bit be set to 0. GPO, Drive High - If the pin is configured as a general-purpose output driven high, the polarity bit is ignored. It is recommended that in this mode this bit be set to 0. 76543210 Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0
6.22.3 FUNCTIONAL CO NTROL (FUNCTIONX)
Default = 00000 Function: Mute Mode - If the pin is configured as a dedicated mute pin, the functional bits determine which chan- nel mutes will be mapped to this pin according to the following table. 0 - Channel mute is not mapped to the GPOx pin 1 - Channel mute is mapped to the GPOx pin: GPO, Drive Low / ADC Overflow Mode - If the pin is configured as a GPO, Drive Low / ADC Overflow Mode pin, the Function1 and Function0 bits determine how the output will behave according to the following table. It is recommended that in this mode the remaining functional bits be set to 0. GPO, Drive High - If the pin is configured as a general-purpose output, the functional bits are ignored and the pin is driven high. It is recommended that in this mode all the functional bits be set to 0. GPOx Reg Address Function4 Function3 Function2 Function1 Function0 GPO7 pin 42 29h M_AOUTA1 M_AOUTB1 M_AOUTA2 M_AOUTB2 M_AOUTA3 M_AOUTB3 M_AOUTA4 M_AOUTB4 GPO6 pin 43 2Ah M_AOUTA1 M_AOUTB1 M_AOUTA2 M_AOUTB2 M_AOUTA3 M_AOUTB3 M_AOUTA4 M_AOUTB4 GPO5 pin 44 2Bh M_AOUTA1 M_AOUTB1 M_AOUTA2 M_AOUTB2 M_AOUTA3 M_AOUTB3 M_AOUTA4 M_AOUTB4 GPO4 pin 45 2Ch M_AOUTA1 M_AOUTB1 M_AOUTA2 M_AOUTB2 M_AOUTA3 M_AOUTB3 M_AOUTA4 M_AOUTB4 GPO3 pin 46 2Dh M_AOUTA1 M_AOUTB1 M_AOUTA2 M_AOUTB2 M_AOUTA3 M_AOUTB3 M_AOUTA4 M_AOUTB4 GPO2 pin 47 2Eh M_AOUTA1 M_AOUTB1 M_AOUTA2 M_AOUTB2 M_AOUTA3 M_AOUTB3 M_AOUTA4 M_AOUTB4 GPO1 pin 48 2Fh M_AOUTA1 M_AOUTB1 M_AOUTA2 M_AOUTB2 M_AOUTA3 M_AOUTB3 M_AOUTA4 M_AOUTB4 Function1 Function0 GPOx Driver Type 0 0 Drive Low CMOS 1 1 OVFL R or L Open Drain
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- PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error
- APPENDIX A: EXTERNAL FILTERS
8.1 ADC Input Filter
general-purpose ceramics) must be avoided since these can degrade signal linearity.
8.2 DAC Output Filter
Figure 24. Recommended Analog Input Buffer Figure 25. Recommended Analog Output Buffer
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9.1 External Filter Components
9.1.1 General
The PLL behavior is affected by the external filter component values in the Typical Connection Diagrams. are worst case for an Fsi transition of 192 kHz. the PLL filter be returned directly to the AGND pin independently of the digital ground plane.
9.1.2 Capacitor Selection
tance. For CRIP, a C0G or NPO dielectric is recommended; and for CFILT, an X7R dielectric is preferred. are sensitive to shock and vibration. These include the Z5U and Y5V dielectrics. Table 16. PLL External Component Values
9.1.3 Circuit Board Layout
VA and AGND traces extend back to their origin and are shown only in truncated form in the drawing. Figure 26. Recommended Layout Example
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Figure 27. Single-Speed Mode Stopband Rejection Figure 28. Single-Speed Mode Transition Band Figure 29. Single-Speed Mode Transition Band (Detail) Figure 30. Single-Speed Mode Passband Ripple Figure 31. Double-Speed Mode Stopband Rejection Figure 32. Double-Speed Mode Transition Band
66 DS605F1
Figure 39. Single-Speed (fast) Stopband Rejection Figure 40. Single-Speed (fast) Transition Band Figure 41. Single-Speed (fast) Transition Band (detail) Figure 42. Single-Speed (fast) Passband Ripple Figure 43. Single-Speed (slow) Stopband Rejection Figure 44. Sing le-Speed (slow) Transition Band
68 DS605F1
Figure 51. Double-Speed (slow) Stopband Rejection Figure 52. Doub le-Speed (slow) Transition Band Figure 53. Double-Speed (slow) Transition Band (detail) Figure 54. Double-Speed (slow) Passband Ripple Figure 55. Quad-Speed (fast) Stopband Rejection Figure 56. Quad-Speed (fast) Transition Band
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12.PACKAGE DIMENSIONS THERMAL CHARACTERISTICS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 Parameter Symbol Min Typ Max Units Allowable Junction Temperature -- + 1 3 5 °C Junction to Ambient Thermal Impedance θJA -4 8 - ° C / W a t t 64L LQFP PACKAGE DRAWING E D1D e L B A
13.ORDERING INFORMATION 14.REFERENCES 1) Cirrus Logic, Audio Quality Measurement Specification , Version 1.0, 1997. http://www.cirrus.com/products/papers/meas/meas.html 2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 3) Cirrus Logic, Techniques to Meas ure and Maximize the Performance of a 120 dB, 96 kHz A/D Con- verter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Con- vention of the Audio Engineering Society, September 1997. 4) Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio , by D.R. Welland, B.P. Del Convention of the Audio Engineering Society, November 1988. 5) Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 6) Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Ap- plication Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 7) Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters ,by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 8) Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 9) Philips Semiconductor, The I2C-Bus Specification: Version 2.1 , January 2000. http://www.semicon- ductors.philips.com Product Description Package Pb-Free Grade Temp Range Container Order # CS42428 114 dB, 192 kHz 8-Ch Codec with PLL 64-pin LQFP YES Commercial -10° to +70° C Tray CS42428-CQZ Tape & Reel CS42428-CQZR Automotive -40° to +85° C Tray CS42428-DQZ Tape & Reel CS42428-DQZR CDB42428 CS42428 Evaluation Board No - - - CDB42428
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15.REVISION HISTORY Release Date Changes A1 May 2003 Advance Release A2 August 2004 Added lead free part numbers. F1 November 2005 Final Release – Added Revision History table on page 71. – Updated PLL components in Table 16 on page 62. – Added OMCK Frequency specificatio n in the Switching Characteristics table on page 11. – Updated ADC Input Impedance and Offset Error specifications in the Analog Input Characteristics table on page 7. – Updated the DAC Full-Scale Voltage, Output Impedance, and Gain Drift specifications in the Analog Output Characteristics table on page 9. – Updated specification conditions for the analog input characteristics on page 7. – Updated specification conditions for the analog output characteristics on page 9. – Updated specification of t ds, tdh, tdpd, and tlrpd in the Switching Characteristics table on page 11. – Corrected reference to the SW_CTRL[1:0] bits in section 4.4.3 on page 24. – Moved the VQ and FILT+ specific ations from the Analog Input Characteristics table on page 7 to the DC Electrical Characteristics table on page 14. – Updated the Power Supply Current and Power Consumption specifications in the DC Electrical Characteristics table on page 14. – Updated section 4.4.4 on page 24. – Corrected default value of the Chip _ID[3:0] bits in register 01h on pages 39 and 42. – Updated default value of the Rev_ID[3:0] bits in register 01h on pages 39 and 42. – Updated PLL_CLK[2:0] bit description on page 49.
Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc.