CS42324

CS42324 CIRRUS | Alldatasheet

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Copyright © Cirrus Logic, Inc. 2008 (All Rights Reserved)http://www.cirrus.com Advance Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. 10-In, 6-Out, 2 Vrms Audio CODEC D/A Features  Dual 24-bit Stereo DACs  Multi-bit Delta-Sigma Modulator  100 dB Dynamic Range (A-Wtd)  -90 dB THD+N  Integrated Line Driver – 2 Vrms Output – Single-Ended Outputs  Up to 96 kHz Sampling Rates  Stereo 7:1 Output Multiplexer  Volume Control with Soft Ramp – 0.5 dB Step Size – Zero Crossing Click-Free Transitions  Selectable Serial Audio Interface Formats – Left- or Right-Justified, Up to 24-bit – I²S Up to 24-bit  Selectable 50/15 μs De-Emphasis  Internal Analog Mute  Control Output for External Muting  Popguard® Technology A/D Features  Multi-bit Delta-Sigma Modulator  24-bit Conversion  Up to 96 kHz Sampling Rates  95 dB Dynamic Range (A-Wtd)  -88 dB THD+N  Stereo 5:1 Input Multiplexer  Digital Volume Control with Soft Ramp – 0.5 dB Step Size  Selectable Serial Audio Interface Formats – Left-Justified –I ² S  High-Pass Filter or DC Offset Calibration See System Features, General Description, and Order- ing information on page 2. 1.8 V to 3.3 V Internal Voltage Reference Multibit ΔΣ Modulator Multibit ΔΣ Modulator Stereo DAC Multibit Oversampling Stereo ADC Low-Latency Decimation Filter Stereo Input 1 Serial Audio Inputs Serial Audio Output 3.3 V 3.3 V 5:1 MUX 7:1 MUX Volume Control/Mixer Volume Control/Mixer PCM Serial Interface Mute Control Register Configuration Level Translator Level Translator Level Translator Reset SPI & I2C Control Data Mute 1 Mute 2 Mute 3 Stereo Input 2 Stereo Input 3 Stereo Input 4 Stereo Input 5 Interrupt ADC Overflow 7:1 MUX 7:1 MUX Stereo Output 1 Stereo Output 2 Stereo Output 3

9 V to12 V

JANUARY '08 DS721A6 CS42324

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 Direct Interface with 1.8 V to 3.3 V Logic Levels  Supports Asynchronous Serial Port Operation – Two Independent Clock Domains – ADC, DAC1, and DAC2 can be Independently Assigned to the Two Clock Domains – Each Serial Port Supports Master or Slave Operation  Internal Digital Loopback  +3.3 V Analog Power Supply  +3.3 V Digital Power Supply  +9 V to +12 V High-Voltage Power Supply  Hardware or Software Mode Configuration – Supports I²C ® and SPI™ Software Interface General Description The CS42324 is a highly integrated stereo audio CODEC. The CS42324 perf orms stereo analog-to- digital (A/D) and up to four channels of digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 96 kHz. A 5:1 stereo input multiplexe r is included for selecting between line-level inputs. The output of the input multi- plexer is followed by an advanced 3rd-order, multi-bit delta-sigma modulator and digital filtering/decimation. Sampled data is transmitted by the serial audio inter- face at rates from 4 kHz to 96 kHz, in either Slave or Master Mode. The D/A converter is based on a 5th-order multi-bit del- ta-sigma modulator with an ultra-linear low-pass filter and offers a volume control that operates with a 0.5 dB step size. It incorporates selectable soft ramp and zero crossing transition functions to eliminate clicks and pops. An integrated 7:1 stereo output multiplexer on each of the three stereo 2 Vrms line-level outputs is used to se- lect any of the 5 stereo analog inputs, for analog bypass support, or the outputs of the 2 internal DACs. Each

2 Vrms output can be muted with the selectable analog

mute function. Standard 50/15 μs de-emphasis is available for a 44.1 kHz sample rate for compatibility with digital audio programs mastered using the 50/15 μs pre-emphasis technique. Integrated digital level translators allow easy interfacing between the CS42324 and other devices operating over a wide range of logic levels. The CS42324 is available in a 48-pin LQFP package in Commercial (-40°C to +85°C) and Automotive (-40°C to +105°C) grades. The CDB42324 Customer Demonstra- tion board is also available for device evaluation and implementation suggestions. Please refer to “Ordering information” on page 71 for complete details.

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1. PIN DESCRIPTIONS

1.1 Software Mode

Pin Name # Pin Description SDA/CDOUT 1 I²C Format SDA (Input/Output) - Acts as an input/output data pin. An external pull-up resistor is required for I²C control port operation. SPI Format CDOUT (Output) - Acts as an output only data pin. SCL/CCLK 2 I²C Format, SCL (Input) – Serial clock for the serial control port. An external pull-up resistor is required for I²C control port operation. SPI Format, CCLK (Input) – Serial clock for the serial control port. AD0/CS 3 I²C Format, AD0 (Input) - Forms the device address input AD[0]. SPI Format, CS (Input) - Acts as the active low chip select input. AD1/CDIN 4 I²C Format, AD1 (Input) - Forms the device address input AD[1]. SPI Format, CDIN (Input) - Becomes the input data pin. INT 5 Interrupt (Output) - Indicates an interrupt condition has occurred. FILT+ 6 FILT+ (Output) - Full-scale reference voltage for ADC. VCMADC 7 ADC Common-Mode Voltage (Output) - Filter connections for the ADC internal quiescent refer- ence voltage. GND 8 Analog Ground (Input) - Analog ground reference. VA 9 Analog Power (Input) - Positive power for the internal analog section. VBIAS 10 Bias Voltage (Output) - Positive reference voltage for the internal DAC. MUTEC1 11 Mute Control 1 (Output) - Active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail output. This pin will become a high-impedance out- put during power-down mode or when an invalid MCLK to LRCK ratio is detected. OVFL SCL/CCLK GNDH SCLK1 AD0/CS AD1/CDIN INT SDA/CDOUT FILT+ VCMADC GND VA VBIAS MUTEC1 MUTEC2 VA_H AOUT1B AOUT2A AOUT2B AOUT3A AOUT3B MUTEC3 VCMBUF VCMDAC VA_H AOUT1A RST AIN1A AIN1B AIN2A AIN2B AIN3A AIN3B AIN4A AIN4B AIN5A AIN5B SDIN2 MCLK1 LRCK1 VD GND VL SDOUT SCLK2 LRCK2 MCLK2 SDIN1 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 CS42324

Mute Control 2 (Output) - Active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail output. This pin will become a high-impedance out- put during power-down mode or when an invalid MCLK to LRCK ratio is detected. MUTEC3 13 Mute Control 3 (Output) - Active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail output. This pin will become a high-impedance out- put during power-down mode or when an invalid MCLK to LRCK ratio is detected. VCMBUF 14 VCMBUF (Output) - Internally buffered VCMDAC VCMDAC 15 DAC Common-Mode Voltage (Output) - Filter connections for the DAC internal quiescent refer- ence voltage. VA_H 16 18 Analog High Voltage Power (Input) - Positive power for the internal output buffer section. GNDH 17 Analog Ground (Input) - Ground reference for high-voltage section. AOUT1A, AOUT1B AOUT2A, AOUT2B AOUT3A, AOUT3B 19, 20 21, 22 23, 24 DAC Analog Audio Outputs (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table. AIN5B, AIN5A AIN4B, AIN4A AIN3B, AIN3A AIN2B, AIN2A AIN1B, AIN1A 25, 26 27, 28 29, 30 31, 32 33, 34 Stereo Analog Inputs 1-5 (Input) - The full-scale input level is specified in the ADC Analog Char- acteristics specification table. RST 35 Reset (Input) - The device enters a low-power mode when this pin is driven low. OVFL 36 ADC Overflow (Output) - Indicates an ADC overflow condition is present. SDIN2 SDIN1 38 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. MCLK2 39 Master Clock 2 (Input) - Optional asynchronous clock source for the DAC’s delta-sigma modula- tors. LRCK2 40 Serial Port 2 Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is cur- rently active on the serial audio input data line. SCLK2 41 Serial Port 2 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 2. VD 42 Digital Power (Input) - Positive power for the internal digital section. GND 43 Digital Ground (Input) - Ground reference for the internal digital section. VL 44 Digital Interface Power (Input) - Determines the required signal level for the control and serial port interfaces as shown in “I/O Power Rails” on page 12. Refer to the“Recommended Operating Conditions” on page 13 for appropriate voltages. SDOUT 45 Serial Audio Data Output (Output) - Output for two’s complement serial audio data. SCLK1 46 Serial Port 1 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 1. LRCK1 47 Serial Port 1 Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is cur- rently active on the serial audio output data line. MCLK1 48 Master Clock 1 (Input) - Clock source for the ADC’s delta-sigma modulators. By default, this sig- nal also clocks the DAC’s delta-sigma modulators.

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1.2 Hardware Mode

Pin Name # Pin Description M0, M1 1, 2 Mode Selection (Input) - Determines the operational mode of the device. MDIV 3 MCLK Divider (Input) - Setting this pin high places a divide-by-2 circuit in the MCLK path to the core device circuitry. MUTE 4 MUTE (Input) - Engages the internal digital mute and activates the MUTECx pins DIF 5 DIF (Input) - Sets the serial audio interface format. Setting DIF high selects I²S audio format and low selects LJ audio format. FILT+ 6 FILT+ (Output) - Full-scale reference voltage for ADC. VCMADC 7 ADC Common-Mode Voltage (Output) - Filter connections for the ADC internal quiescent refer- ence voltage. GND 8 Analog Ground (Input) - Analog ground reference. VA 9 Analog Power (Input) - Positive power for the internal analog section. VBIAS 10 Bias Voltage (Output) - Positive reference voltage for the internal DAC. MUTEC1 11 Mute Control 1 (Output) - Active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail output. This pin will become a high-impedance out- put during power-down mode or when an invalid MCLK to LRCK ratio is detected. MUTEC2 12 Mute Control 2 (Output) - Active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail output. This pin will become a high-impedance out- put during power-down mode or when an invalid MCLK to LRCK ratio is detected. 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 OVFL RST AIN1A AIN1B AIN2A AIN2B AIN3A AIN3B AIN4A AIN4B AIN5A AIN5B MDIV MUTE DIF FILT+ VCMADC GND VA VBIAS MUTEC1 MUTEC2 SCLK1 SDIN2 MCLK1 LRCK1 VD GND VL SDOUT SCLK2 LRCK2 MCLK2 SDIN1 GNDH VA_H AOUT1B AOUT2A AOUT2B AOUT3A AOUT3B MUTEC3 VCMBUF VCMDAC VA_H AOUT1A CS42324

Mute Control 3 (Output) - Active-low mute output can drive external circuitry to eliminate the clicks and pops associated with any single-rail output. This pin will become a high-impedance out- put during power-down mode or when an invalid MCLK to LRCK ratio is detected. VCMBUF 14 VCMBUF (Output) - Internally buffered VCMDAC VCMDAC 15 DAC Common-Mode Voltage (Output) - Filter connections for the DAC internal quiescent refer- ence voltage. VA_H 16, 18 Analog High Voltage Power (Input) - Positive power for the internal output buffer section. GNDH 17 Analog Ground (Input) - Ground reference for high-voltage section. AOUT1A, AOUT1B AOUT2A, AOUT2B AOUT3A, AOUT3B 19, 20 21, 22 23, 24 DAC Analog Audio Outputs (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table. AIN5B, AIN5A AIN4B, AIN4A AIN3B, AIN3A AIN2B, AIN2A AIN1B, AIN1A 25, 26 27, 28 29, 30 31, 32 33, 34 Stereo Analog Inputs 1-5 (Input) - The full-scale input level is specified in the ADC Analog Char- acteristics specification table. RST 35 Reset (Input) - The device enters a low-power mode when this pin is driven low. OVFL 36 ADC Overflow (Output) - Indicates an ADC overflow condition is present. SDIN2 SDIN1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. MCLK2 39 Master Clock 2 (Input) - Optional asynchronous clock source for the DAC’s delta-sigma modula- tors. LRCK2 40 Serial Port 2 Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is cur- rently active on the serial audio input data line. SCLK2 41 Serial Port 2 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 2. VD 42 Digital Power (Input) - Positive power for the internal digital section. GND 43 Digital Ground (Input) - Ground reference for the internal digital section. VL 44 Digital Interface Power (Input) - Determines the required signal level for the control and serial port interfaces as shown in “I/O Power Rails” on page 12. Refer to the“Recommended Operating Conditions” on page 13 for appropriate voltages SDOUT 45 Serial Audio Data Output (Output) - Output for two’s complement serial audio data. SCLK1 46 Serial Port 1 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 1. LRCK1 47 Serial Port 1 Left Right/Clock (Input/Output) - Determines which channel, Left or Right, is cur- rently active on the serial audio output data line. MCLK1 48 Master Clock 1 (Input) - Clock source for the ADC’s delta-sigma modulators. By default, this sig- nal also clocks the DAC’s delta-sigma modulators.

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1.3 Digital I/O Pin Characteristics

2 SCL

3 AD0

4 AD1

35 RST

Table 1. I/O Power Rails

1. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = GNDH = 0 V; All voltages with respect to ground. ABSOLUTE MAXIMUM RATINGS GND = GNDH = 0 V; All voltages with respect to ground. (Note 1) Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transien t currents of up to ±100 mA on the analog input pins will not cause SCR latch-up. Parameters Symbol Min Nom Max Units DC Power Supplies: Analog Digital Logic High Voltage Analog VA VD VL VA_H 3.13 3.13 1.71 8.55 3.3 3.3 3.3 9.0 3.47 3.47 3.47 12.60 V V V V Ambient Operating Temperature (Power Applied) Commercial(-CQZ) Automotive(-DQZ) T A -40 -40 +85 +105 Parameter Symbol Min Max Units DC Power Supplies: Analog Digital Logic High Voltage Analog VA VD VL VA_H -0.3 -0.3 -0.3 -0.3 +4.50 +4.50 +4.50 +17.0 V V V V Input Current (Note 2) I in -10 +10 mA Analog Input Voltage V INA GND - 0.3 VA_H + 0.3 V Digital Input Voltage Logic V IND -0.3 VL + 0.4 V Ambient Operating Temperature (Power Applied) T A -55 +125 °C Storage Temperature T stg -65 +150 °C

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DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) Test Conditions (unless otherwise specified): VA = VD = VL = 3.3 V, VA_H = 9 V, GND = GNDH = 0 V; TA = 25° C; 997 Hz Full-Scale Output Sine Wave. Decoupling capacitors, Filter capacitors, and Recommended output filter as shown in Figure 7 on page 26 and Figure 8 on page 27; Fs = 48 kHz or 96 kHz; Synchronous Mode; Measurement Bandwidth 10 Hz to 20 kHz, Notes: 3. One-half LSB of triangular PDF dither added to data. 4. See Figures 1 and 2 on page 16. RL and CL reflect the minimum resistance and maximum capacitance allowed in order to maintain stability in the internal op-amp. CL affects the dominant pole of the internal output amp; increasing CL beyond 100 pF can cause the internal op-amp to become unstable. Parameter Symbol Min Typ Max Unit Dynamic Range (Note 3) 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 100 dB dB dB dB Total Harmonic Distortion + Noise (Note 3) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -90 -77 -37 -87 -77 -37 -84 -73 -33 -82 -62 -22 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - -100 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 0.25 dB Gain Drift - 100 - ppm/°C Analog Output Full-Scale Output Voltage 1.9 2.0 2.1 V rms Max current draw from an AOUT pin I OUT - 575 - μA AC-Load Resistance (Note 4) RL 5-- k Ω Load Capacitance (Note 4) CL -- 1 0 0 p F Output Impedance Z OUT -5 0- Ω

DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) VA_H = 8.55 V to 12.60 V, GND = GNDH = 0 V; TA = -40° C to +85° C; 997 Hz Full-Scale Output Sine Wave. Decoupling capacitors, filter capacitors, and recommended output filter as shown in Figure 7 on page 26 and Fig- ure 8 on page 27; Fs = 48 kHz or 96 kHz; Synchronous Mode; Measurement Bandwidth 10 Hz to 20 kHz, Parameter Symbol Min Typ Max Unit Dynamic Range (Note 3) 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted 100 dB dB dB dB Total Harmonic Distortion + Noise (Note 3) 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB THD+N -90 -77 -37 -87 -77 -37 -80 -67 -27 -77 -67 -27 dB dB dB dB dB dB Interchannel Isolation (1 kHz) - -100 - dB DC Accuracy Interchannel Gain Mismatch - 0.1 0.25 dB Gain Drift - 100 - ppm/°C Analog Output Full-Scale Output Voltage 1.9 2.0 2.1 V rms Max current draw from an AOUT pin I OUT -5 7 5- μA AC-Load Resistance (Note 4) RL 5-- k Ω Load Capacitance (Note 4) CL - - 100 pF Output Impedance Z OUT -5 0- Ω

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1. For Single-Speed Mode, the measurement bandwidth is from StopBand to 3 Fs.

For Double-Speed Mode, the measurement bandwidth is from StopBand to 3 Fs.

1. De-emphasis is available only in Single-Speed Mode.

Figure 1. Equivalent Analog Output Load Figure 2. Maximum Analog Output Loading

ADC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) Test Conditions (unless otherwise specified): VA = VD = VL = 3.3 V, VA_H = 9 V, GND = GNDH = 0 V; TA = 25° C; 997 Hz Input Sine Wave. Decoupling capacitors, filter capacitors, and recommended input filter as shown in Figure 7 on page 26 and Figure 8 on page 27; Fs = 48 kHz or 96 kHz; Synchronous Mode; Measurement Bandwidth

10 Hz to 20 kHz,

Note: 8. Referred to the typical line- level full-scale input voltage. Parameter Symbol Min Typ Max Unit Single-Speed Mode Dynamic Range A-weighted unweighted dB dB Total Harmonic Distortion + Noise (Note 8) -1 dB -20 dB -60 dB THD+N - -88 -72 -32 -80 dB dB dB Double-Speed Mode Dynamic Range A-weighted unweighted dB dB Total Harmonic Distortion + Noise (Note 8) -1 dB -20 dB -60 dB THD+N - -88 -72 -32 -80 dB dB dB DC Accuracy Interchannel Gain Mismatch - 0.1 - dB Gain Error -5 - +5% Gain Drift - ±100 - ppm/°C Analog Input Characteristics Full-scale Input Voltage 0.576•VA 0.606•VA 0.636•VA V rms Input Impedance - 200 - k Ω Maximum Interchannel Input Impedance Mismatch - 2 - % Interchannel Isolation (1 kHz) - -90 - dB

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ADC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) VA_H = 8.55 V to 12.60 V, GND = GNDH = 0 V; TA = -40° C to +85° C; 997 Hz Input Sine Wave. Decoupling capacitors, filter capacitors, and recommended input filter as shown in Figure 7 on page 26 and Figure 8 on page 27; Fs = 48 kHz or 96 kHz; Synchronous Mode; Measurement Bandwidth 10 Hz to 20 kHz, Note: 9. Referred to the typical line- level full-scale input voltage. Parameter Symbol Min Typ Max Unit Single-Speed Mode Dynamic Range A-weighted unweighted dB dB Total Harmonic Distortion + Noise (Note 8) -1 dB -20 dB -60 dB THD+N - -88 -72 -32 -78 dB dB dB Double-Speed Mode Dynamic Range A-weighted unweighted dB dB Total Harmonic Distortion + Noise (Note 8) -1 dB -20 dB -60 dB THD+N - -88 -72 -32 -78 dB dB dB DC Accuracy Interchannel Gain Mismatch - 0.1 - dB Gain Error -5 - +5% Gain Drift - ±100 - ppm/°C Analog Input Characteristics Full-scale Input Voltage 0.576•VA 0.606•VA 0.636•VA V rms Input Impedance - 200 - k Ω Maximum Interchannel Input Impedance Mismatch - 2 - % Interchannel Isolation (1 kHz) - -90 - dB

ADC DIGITAL FILTER CHARACTERISTICS Notes: 10. Response is clock dependent and will scale with sa mple rate (Fs). Note th at the response plots (Figures 23 to 30) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 11. Response shown is for Fs = 48 kHz. Parameter (Note 10) Symbol Min Typ Max Unit Single-Speed Mode Passband (-0.1 dB) 0 - 0.489 Fs Passband Ripple - - 0.035 dB Stopband 0.569 - - Fs Stopband Attenuation 70 - - dB Total Group Delay t gd -1 2 / F s - s Double-Speed Mode Passband (-0.1 dB) 0 - 0.489 Fs Passband Ripple - - 0.025 dB Stopband 0.5604 - - Fs Stopband Attenuation 69 - - dB Total Group Delay t gd -9 / F s - s High-Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB (Note 11) Hz Hz Phase Deviation @ 20 Hz (Note 11) -1 0 -D e g Passband Ripple --0 d B Filter Settling Time 105/Fs s

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ANALOG PASS-THRU CHARACTERISTICS Test Conditions (unless otherwise specified): VA = VD = VL = 3.3 V; VA_H = 9 V; GND = GNDH = 0 V; TA = 25° C; Input test signal is a 1 kHz sine wave; Measurement Bandwidth is 10 Hz to 20 kHz; Synchronous Mode. Note: 12. Referred to the typical line- level full-scale input voltage. Parameter Symbol Min Typ Max Unit Analog Input to Analog Output Characteristics (Gain=0dB) Dynamic Range A-weighted unweighted dB dB Total Harmonic Distortion + Noise (Note 8) 0d B -3 dB THD+N - -87 -93 -81 dB dB Frequency Response 10 Hz to 20 kHz - ±0.1 - dB Analog Characteristics Max Input Voltage - 2.0 - V rms Max Output Voltage - 2.0 - V rms Max current draw from an AOUT pin I OUT - 575 - μA AC-Load Resistance (Note 4) RL 5- - k Ω Load Capacitance (Note 4) CL - - 100 pF Output Impedance Z OUT -5 0- Ω Interchannel Isolation (1 kHz) - -90 - dB

DC ELECTRICAL CHARACTERISTICS GND = GNDH = 0 V; all voltages with respect to ground. MCLK1=12.288 MHz; MCLK2=static; Fs=48 kHz; Master Mode. Notes: 13. Power-Down Mode is defined as RST = Low, with all clock and data lines held static low and no analog input. 14. Valid with the recommended capacitor values on FILT+, VCMDAC, VCMADC and VCMBUF as shown in Figure 7 on page 26 and Figure 8 on page 27. 15. The DC current draw represents the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors. DIGITAL INTERFACE CHARACTERISTICS Note: 16. Digital Interface signals include all pins sourced from the VL supply as shown in “I/O Power Rails” on page 12. Parameter Symbol Min Typ Max Unit Power Supply Current (Normal Operation) VA_H = 9 V VA = 3.3 V VD = 3.3 V VL = 3.3 V IA_H IA ID IL mA mA mA mA Power Supply Current VA _H= 9 V (Power-Down Mode) (Note 13) VL=VD=VA=3.3 V IPD - 200 μA μA Power Consumption (Normal Operation) VA_H = 9 V VL=VD=VA = 3.3 V (Power-Down Mode) All supplies 216 169 0.7 289 225 mW mW mW Power Supply Rejection Ratio (1 kHz) (Note 14) PSRR - 60 - dB Reference Voltages VCMADC Nominal Voltage VCMADC - 0.5•VA - V VCMDAC Nominal Voltage VCMDAC - 4 - V DC Current from VCMADC or VCMDAC (Note 15) I CM -- 1 μA VCMADC or VCMDAC Output Impedance Z CM -2 3 - k Ω FILT+ Nominal Voltage FILT+ - VA - V VBIAS Nominal Voltage VBIAS - VA-0.8 - V Parameters (Note 16) Symbol Min Typ Max Units High-Level Input Voltage V IH 0.7•VL - - V Low-Level Input Voltage V IL - - 0.2•VL V High-Level Output Voltage at Io=2 mA Digital Interface MUTEC1/MUTEC2/MUTEC3 VOH VOH VL-1.0 VA_H-1.0 V V Low-Level Output Voltage at Io=2 mA Digital Interface MUTEC1/MUTEC2/MUTEC3 VOL VOL 0.4 0.4 V V Input Leakage Current I in -10 - +10 μA Input Capacitance - - 1 pF Maximum MUTEC1/MUTEC2/MUTEC3 Drive Current -3- m A Minimum OVFL Active Time μs106

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specified under “System Clocking” on page 28.

1. In Slave Mode, the SCLK/LRCK ratio can be set a ccording to preference. However, specified perfor-

4.2.2 Slave Mode on page 30. Figure 3. Serial Input Timing

Figure 4. Serial Output Timing

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Note: 19. Data must be held for sufficient ti me to bridge the transition time, tfc, of SCL. Figure 5. Software Mode Timing - I²C Format

Inputs: Logic ‘0’ = GND = GNDH = 0 V; Logic ‘1’ = VLC; CL =2 0p F . Notes: 20. t spi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

1. Data must be held for sufficient time to bridge the transition time of CCLK.
2. CDOUT should not be sampled during this time.

Figure 6. Software Mode Timing - SPI Mode

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1. TYPICAL CONNECTION DIAGRAMS

Figure 7. Typical Connection Diagram - Software Mode

2 Vrms Left

2 Vrms Right

Figure 8. Typical Connection Diagram - Hardware Mode

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4.1 System Clocking

speed modes as shown in Table 2.

4.1.1 Master Clock

Table 2. Speed Modes Table 3. Single-Speed Mode Common Clock Frequencies Table 4. Double-Speed Mode Common Clock Frequencies

4.1.2 Synchronous / Asynchronous Mode

serial ports may operate at different asynchronous rates. chronous operation are not available.

4.2 Serial Port Operation

master mode (LRCKx and SCLKx pins are outputs, generated clocks shown in Figure 9 are enabled). timing requirements outlined in “Switching Characteristics - Serial Audio” on page 22. the master/slave mode setting for the serial ports as well as the speed mode as shown in Table 5.

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Table 5. M1 and M0 Mode Pins in Hardware Mode Figure 9. Serial Port Topology

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4.2.1 Master Mode

from the MCLKx selected by the SP1_MCLK and SP2_MCLK signals as shown in Figure 10.

4.2.2 Slave Mode

to Table 6 for required serial bit clock to Left/Right clock ratios. nous / Asynchronous Mode” on page 29. of MCLKx using either the MCLKx FREQ bits or the MDIV hardware control pin. Table 6. Slave Mode SCLK/LRCK Ratios See Table 3 an Table 4 on page 28 for clock ratio configuration. Table 7. MCLKx to LRCKx Ratios Figure 10. Master Mode Clock Generation

4.2.3 ADC, DAC1, and DAC2 clock selection

converters discussed here are always slave. nous to the LRCK/SCLK selected by xxx_SP.

4.2.4 High-Impedance Digital Output

Figure 11. Converter Clocking Figure 12. Tri-State Serial Port

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4.2.5 Digital Interface Formats

4.2.6 Synchronization of Multiple Devices

CS42324 in Master Mode, and slave all of the other devices to the one master. Table 8. Hardware Mode Interface Format Control Figure 13. Left-Justified up to 24-Bit Data Figure 14. I²S up to 24-Bit Data Figure 15. Right-Justified 16-Bit Data, Right-Justified 24-Bit Data

4.3 Analog-to-Digital Data Path

4.3.1 ADC Analog Input Multiplexer

it to the ADC. Figure 16 shows the architecture of the input multiplexer. put multiplexer. By default, line level input 1 is selected.

4.3.2 ADC Description

since these can degrade signal linearity. Any unused analog input pairs should be left unconnected. toggle between ‘1’ and ‘0’, possibly introducing noise into the system as the bit switches back and forth. the specified offset level). Figure 16. Analog Input Architecture

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4.3.3 High-Pass Filter an d DC Offset Calibration

When using operational amp lifiers in the input circui try driving the CS42324, a small DC offset may be driven into the A/D converter. The CS42324 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding clicks when switching between de- vices in a multichannel system. The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPFFreeze bit is set during normal opera tion, the current value of the DC offset for the each channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1. Running the CS42324 with the high-pass filt er enabled until the filter settles. See “ADC Digital Filter Characteristics” on page 19 for filter settling time. 2. Disabling the high-pass filter and freezing th e stored DC offset for continuous subtraction. A system calibration performed in th is way eliminates offsets anywhere in the signal path between the calibration point and the CS42324.

4.3.4 Digital Attenuation Control

Digital attenuation control functions are implemented, offering independent channel control for the ADC PCM signal path. The volume controls are programmable to ramp in increments of 0.5 dB at a rate con- trolled by the ADC soft ramp. Each ADC signal path may also be independently mute d via mute control bits. When enabled, each bit attenuates the signal to its maximum value. When the mute bit is disabled, the signal returns to the atten- uation level set in the respective vo lume control register. The attenuation is ramped up and down at the rate specified by the ADC_SOFT.

4.4 Digital-to-Analog Data Path

4.4.1 Digital Volume Control

Two stereo digital volume control functions are im plemented, offering independent channel control for DAC1 and DAC2 PCM signal paths into the digital mixer. The volume controls are programmable to ramp in increments of 0.5 dB at a rate controlled by the DAC1/2 soft ramp/zero cross settings. Each DAC1/2 signal path may also be independen tly muted via mute control bits. When enabled, each bit attenuates the signal to its maxi mum value. When the mute bit is disabled, the signal returns to the attenuation level set in the respective volume control register. The attenuation is ramped up and down at the rate specified by the DAC1/2_SOFT and DAC1/2_ZC bits.

4.4.2 Mono Channel Mixer

Independent channel mixers for DAC1 and DAC2 may be used to create a mix of the left and right chan- nels PCM signals. This mix allows the user to pr oduce a MONO signal from a stereo source. The mixer may also be used to implement a left/right channel swap.

4.4.3 De-Emphasis Filter

with changes in sample rate, Fs.

4.4.4 Internal Digital Loopback

4.4.5 DAC Description

the DAC system phase and amplitude response will be dependent on the external analog circuitry. Figure 17. De-Emphasis Curve

36 DS721A6

4.4.6 Analog Output Multiplexer

shows the architecture of the analog output multiplexer. 0Eh)” on page 57 outline the bit settings necessary to control the output multiplexer.

4.4.7 Output Transient Control

the audio outputs. To make best use of this feature, it is necessary to understand its operation.

4.4.7.1 Power-Up

4.4.7.2 Power-Down

power may be re-applied at any time. Figure 18. Analog Output Architecture

4.4.7.3 Serial Interface Clock Changes

When changing the serial port clock ratio or sample rate, it is recommended that zero data (or near zero data) be present on SDIN for at least 10 LRCK sa mples before the change is made. During the clocking change, the DAC outputs will always be in a zero data state. If non-zero serial audio input is present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes to it’s zero data state.

4.4.8 Mute Control

The MUTECx pins become active during power-up initialization, reset, software/hardware muting, and power-down mode (PDN=1). The MUTECx pins are intended to be used as control for an external mute circuit in order to add off-chip mute capability. Use of the Mute Control function is not mandator y but recommended for designs requiring the absolute minimum in extraneous clicks an d pops. Also, use of the Mute C ontrol function can enable the system designer to achieve idle channel noise/signal-to-nois e ratios which are only limited by the external mute circuit. The MUTECx pins are active-low CMOS drivers.

4.5 Initialization

The initialization and Power-Down sequence flow chart is shown in Figure 19 on page 39. The CODEC en- ters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modu- lators and software registers are reset. The internal voltage reference, multi-bit DACs and ADC, and on-chip amplifiers are powered down.

4.5.1 Determining Hardwa re or Software Mode

The device will remain in the Power-Down state until the RST pin is brought high. If there is a pull-up on SDOUT, or SDOUT is held high by any other means at the time RST pin is brought high, the device will enter Hardware mode and begin powering up immediately. If no pull-up is present, or SDOUT is held low by any other means at the time RST pin is brought high, the device will enter software mode.

4.5.2 Hardware Mode Start-Up

When the pull-up on SDOUT is present Hardware Mo de is selected. Once hardware mode is selected, the hardware mode configuration pins are used to set up the device and power-up will occur following the HW startup path as shown in Figure 19 on page 39 . The modes of configuration for this mode can be found in Section 4.6.1 "Hardware Mode" on page 40. Because of the limited configuration abilities in Hard- ware mode, many modes of operation are not available. Only MCLK1 needs to be applied. Once the appropriate MCLK1 is valid and RST is high, the quiescent voltage, VCMADC and VCMBUF, and the internal voltage references, FILT+ and VCM_ADC, will begin powering up to normal operation. During this voltage reference ramp delay, both SDOUT and the AOUTxA/AOUTxB outputs will be auto matically muted. Once LRCKx is valid, MCLKx occurrences are counted over one LRCKx period to determine the MCLKx/LRCKx frequency ratio and normal operation begins. It is recommended that RST be activated if the analog or digital supplies drop below the recommended operating condition to prevent power-glitch-related issues.

38 DS721A6

4.5.2.1 Recommended Power-Up Sequence, Hardware Mode

1. Hold RST low until MCLK1 and the power supplies are stable. 2. Bring RST high (SDOUT must be pulled high). 3. Apply all LRCKx, SCLKx and SDIN signals for normal operation to begin. 4. Bring RST low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.

4.5.2.2 Recommended Power-Down Sequence, Hardware Mode

To minimize audible pops when turning off or placing the CODEC in standby: 1. Mute the SDIN1 and SDIN2 streams feeding the CODEC. 2. Bring RST low.

4.5.3 Software Mode Start-Up

When no pull-up on SDOUT is present, the Software Mode is accessible once RST is high. The desired register settings can be loaded per the interface descriptions in “Software Mode - I²C Control Port” on page 41. When the desired configuration is complete the PDN bit in “Operational Control (Address 02h)” on page 47 should be set to 0 to initiate the power up sequence. The quiescent voltage, VCMADC and VCMBUF, and the internal voltage references, FILT+ and VCM_ADC, will then begin powering up to nor- mal operation. During this voltage reference ramp delay, both SDOUT and the AOUTxA/AOUTxB outputs will be automatically muted. Once LRCKx is valid, MCLKx occurrences are counted over one LRCKx pe- riod to determine the MCLKx/LRCKx frequency ratio and normal operation begins. It is recommended that RST be activated if the analog or digital supplies drop below the recommended operating condition to prevent power-glitch-related issues.

4.5.3.1 Recommended Power-Up Sequence, Software Mode

1. Hold RST low until the power supplies are stable. 2. Bring RST high, the device will be in “standby”. 3. Load the desired register settings while keeping the PDN bit set to ‘1’b. 4. Start MCLK1 (and MCLK2 if it is used) to the appropriate frequency, as discussed in Section 4.1.1. 5. Set the PDN bit to ‘0’b. 6. Apply all LRCKx, SCLKx and SDIN signals for normal operation to begin. 7. Bring RST low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.

4.5.3.2 Recommended Power-Do wn Sequence, Software Mode

To minimize audible pops when turning off or placing the CODEC in standby: 1. Using the appropriate re gisters, 9Mute the AOUTxA, AOUTxB, DAC’s & ADC’s. 2. Set the PDN bit in the power cont rol register to ‘1’b. The CODEC will not power down until it reaches a fully muted sate. 3. Bring RST low.

4.5.4 Initialization Flow Chart

Figure 19. Initialization Flow Chart

1. No audio signal generated.
2. Control Port Registers reset
3. AOUTx bias = last audio sample.
4. DAC Modulators stop operation.
5. No audio signal generated.
6. Control Port Registers retain
7. Update Control Port Registers

Charged to quiescent voltage.

40 DS721A6

4.6 Device Control

interface. In Hardware Mode, a limited feature set may be controlled via hardware control pins.

4.6.1 Hardware Mode

Power-Up Sequence, Hardware Mode” on page 38 ) and may be controlled via hardware control pins. Table 9. Hardware Mode Feature Summary

4.6.2 Software Mode - I²C Control Port

desired. The state of the pin is sensed while the CS42324 is being reset. from the microcontroller after each transmitted byte. Figure 20. Software Mode Timing, I²C Write Figure 21. Software Mode Timing, I²C Read

42 DS721A6

Send start condition. Send 10011xx0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 10011xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.

4.6.3 Software Mode - SPI Control Port

In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial clock, CCLK (see Figure 22 for the clock to data relationship). There are no AD0 or AD1 pins. Pin CS is the chip select signal and is used to control SPI writes to the registers. When the device detects a high-to-low transition on the AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK.

4.6.3.1 SPI Write

To write to the device, follow the procedure below while adhering to the Software Mode switching speci- fications in “Switching Characteristics - Software Mode - SPI Format” section on page 25. 1. Bring CS low. 2. The address byte on the CDIN pin must then be 10011110 (R/W =0 ) . 3. Write to the memory address pointer, MAP. Th is byte points to the register to be written. 4. Write the desired data to the register pointed to by the MAP. 5. If the INCR bit (see Section 4.6.4.1) is set to 1, repeat the previous step until all the desired registers are written, then bring CS high. 6. If the INCR bit is set to 0 and furt her SPI writes to other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired, bring CS high

4.6.3.2 SPI Read

To read from the device, follow the procedure below while adhering to the values specified in “Switching Characteristics - Software Mode - SPI Format” section on page 25. 1. Bring CS low. 2. The address byte on the CDIN pin must then be 10011111 (R/W =1 ) . 3. CDOUT pin will then output the data from the register pointed to by the MAP, which is set during the SPI write operation. 4. If the INCR bit (see Section 4.6.4.1) is set to 1, keep CS low and continue providing clocks on CCLK to read from multiple consecutive registers. Bring CS high when reading is complete.

1. If the INCR bit is set to 0 and further SPI reads from other registers are desired, it is necessary to bring

4.6.4 Memory Addr ess Pointer (MAP)

pseudo code above for implementation details.

4.6.4.1 Map Increment (INCR)

will auto increment after each byte is written, allowing block reads or writes of successive registers.

4.7 Interrupts and Overflow

external pull-up resistor must be placed on the INT pin for proper operation. Status (Address 18h) (Read Only)” on page 61. Each source may be masked off through mask register bits. these conditions do not need to be unmasked for proper operation of the OVFL pin. Figure 22. Software Mode Timing, SPI Mode

44 DS721A6

1. REGISTER QU ICK REFERENCE This table shows the register names and their associated default values. All bits marked as “Reserved” must main- tain their default values. Addr Function 7 65 4 32 1 0 00h Device ID DEVICE3 DEVICE2 DEVICE1 DEVICE0 REV3 REV2 REV1 REV0 page 46 0110 xxxx 01h Mute Control Reserved SYS_MCLK DAC2_ MuteL DAC2_ MuteR DAC1_ MuteL DAC1_ MuteR ADC_ MuteL ADC_ MuteR page 46 01000000 02h Operational Control Reserved PDN INT_HL FREEZE Res erved TRI-SDOUT TRI-SP1 TRI-SP2 page 47 01000000 03h Serial Port 1 Control SP1_M/S Reserved Reserved SP1_ SPEED MCLK1 FREQ1 MCLK1 FREQ0 Reserved SP1_MCLK page 49 00000000 04h Serial Port 2 Control SP2_M/S Reserved Reserved SP2_ SPEED MCLK2 FREQ1 MCLK2 FREQ0 Reserved SP2_MCLK page 50 00000000 05h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 00000000 06h ADC clocking Reserved ADC_ MCLK Reserved ADC_ SP Reserved Reserved ADC_DIF1 ADC_DIF0 page 50 00001000 07h DAC1 clocking Reserved DAC1_ MCLK Reserved DAC1_SP Reserved Reserved DAC1_DIF1 DAC1_DIF0 page 51 00011000 08h DAC2 clocking Reserved DAC2_ MCLK Reserved DAC2_SP Reserved Reserved DAC2_DIF1 DAC2_DIF0 page 52 00011000 09h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 00000000 0Ah ADC Control Reserved ADC_ HPFRZ ADC_ SOFT Reserved Reserved AIN_SEL2 AIN_SEL1 AIN_SEL0 page 52 10100001 0Bh DAC1 Control DAC1_ DEPH DAC1_ SNGVOL DAC1_SOFT DAC1_ZC DAC1_ LOOPBACK DAC1_INV DAC1_MIX1 DAC1_MIX0 page 53 00100000 0Ch DAC2 Control DAC2_ DEPH DAC2_ SNGVOL DAC2_ SOFT DAC2_ ZC DAC2_ LOOPBACK DAC2_INV DAC2_MIX1 DAC2_MIX0 page 55 00100000 0Dh AOUT1 Control Reserved Reserve d Reserved Reserved MUTEC1 AOUT1_ SEL2 AOUT1_ SEL1 AOUT1_ SEL0 page 56 00000110 0Eh AOUT2 Control Reserved Reserve d Reserved Reserved MUTEC2 AOUT2_ SEL2 AOUT2_ SEL1 AOUT2_ SEL0 page 57 00000111 0Fh AOUT3 Control Reserved Reserve d Reserved Reserved MUTEC3 AOUT3_ SEL2 AOUT3_ SEL1 AOUT3_ SEL0 page 57 00000001

ADCA_ VOL7 ADCA_ VOL6 ADCA_ VOL5 ADCA_ VOL4 ADCA_ VOL3 ADCA_ VOL2 ADCA_ VOL1 ADCA_ VOL0 page 58 00000000 11h ADC Ch B Volume Control ADCB_ VOL7 ADCB_ VOL6 ADCB_ VOL5 ADCB_ VOL4 ADCB_ VOL3 ADCB_ VOL2 ADCB_ VOL1 ADCB_ VOL0 page 58 00000000 12h DAC1 Ch A Volume Control DAC1A_ VOL7 DAC1A_ VOL6 DAC1A_ VOL5 DAC1A_ VOL4 DAC1A_ VOL3 DAC1A_ VOL2 DAC1A_ VOL1 DAC1A_ VOL0 page 58 00000000 13h DAC1 Ch B Volume Control DAC1B_ VOL7 DAC1B_ VOL6 DAC1B_ VOL5 DAC1B_ VOL4 DAC1B_ VOL3 DAC1B_ VOL2 DAC1B_ VOL1 DAC1B_ VOL0 page 58 00000000 14h DAC2 Ch A Volume Control DAC2A_ VOL7 DAC2A_ VOL6 DAC2A_ VOL5 DAC2A_ VOL4 DAC2A_ VOL3 DAC2A_ VOL2 DAC2A_ VOL1 DAC2A_ VOL0 page 59 00000000 15h DAC2 Ch B Volume Control DAC2B_ VOL7 DAC2B_ VOL6 DAC2B_ VOL5 DAC2B_ VOL4 DAC2B_ VOL3 DAC2B_ VOL2 DAC2B_ VOL1 DAC2B_ VOL0 page 59 00000000 16h Interrupt Mode SP2_ CLKERR1 SP2_ CLKERR0 SP1_ CLKERR1 SP1_ CLKERR0 DAC_ AMUTE1 DAC_ AMUTE0 ADC_ OVFLx1 ADC_ OVFLx0 page 59 00000000 17h Interrupt Mask DAC2_ AMUTELM DAC2_ AMUTERM DAC1_ AMUTELM DAC1_ AMUTERM SP2_ CLKERRM SP1_ CLKERRM ADC_ OVFLPM ADC_ OVFLNM page 59 00000000 18h Interrupt Status DAC2_ AMUTEL DAC2_ AMUTER DAC1_ AMUTEL DAC1_ AMUTER SP2_ CLKERR SP1_ CLKERR ADC_ OVFLP ADC_ OVFLN page 61 00000000 Addr Function 7 65 4 32 1 0

46 DS721A6

1. REGISTER DESCRIPTION All registers are read/write except where otherwise noted. See the following bit definition tables for bit assignment information. The default state of each bi t after release of reset is listed in th e shaded row of each bit description table. When writing to registers containing “Reserved” bits, all bits marked as “Reserved” must maintain their default values. 6.1 Device I.D. and Revi sion Register (Address 00h) (Read Only) 6.1.1 Device I.D. (Read Only) I.D. code for the CS42324.

6.1.2 Chip Revision (Read Only)

CS42324 revision level.

6.2 Mute Control (Address 01h)

6.2.1 System MCLK Source

This bit selects which MCLK pin provides the clock fo r internal state machines. It must always be set to whichever clock is currently active.

6.2.2 Mute DAC2 Left-Channel

When set, this bit engages internal mute circuit on DAC2 output. 76543210 DEVICE3 DEVICE2 DEVICE1 DEVICE0 REV3 REV2 REV1 REV0 DEVICE[3:0] Device

0110 CS42324

REV[3:0] Revision Level 000 A1 001 B0 76543210 Reserved SYS_MCLK DAC2_ MuteL DAC2_ MuteR DAC1_ MuteL DAC1_ MuteR ADC_ MuteL ADC_ MuteR SYS_MCLK System MCLK source

0 MCLK1

1 MCLK2

DAC2_MuteL Mute status of DAC2 Left-channel

0 Un-muted

6.2.3 Mute DAC2 Right-Channel

When set, this bit engages internal mute circuit on DAC2 output.

6.2.4 Mute DAC1 Left-Channel

When set, this bit engages internal mute circuit on DAC1 output.

6.2.5 Mute DAC1 Right-Channel

When set, this bit engages internal mute circuit on DAC1 output.

6.2.6 Mute ADC Left-Channel

When set, this bit engages internal mute circuit on ADC output.

6.2.7 Mute ADC Right-Channel

When set, this bit engages internal mute circuit on ADC output.

6.3 Operational Control (Address 02h)

6.3.1 Global Power-Down

When set, this bit places the device in power-down mode. DAC2_MuteR Mute status of DAC2 Right-channel

1 Muted

DAC1_MuteL Mute status of DAC1 Left-channel

0 Unmuted

DAC1_MuteR Mute Status of DAC1 Right-Channel ADC_MuteL Mute Status of ADC Left-Channel ADC_MuteR Mute Status of ADC Right-Channel Reserved PDN INT_H/L FREEZE Reserved TRI-SDOUT TRI-SP1 TRI-SP2 PDN Device Power-Down State

0 Device is running

1 Device is in power-down mode

48 DS721A6

6.3.2 INT Pin High/ Low Active (INT_H/L)

6.3.3 Freeze

6.3.4 Tri-State SDOUT

When this bit is set, SDOUT will be placed in a high-impedance state.

6.3.5 Tri-State Serial Port 1

LRCK1 will remain as inputs.

0 Active low, open drain driver

1 Active high, CMOS driver

0 Changes to registers take effect immediately

1 Changes to registers are held until FREEZE is released

Table 10. Freeze-able Bits

0 Output

1 High-impedance

0 SCLK1 and LRCK1 operate as inputs if Serial Port 1 is configured as a slave; SCLK1 and LRCK1

1 SCLK1 and LRCK1 operate as inputs if Serial Po rt 1 is configured as a slave; SCLK1 and LRCK1

6.3.6 Tri-State Serial Port 2

When enabled, and the device is configured as a master, then SCLK2 and LRCK2 of Serial Port 2 (SP2) will be placed in a high-impedance output state. If Serial Port 2 is configured as a slave, SCLK2 and LRCK2 will remain as inputs. SDIN1 and SDIN2 are always configured as inputs.

6.4 Serial Port 1 Control (Address 03h)

6.4.1 Serial Port 1 Master/Slave Select

This bit configures Serial Port 1 to operate as either a clock master or clock slave.

6.4.2 Serial Port 1 Speed Mode

In Master Mode this bit configures the speed mode of Serial Port 1.

6.4.3 MCLK1 Divider

These bits configure the internal MCLK1 dividers.

6.4.4 Serial Port 1 MCLK source

This bit selects which MCLK pin provides the clock for deriving Master Mode sub-clocks for Serial Port 1. TRI-SP2 SCLK2 and LRCK2 State

0 SCLK2 and LRCK2 operate as inputs if Serial Port 2 is configured as a slave; SCLK2 and LRCK2

operate as outputs if Serial Port 2 is configured as a master

1 SCLK2 and LRCK2 operate as inputs if Serial Port 2 is configured as a slave; SCLK2 and LRCK2

become high-impedance outputs if Serial Port 2 is configured as a master 76543210 SP1_M/S Reserved Reserved SP1_SPEED MCLK1 FREQ1 MCLK1 FREQ0 Reserved SP1_MCLK SP1_M/S Serial Port 1 Master/Slave Select

0 Slave Mode

1 Master Mode

SP1_SPEED Serial Port 1 Speed Mode

0 Single-Speed Mode (SSM)

1 Double-Speed Mode (DSM)

FREQ[1:0] MCLK Divider 00 ÷1 01 ÷1.5 10 ÷2 11 ÷3 SP1_MCLK Serial Port 1 MCLK source

50 DS721A6

6.5 Serial Port 2 Control (Address 04h)

6.5.1 Serial Port 2 Master/Slave Select

This bit configures Serial Port 2 to operate as either a clock master or clock slave.

6.5.2 Serial Port 2 Speed Mode

In Master Mode this bit configures the speed mode of Serial Port 2.

6.5.3 MCLK2 Divider

These bits configure the internal MCLK2 dividers.

6.5.4 Serial Port 2 MCLK Source

This bit selects which MCLK pin provides the clock for deriving Master Mode sub-clocks for Serial Port 2.

6.6 ADC Clocking (Address 06h)

6.6.1 ADC MCLK Source

This bit selects which MCLK pin provides the clock for the ADC. 76543210 SP2_M/S Reserved Reserved0 SP2_SPEED MCLK2 FREQ1 MCLK2 FREQ0 Reserved SP2_MCLK SP2_M/S Serial Port 2 Master/Slave Select SP2_SPEED Serial Port 2 Speed Mode FREQ[1:0] MCLK Divider 00 ÷1 01 ÷1.5 10 ÷2 11 ÷3 SP2_MCLK Serial Port 2 MCLK source Reserved ADC_MCLK Reserved ADC_SP Reserved Reserved ADC_DIF1 ADC_DIF0 ADC_MCLK ADC MCLK source

6.6.2 ADC Serial Port Source

This bit selects which serial port provides the sub clocks for the ADC.

6.6.3 ADC Digital Interface Format (ADC_DIF)

These bits configure the serial audio interface format for transmitting digital audio data on SDOUT

6.7 DAC1 Clocking (Address 07h)

6.7.1 DAC1 MCLK Source

This bit selects which MCLK pin provides the clock for DAC1.

6.7.2 DAC1 Serial Port Source

This bit selects which serial port provides the sub clocks for the DAC1.

6.7.3 DAC1 Digital Interf ace Format (DAC1_DIF)

These bits configure the serial audio interface format for incoming digital audio data on SDIN1. ADC_SP ADC sub clock source

0 Serial Port 1 (SCLK1/LRCK1)

1 Serial Port 2 (SCLK2/LRCK2)

ADC_DIF[1:0] ADC Serial Au dio Interface Format

00 Left-Justified, 24-bit data

01 I²S, 24-bit data

10 Reserved

11 Reserved

Reserved DAC1_MCLK Reserved DAC1_SP Reserved Reserved DAC1_DIF1 DAC1_DIF0 DAC1_MCLK DAC1 MCLK source DAC1_SP DAC1 sub clock source DAC1_DIF[1:0] DAC1 Serial Audio Interface Format

00 Left-Justified, up to 24-bit data

01 I²S, up to 24-bit data

10 Right Justified, 16-bit data

11 Right Justified, 24-bit data

52 DS721A6

6.8 DAC2 Clocking (Address 08h)

6.8.1 DAC2 MCLK Source

This bit selects which MCLK pin provides the clock for DAC2.

6.8.2 DAC2 Serial Port Source

This bit selects which serial port provides the sub clocks for the DAC2.

6.8.3 DAC2 Digital Inte rface Format (DAC2_DIF)

These bits configure the serial audio interface format for incoming digital audio data on SDIN2.

6.9 ADC Control (Address 0Ah)

6.9.1 ADC High-Pass Filter Freeze

The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the decimation filter. If the ADC_HPFRZ bit is taken high during normal operation, the current value of the DC offset is frozen and this DC offset will continue to be subtracted from the conversion result. For DC mea- surements, this bit must be set to ‘1’.

6.9.2 ADC Soft Ramp Control

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. 76543210 Reserved DAC2_MCLK Reserved DAC2_SP Reserved Reserved DAC2_DIF1 DAC2_DIF0 DAC2_MCLK DAC2 MCLK source DAC2_SP DAC2 sub clock source DAC2_DIF[1:0] DAC2 Serial Audio Interface Format Reserved ADC_HPFRZ ADC_SOFT Reserved Reserved AIN_SEL2 AIN_SEL1 AIN_SEL0 ADC_HPFRZ ADC High-Pass Filter Freeze

0 Continuous DC Subtraction

1 Fixed DC Subtraction

6.9.3 Analog Input Selection

These bits are used to select the input source for the ADC.

6.10 DAC1 Control (Address 0Bh)

6.10.1 DAC1 De-Emphasis Control

This bit enables the digital filter to apply the standard 15μs/50μs digital de-emphasis filter response for a sample rate (Fs) of 44.1 kHz. De-emphasis is available only in Single-Speed Mode.

6.10.2 DAC1 Single Volume Control

The individual channel volume levels are independently controlled by their respective Volume Control reg- isters when this function is disabled. When enabled, the volume on DAC1 channels is determined by the DAC1A Volume Control register and the DAC1B Volume Control register is ignored.

6.10.3 DAC1 Soft Ramp Control

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. ADC_SOFT ADC Soft Ramp Control

0 Off

AIN_SEL[2:0] ADC Soft Ramp Control

000 Reserved

001 Line-Level Input Pair 1

010 Line-Level Input Pair 2

011 Line-Level Input Pair 3

100 Line-Level Input Pair 4

101 Line-Level Input Pair 5

110 Reserved

111 Reserved

DAC1_DEPH DAC1_SNGV OL DAC1_SOFT DAC1_ZC DAC1_ LOOPBACK DAC1_INV DAC1_MIX1 DAC1_MIX0 DAC1_DEPH DAC1 De-Emphasis Control 1 On (valid for Fs = 44.1 kHz) DAC1_SNGVOL DAC1 Single Volume Control DAC1_SOFT DAC1 Soft Ramp Control 0O f f 1 On

54 DS721A6

6.10.4 DAC1 Zero Cross Control

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time- out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut- ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam- ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon- itored and implemented for each channel.

6.10.5 DAC1 Loop-Back

Loops ADC SDOUT, SCLK, and LRCK to DAC1 serial port pins.

6.10.6 DAC1 Invert Signal Polarity

When enabled, this bit will effect a 180 degree phase shift in the DAC1 channels.

6.10.7 DAC1 Channel Mixer

These bits implement mono mixes of the left and right channels as well as a left/right channel swap. DAC1_SOFT DAC1_ZC Mode 0 0 Changes to affect immediately 0 1 Zero Cross enabled 1 0 Soft Ramp enabled 1 1 Soft Ramp and Zero Cross enabled DAC1_LOOP_ BACK DAC1 Loop-Back DAC1_INV DAC1 Invert Signal Polarity DAC1_MIX[1:0] DAC1 OUTA DAC1 OUTB

00 L R

11 R L

6.11 DAC2 Control (Address 0Ch)

6.11.1 DAC2 De-Emphasis Control

This bit enables the digital filter to apply the standard 15μs/50μs digital de-emphasis filter response for a sample rate (Fs) of 44.1 kHz. De-emphasis is available only in Single-Speed Mode.

6.11.2 DAC2 Single Volume Control

The individual channel volume levels are independently controlled by their respective Volume Control reg- isters when this function is disabled. When enabled, the volume on DAC2 channels is determined by the DAC2A Volume Control register and the DAC2B Volume Control register is ignored.

6.11.3 DAC2 Soft Ramp Control

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.

6.11.4 DAC2 Zero Cross Control

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time- out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut- ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam- ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon- itored and implemented for each channel. 76543210 DAC2_DEPH DAC2_ SNGVOL DAC2_SOFT DAC2_ZC DAC2_ LOOP_BACK DAC2_INV DAC2_MIX1 DAC2_MIX0 DAC2_DEPH DAC2 De-Emphasis Control 1 On (valid for Fs = 44.1 kHz) DAC2_SNGVOL DAC2 Single Volume Control DAC2_SOFT DAC2 Soft Ramp Control 0O f f 1 On DAC2_SOFT DAC2_ZC Mode 0 0 Changes to affect immediately 0 1 Zero Cross enabled 1 0 Soft Ramp enabled 1 1 Soft Ramp and Zero Cross enabled

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6.11.5 DAC2 Loop-Back

Loops ADC SDOUT, SCLK, and LRCK to DAC1 serial port pins.

6.11.6 DAC2 Invert Signal Polarity

When enabled, this bit will effect a 180 degree phase shift in the DAC2 channels.

6.11.7 DAC2 Channel Mixer

These bits implements mono mixes of the left and right channels as well as a left/right channel swap.

6.12 AOUT1 Control (Address 0Dh)

6.12.1 External Mute Control Pin

This bit controls the logic state of the corresponding MUTEC1 pin. Though this bit is active high, it should be noted that the MUTEC1 pin is active low.

6.12.2 AOUT1 Select

These bits are used to select the analog output source. DAC2_LOOP_ BACK DAC2 Loop-Back DAC2_INV DAC2 Invert Signal Polarity DAC2_MIX[1:0] DAC2 OUTA DAC2 OUTB Reserved Reserved Reserved Reserved MU TEC1 AOUT1_SEL2 AOUT1_SEL1 AOUT1_SEL0 MUTEC1 Output on MUTEC1 pin

0 High (Mute Disengaged)

1 Low (Mute Engaged)

AOUT1_SEL[2:0] AOUT1 Source

001 AIN Pair 1

010 AIN Pair 2

011 AIN Pair 3

100 AIN Pair 4

101 AIN Pair 5

110 DAC1 Output Pair

111 DAC2 Output Pair

6.13 AOUT2 Control (Address 0Eh)

6.13.1 External Mute Control Pin

This bit controls the logic state of the corresponding MUTEC2 pin. Though this bit is active high, it should be noted that the MUTEC2 pin is active low.

6.13.2 AOUT2 Select

These bits are used to select the analog output source.

6.14 AOUT3 Control (Address 0Fh)

6.14.1 External Mute Control Pin

This bit controls the logic state of the corresponding MUTEC3 pin. Though this bit is active high, it should be noted that the MUTEC3 pin is active low. 76543210 Reserved Reserved Reserved Reserved MUTEC2 AOUT2_SEL2 AOUT2_SEL1 AOUT2_SEL0 MUTEC2 Output on MUTEC2 pin AOUT2_SEL[2:0] AOUT2 Source Reserved Reserved Reserved Reserved MUTEC3 AOUT3_SEL2 AOUT3_SEL1 AOUT3_SEL0 MUTEC3 Output on MUTEC3 pin

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6.14.2 AOUT3 Select

These bits are used to select the analog output source.

6.15 ADCx Volume Control: ADCA (Address 10h) & ADCB (Address 11h)

The level for each channel of the ADC can be adjusted in 0.5 dB increments as dictated by the ADC Soft and Zero Cross bits (ADC_SOFT) from +12 to -84 dB. Levels are decoded in two’s complement, as shown in the table below.

6.16 DAC1x Volume Control: DAC1A (Address 12h) & DAC1B (Address 13h)

The level for each channel of DAC1 output can be adj usted in 0.5 dB increments as dictated by the DAC1 Soft and Zero Cross bits (DAC1_SOFT & DAC1_ZC) from 0 to -127.5 dB. Levels are decoded as unsigned, as shown in the table below. AOUT3_SEL[2:0] AOUT3 Source ADCx_VOL7 ADCx_VOL6 ADCx_VOL5 ADCx_VOL4 ADCx_VOL3 ADCx_VOL2 ADCx_VOL1 ADCx_VOL0 Binary Code Volume Setting 0001 1000 +12.0 dB 0000 0000 0.0 dB 1111 1111 -0.5 dB 1111 1110 -1.0 dB 0101 1000 -84.0 dB All other values Reserved 76543210 DAC1x_VOL7 DAC1x_VOL6 DAC1x_VOL5 DAC1x_VOL4 DAC1x_VOL3 DAC1x_VOL2 DAC1x_VOL1 DAC1x_VOL0 Binary Code Volume Setting 0000 0000 0 dB 0000 0001 -0.5 dB 0000 0010 -1.0 dB 1111 1111 -127.5 dB

6.17 DAC2x Volume Control: DAC1A (Address 14h) & DAC1B (Address 15h)

The level for each channel of DAC2 output can be ad justed in 0.5 dB increments as dictated by the DAC2 Soft and Zero Cross bits (DAC2_SOFT & DAC2_ZC) from 0 to -127.5 dB. Levels are decoded in unsigned, as shown in the table below.6.18 Interrupt Mode (Address 16h) The Interrupt Mode register contains four two-bit codes which correspond to either an Interrupt Status bit or group of bits as shown below. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising-edge Active Mode, the INT pin becomes active on the arrival of the interrupt condi- tion. In the Falling-edge Active Mode, the INT pin becomes active on the removal of the interrupt condition. In Level Active Mode, the INT pin remains active during the interrupt condition .

6.19 Interrupt Mask (Address 17h)

These bits are mask bits for the corresponding bits in the “Interrupt Status (Address 18h) (Read Only)” reg- ister on page 61. 76543210 DAC2x_VOL7 DAC2x_VOL6 DAC2x_VOL5 DAC2x_VOL4 DAC2x_VOL3 DAC2x_VOL2 DAC2x_VOL1 DAC2x_VOL0 Binary Code Volume Setting 0000 0000 0 dB 0000 0001 -0.5 dB 0000 0010 -1.0 dB 1111 1111 - 127.5 dB 76543210 SP2_ CLKERR1 SP2_ CLKERR0 SP1_ CLKERR1 SP1_ CLKERR0 DAC_AMUTE1 DAC_AMUTE0 ADC_ OVFLx1 ADC_ OVFLx0 Interrupt Mode Associated Interrupt Status Bit(s) SP2_CLKERR[1:0] SP2_CLKERR SP1_CLKERR[1:0] SP1_CLKERR DAC_AMUTE[1:0] DAC2_AMUTEL, DAC2_A MUTER, DAC1_AMUTEL, DAC1_AMUTER ADC_AVFLx[1:0] ADC_OVFLP , ADC_OVFLN Bit Settings Interrupt Mode Setting

00 Rising-edge Active

01 Falling-edge Active

10 Level Active

DAC2_ AMUTELM DAC2_ AMUTERM DAC1_ AMUTELM DAC1_ AMUTERM SP2_ CLKERRM SP1_ CLKERRM ADC_ OVFLPM ADC_ OVFLNM Bit Settings Bit in Interrupt Register

0 Not Masked

1 Masked

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6.19.1 DAC2 Auto Mute Left Mask (DAC2_AMUTELM)

This bit serves as a mask for the DAC2 Auto Mute Left interrupt source. If this bit is cleared, the DAC2_AMUTEL interrupt is unmasked, meaning that if the DAC2_AMUTEL condition occurs, the INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If the DAC2_AMUTELM bit is set, the DAC2_AMUTEL condition is masked, meaning that its oc- currence will not affect the INT pin.

6.19.2 DAC2 Auto Mute Ri ght Mask (DAC2_AMUTERM)

This bit serves as a mask for the DAC2 Auto Mute Left interrupt source. If this bit is cleared, the DAC2_AMUTER interrupt is unmasked, meaning that if the DAC2_AMUTER condition occurs, the INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If the DAC2_AMUTERM bit is set, the DAC2_AMU TER condition is masked, meaning that its occurrence will not affect the INT pin.

6.19.3 DAC1 Auto Mute Left Mask (DAC1_AMUTELM)

This bit serves as a mask for the DAC1 Auto Mute Left interrupt source. If this bit is cleared, the DAC1_AMUTEL interrupt is unmasked, meaning that if the DAC1_AMUTEL condition occurs, the INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If the DAC1_AMUTELM bit is set, the DAC1_AMUTEL condition is masked, meaning that its oc- currence will not affect the INT pin.

6.19.4 DAC1 Auto Mute Ri ght Mask (DAC1_AMUTELM)

This bit serves as a mask for the DAC1 Auto Mute Left interrupt source. If this bit is cleared, the DAC1_AMUTER interrupt is unmasked, meaning that if the DAC1_AMUTER condition occurs, the INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If the DAC1_AMUTERM bit is set, the DAC1_AMU TER condition is masked, meaning that its occurrence will not affect the INT pin.

6.19.5 Serial Port 2 Clock Error Mask (SP2_CLKERRM)

This bit serves as a mask for the serial port 2 clock error interrupt source. If this bit is cleared, the SP2_CLKERR interrupt is unmasked, meaning that if the SP2_CLKERR bit is set, the INT pin will go ac- tive according to the SP2_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If the SP2_CLKERRM bit is set, the SP2_CLKERR condition is masked, meaning that its occurrence will not affect the INT pin.

6.19.6 Serial Port 1 Clock Error Mask (SP1_CLKERRM)

This bit serves as a mask for the serial port 1 clock error interrupt source. If this bit is cleared, the SP1_CLKERR interrupt is unmasked, meaning that if the SP1_CLKERR bit is set, the INT pin will go ac- tive according to the SP1_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If the SP1_CLKERRM bit is set, the SP1_CLKERR condition is masked, meaning that its occurrence will not affect the INT pin.

6.19.7 ADC Positive Over flow Mask (ADC_OVFLPM)

This bit serves as a mask for the ADC positive over flow interrupt source. If th is bit is cleared, the ADC_OVFLP interrupt is unmasked, meaning that if the ADC_OVFLP conditions are met in the interrupt status register, the INT pin will go active according to the ADC_OVFLx[1:0] bits in the “Interrupt Mode (Ad- dress 16h)” register on page 59. If the ADC_OVFLPM bit is set, the ADC_OVFLP condition is masked, meaning that its occurrence will not affect the INT pin. However, the OVFL pin will continue to reflect the overflow state of the ADC.

6.19.8 ADC Negative Overfl ow Mask (ADC_OVFLNM)

This bit serves as a mask for the ADC negative over flow interrupt source. If this bit is cleared, the ADC_OVFLN interrupt is unmasked, meaning that if the ADC_OVFLN conditions are met in the interrupt status register, the INT pin will go active according to the ADC_OVFLx[1:0] bits in the “Interrupt Mode (Ad- dress 16h)” register on page 59. If the ADC_OVFLNM bit is set, the ADC_OVFLN condition is masked, meaning that its occurrence will not affect the INT pin. However, the OVFL pin will continue to reflect the overflow state of the ADC.

6.20 Interrupt Status (Address 18h) (Read Only)

This register defaults to 00h and is read only. If the INT pin is active, reading this register clears the interrupt condition.

6.20.1 DAC2 Auto Mute Left Interrupt Status (DAC2_AMUTEL)

This bit is read only. When set, indicates that DAC2 left channel has had an auto-mute condition since the last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive sam- ples of zeroes or ones on the left channel of SDIN2, will cause this bit to be set. This interrupt status bit is an edge-triggered event and will be cleared following a read of this register. The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” on page 59 and the status of this bit if DAC2_AMUTELM bit is cleared.

6.20.2 DAC2 Auto Mute Right Interrupt Status (DAC2_AMUTER)

This bit is read only. When set, indicates that DAC2 right channel has had an auto-mute condition since the last read of this register. Conditions which c ause an auto-mute, such as receiving 4096 consecutive samples of zeroes or ones on the right channel of SDIN2, will cause this bit to be set. This interrupt status bit is an edge-triggered event and will be cleared following a read of this register. The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” on page 59 and the status of this bit if DAC2_AMUTERM bit is cleared. 76543210 DAC2_ AMUTEL DAC2_ AMUTER DAC1_ AMUTEL DAC1_ AMUTER SP2_ CLKERR SP1_ CLKERR ADC_ OVFLP ADC_ OVFLN Bit Settings Bit in Interrupt Register 0 Interrupt has not occurred since the last read of this register. 1 Interrupt has occurred since the last read of this register.

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6.20.3 DAC1 Auto Mute Left In terrupt Status (DAC1_AMUTEL)

This bit is read only. When set, indicates that DAC1 left channel has had an auto-mute condition since the last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive sam- ples of zeroes or ones on the left ch annel of SDIN1, will cause this bit to be set. This interrupt status bit is an edge-triggered event and will be cleared following a read of this register. The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” on page 59 and the status of this bit if DAC1_AMUTELM bit is cleared.

6.20.4 DAC1 Auto Mute Right In terrupt Status (DAC1_AMUTEL)

This bit is read only. When set, indicates that DA C1 right channel has had an auto-mute condition since the last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive samples of zeroes or ones on the right channel of SDIN1, will cause this bit to be set. This interrupt status bit is an edge-triggered event and will be cleared following a read of this register. The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” on page 59 and the status of this bit if DAC1_AMUTERM bit is cleared.

6.20.5 Serial Port 2 Clock Error Interrupt Status (SP2_CLKERR)

This bit is read only. When set, indicates that Serial Port 2 has had a clock error since the last read of this register. Conditions which cause a clock error in th e serial port, such as loss of LRCK2, SCLK2, an MCLKx/LRCK2 ratio change, or speed mode change, will cause this bit to be set. This interrupt bit is an edge-triggered event and will be cleared following a read of this register. The INT pin will go active according to the SP2_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)” on page 59 and the status of this bit if SP2_CLKERRM bit is cleared.

6.20.6 Serial Port 1 Clock Error Interrupt Status (SP1_CLKERR)

This bit is read only. When set, indicates that Serial Port 1 has had a clock error since the last read of this register. Conditions which cause a clock error in th e serial port, such as loss of LRCK1, SCLK1, an MCLKx/LRCK1 ratio change, or speed mode change, will cause this bit to be set. This interrupt bit is an edge-triggered event and will be cleared following a read of this register. The INT pin will go active according to the SP1_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)” on page 59 and the status of this bit if SP1_CLKERRM bit is cleared.

6.20.7 ADC Positive Overflow Interrupt Bit (ADC_OVFLP)

This bit is read only. When set, indicates that a pos itive over-range condition occurred anywhere in the CS42324 ADC signal path and has ADC data has been clipped to positive full scale since the last read of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this reg- ister. The INT pin will go active according to the ADC_OVFLx[1:0] bits in the “Interrupt Mode (Address 16h)” on page 59 and the status of this bit if ADC_OVFLPM bit is cleared. To determine the current overflow state of the ADC use the OVFL pin.

6.20.8 ADC Negative Overflow Interrupt Bit (ADC_OVFLN)

This bit is read only. When set, indicates that a ne gative over-range condition occurred anywhere in the CS42324 ADC signal path and has ADC data has been clipped to negative full scale since the last read of this register. This interrupt bit is an edge-trig gered event and will be cleared following a read of this register. The INT pin will go active according to the ADC_OVFLx[1:0] bits in the “Interrupt Mode (Address 16h)” on page 59 and the status of this bit if ADC_OVFLNM bit is cleared. To determine the current overflow state of the ADC use the OVFL pin.

64 DS721A6

1. GROUNDING AND POWE R SUPPLY DECOUPLING As with any high-resolution converter, the CS42324 requires careful attention to power supply and grounding ar- rangements if its potential perf ormance is to be realized. Figure 7 on page 26 shows the recommended power ar- rangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the system logic supply (VL) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as near to the CS42324 as possible, with the low value ceramic ca- pacitor being the nearest. All signals, especially clocks , should be kept away from the FILT+, VCM_ADC, VBIAS, VCMBUF, and VCMDAC pins in order to avoid unwanted coupling into the modulators. The FILT+, VCM_ADC, VBIAS, VCMBUF, and VCMDAC decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from each pin to GND. The CS42324 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the CS42324 digital outputs only to CMOS inputs.

66 DS721A6

Figure 29. Double-Speed Mode Transition Band (Detail) Figure 30. Double-Speed Mode Passband Ripple

68 DS721A6

Figure 37. Double-Speed Transition Band (detail) Figure 38. Double-Speed Passband Ripple Figure 39. Quad-Speed Stopband Rejection Figure 40. Quad-Speed Transition Band Figure 41. Quad-Speed Transition Band (detail) Figure 42. Quad-Speed Passband Ripple

10.PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measure- ment. This measurement technique has been accept ed by the Audio Engineer ing Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kH z), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right chan nels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci- bels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error

70 DS721A6

11.PACKAGE DIMENSIONS THERMAL CHARACTERISTICS AND SPECIFICATIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX * Nominal pin pitch is 0.50 mm *Controlling di mension is mm. *JEDEC Designation: MS022 Parameters Symbol Min Typ Max Units Package Thermal Resistance multi-layer dual-layer θJA θJA θJC °C/Watt °C/Watt °C/Watt 48L LQFP PACKAGE DRAWING E D1D e L B A

12.ORDERING INFORMATION 13.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order # CS42324 2-In, 4-Out Audio CODEC with 2Vrms Analog I/O LQFP Yes Commercial -40°C to +85° C Tray CS42324-CQZ CS42324 2-In, 4-Out Audio CODEC with 2Vrms Analog I/O LQFP Yes Automotive -40°C to +105° C Tray CS42324-DQZ CDB42324 Evaluation Board - - - - CDB42324 Release Changes A5 Changed Title A6 Corrected SCL/CCLK pin description (Pin 2) in the Pin Description table on page 8. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information t o verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the infor- mation only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD- ING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.