CS4223-BS

CS4223_03 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

/circle6 105 dB Dynamic Range A/D Converters /circle6 105 dB Dynamic Range D/A Converters /circle6 110 dB DAC Signal-to-Noise Ratio (EIAJ) /circle6 Analog Volume Control (CS4224 only) /circle6 Differential Inputs / Outputs /circle6 On-chip Anti-aliasing and Output Smoothing Filters /circle6 De-emphasis for 32, 44.1 and 48 kHz /circle6 Supports Master and Slave Modes /circle6 Single +5 V power supply /circle6 On-Chip Crystal Oscillator /circle6 3-5VD i g i t a lI n t e r f a c e

Description

The CS4223/4 is a highly integrated, high performance, 24-bit, audio codec providing stereo analog-to-digital and stereo digital-to-analog converters using delta-sigma conversion techniques. The device operates from a sin- gle +5 V power supply, and features low power consumption. Selectable de-emphasis filter for 32, 44.1, and 48 kHz sample rates is also included. The CS4224 includes an analog volume control capable of 113.5 dB attenuation in 0.5 dB steps. The analog vol- ume control architecture preserves dynamic range during attenuation. Volume control changes are imple- mented using a “soft” ramping or zero crossing technique. Applications include digital effects processors, DAT, and multitrack recorders.

ORDERING INFORMATION

CS4223-KS -10 to +70 °C 28-pin SSOP CS4223-BS -40 to +85 °C 28-pin SSOP CS4223-DS -40 to +85 °C 28-pin SSOP CS4224-KS -10 to +70 °C 28-pin SSOP CDB4223/4 Evaluation Board I SCL/CCLK SDA/CDIN AD0/CS MCLK VD VA RST LRCK SCLK SDIN SDOUT DGND AGND AOUTL+ AOUTL- AOUTR+ AOUTR- AINL- AINL+ AINR- AINR+ Control Port Serial Audio Data Interface Digital Filters with De-EmphasisDigital Filters Left DAC Right DAC Analog Low Pass and Output Stage Voltage Reference Left ADC Right ADC Volume Control (DIF1)( DIF0)( DEM0) IC / S P I (DEM1) Clock OSC ( ) = CS4223 Volume Control VL XTI XTO * = CS4224 JAN ‘03 DS290F1 CS4223 CS4224

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SWITCHING CHARACTERISTICS - CONTROL PORT - I Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product informa- tion describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe thatthe information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including useof this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in thism a t e r i a l and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Purchase of I 2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those components in a standard I2Cs y s t e m . Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

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1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T A =2 5°C.) SPECIFIED OPERATING CONDITIONS (AGND, DGND = 0 V, all voltages with respect to 0 V.) ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to 0 V.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 2. The maximum over or under voltage is limited by the input current. Parameter Symbol Min Nom Max Unit Power Supplies Digital Analog Digital |V A-V D| VD VA VL 4.75 4.75 2.7 5.0 5.0 5.0 5.25 5.25 5.25 0.4 V V V V Ambient Operating Temperature Commercial (-KS) Industrial (-BS/-DS) T AC TAI -10 -40 Parameter Symbol Min Max Unit Power Supplies Digital Analog VD VA -0.3 -0.3 6.0 6.0 V V Input Current (Note 1) - ±10 mA Analog Input Voltage (Note 2) -0.7 VA + 0.7 V Digital Input Voltage (Note 2) -0.7 VD + 0.7 V Ambient Temperature Power Applied -55 +125 °C Storage Temperature -65 +150 °C

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ANALOG CHARACTERISTICS (Full Scale Input Sine wave, 997 Hz; Fs = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in Figures 4 and 5.) Notes: 3. Referenced to typical full-scale differential input voltage (2 Vrms). 4. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the 0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.625x Fs. 5. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 MHz ±21.8 kHz where n = 0,1,2,3...). 6. Group delay for Fs = 48 kHz, t gd = 18/48 kHz = 375 µs. Parameter Symbol CS4223/4 - KS CS4223/4 - BS/ - DS UnitMin Typ Max Min Typ Max Analog Input Characteristics Total Harmonic Distortion THD - 0.0014 - - 0.0014 - % Dynamic Range A-weighted unweighted 105 102 105 102 dB dB Total Harmonic Distortion + Noise (Note 3) THD+N - -97 -90 - -97 -87 dB Interchannel Isolation (1 kHz) - 90 - - 90 - dB Interchannel Gain Mismatch - - 0.1 - - 0.1 dB Offset Error with High Pass Filter - - 0 - - 0 LSB Gain Drift - 100 - - 100 - ppm/°C Input Resistance 10 - - 10 - - k Ω Input Capacitance - - 15 - - 15 pF Common Mode Input Voltage - 2.3 - - 2.3 - V Common Mode Rejection Ratio CMRR 75 - - 75 - - dB A/D Decimation Filter Characteristics Passband (Note 4) 0 - 21.8 0 - 21.8 kHz Passband Ripple - - ±0.01 - - ±0.01 dB Stopband (Note 4) 30 - 6114 30 - 6114 kHz Stopband Attenuation (Note 5) 80 - - 80 - - dB Group Delay (Fs = Output Sample Rate) Left (Note 6) Right tgd_L tgd_R 18/Fs 17/Fs 18/Fs 17/Fs s s Group Delay Variation vs. Frequency ∆tgd --0--0 µ s High Pass Filter Characteristics Frequency Response -3 dB (Note 4) -0.1 dB 3.7 3.7 Hz Hz Phase Deviation @ 20 Hz (Note 4) - 10 - - 10 - Degree Passband Ripple - - 0 - - 0 dB

ANALOG CHARACTERISTICS (CONTINUED) Notes: 7. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 48 kHz, the 0.01 dB passband edge is 0.4535x Fs and the stopband edge is 0.5465x Fs. 8. Digital filter characteristics. 9. Measurement bandwidth is 10 Hz to 3 Fs. Parameter Symbol CS4223/4 - KS CS4223/4 - BS/ - DS UnitMin Typ Max Min Typ Max Analog Output Characteristics - Minimum Attenuation, 10 k Ω, 100 pF load; unless otherwise specified. Signal-to-Noise, Idle-Channel Noise (CS4224 only) DAC muted, A-weighted 102 110 - 97 110 - dB Dynamic Range DAC not muted, A-weighted DAC not muted, unweighted 100 105 102 105 102 dB dB Total Harmonic Distortion THD - 0.0014 - - 0.0014 - % Total Harmonic Distortion + Noise THD+N - -97 -92 - -97 -87 dB Interchannel Isolation (1 kHz) - 90 - - 90 - dB Interchannel Gain Mismatch - - 0.1 - - 0.1 dB Programmable Output Attenuation Span 110 113.5 - 110 113.5 - dB Differential Offset Voltage - ±10 - - ±10 - mV Common Mode Output Voltage - 2.4 - - 2.4 - V Gain Drift - 100 - - 100 - ppm/° C Out-of-Band Energy Fs/2 to 2 Fs - -60 - - -60 - dBFs Analog Output Load Resistance Capacitance 100 100 kΩ pF Combined Digital and Analog Filter Characteristics Frequency Response10 Hz to 20 kHz - ±0.1 - - ±0.1 - dB Deviation from Linear Phase - ±0.5 - - ±0.5 - Degree Passband: to 0.01 dB corner (Notes 7 and 8) 0 - 21.8 0 - 21.8 kHz Passband Ripple (Note 8) - - ±0.01 - - ±0.01 dB Stopband (Notes 7 and 8) 26.2 - - 26.2 - - kHz Stopband Attenuation (Note 9) 70 - - 70 - - dB Group Delay (Fs = Input Sample Rate) Left Right tgd_L tgd_R 26/Fs 27/Fs 26/Fs 27/Fs s s Power Supply Power Supply Current VA VD VL Total Power Down 0.4 0.4 mA mA mA mA Power Supply Rejection Ratio 1 kHz - 65 - - 65 - dB

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Parameter Symbol Min Max Unit High-level Input Voltage VL = 5V VL = 3V VIH VIH 2.8 2.0 VL + 0.3 VL + 0.3 V V Low-level Input Voltage V IL -0.3 0.8 V High-level Output Voltage at IO =- 2 . 0m A V OH VL - 1.0 - V Low-level Output Voltage at IO =2 . 0m A V OL -0 . 5 V Input Leakage Current Digital Inputs - 10 µA Output Leakage Current High Impedance Digital Outputs - 10 µA

Notes: 10. After powering up the CS4223/4, PDN should be held low for 10 ms to allow the power supply to settle. *SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1. Figure 1. Serial Audio Port Data I/O Timing

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Notes: 11. Not tested but guaranteed by design.

1. t spi only needed before first falling edge of CS after RST rising edge. t spi = 0 at all other times.
2. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 2. SPI Control Port Timing

Notes: 15. Not tested but guaranteed by design.

1. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Figure 3. I 2C Control Port Timing

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1. TYPICAL CONNECTION DIAGRAM — CS4223

27 RST

23 Analog FilterAOUTR+

3 External

Figure 4. CS4223 Recommended Connection Diagram

1. TYPICAL CONNECTION DIAGRAM — CS4224

18 I2C/SPI

11 SCL/CCLK

Figure 5. CS4224 Recommended Connection Diagram

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1. REGISTER QUICK REFERENCE - CS4224 Addr Function 7 6 5 4 3 2 1 0 0h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 0 0 0 0 0 0 0 0 1h ADC Control PDN HPDR HPDL ADMR ADML CAL CALP CLKE default 0 0 0 0 0 0 0 0 2h DAC Control Reserved MUTC MUTR MUTL SOFT Reserved RMP1 RMP0 default 0 0 0 0 0 0 0 0 3h-4h Output Attenuator Level ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 default 0 0 0 0 0 0 0 0 5h DSP Port Mode Reserved DEM1 DEM0 DSCK DOF1 DOF0 DIF1 DIF0 default 0 0 0 0 0 0 0 0 6h Converter Status Report ACCR ACCL LVR2 LVR1 LVR0 LVL2 LVL1 LVL0 default 0 0 0 0 0 0 0 0 7h Master Clock Control Reserved Reserved Reserved Reserved Reserved Reserved MCK1 MCK0 default 0 0 0 0 0 0 0 0

1. REGISTER DESCRIPTIONS - CS4224 Note: All registers are read/write in I 2C mode and write-only in SPI mode, unless otherwise noted.

5.1 ADC Control (address 01h)

5.1.1 POWER DOWN ADC (PDN)

Default = 0 0 - Disabled 1-E n a b l e d Function: The ADC will enter a low-power state when this function is enabled.

5.1.2 LEFT AND RIGHT CHANNEL HIGH PASS FILTER DEFEAT (HPDR-HPDL)

Default = 0 0 - Disabled 1-E n a b l e d Function: The internal high-pass filter is defeated when this function is enabled. Control of the internal high- pass filter is independent for the left and right channel.

5.1.3 LEFT AND RIGHT CHANNEL ADC MUTING (ADMR-ADML)

Default = 0 0 - Disabled 1-E n a b l e d Function: The output for the selected ADC channel will be muted when this function is enabled.

5.1.4 CALIBRATION CONTROL (CAL)

Default = 0 0 - Disabled 1-E n a b l e d Function: The device will automatically perform an offset calibration when brought out of reset, which last ap- proximately 50 ms. When this function is enabled, a rising edge on the reset line will initiate an offset calibration.

5.1.5 CALIBRATION STATUS (CALP) (READ ONLY)

Default = 0 0 - Calibration done 1 - Calibration in progress 76543210 PDN HPDR HPDL ADMR ADML CAL CALP CLKE 00000000

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5.1.6 CLOCKING ERROR (CLKE) (READ ONLY)

Default = 0 0 - No error 1 - Error

5.2 DAC Control (address 02h)

5.2.1 MUTE ON CONSECUTIVE ZEROS (MUTC)

Default = 0 0 - Disabled 1-E n a b l e d Function: The DAC output will mute following the reception of 512 consecutive audio samples of static 0 or -1 when this function is enabled. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The muting function is affected, similar to volume control changes, by the SOFT bit in the DAC Control register.

5.2.2 MUTE CONTROL (MUTR-MUTL)

Default = 0 0 - Disabled 1-E n a b l e d Function: The output for the selected DAC channel will be muted when this function is enabled. The muting function is affected, similar to volume control changes, by the SOFT bit in the DAC Control register.

5.2.3 SOFT RAMP CONTROL (SOFT)

Default = 0 0 - Soft Ramp level changes 1 - Zero Cross level changes Function: Soft Ramp level changes will be implemented by incrementally ramping, in 0.5 dB steps, from the cur- rent level to the new level. The rate of change defaults to 0.5 dB per 8 left/right clock periods and is adjustable through the RMP bits in the DAC Control register. Zero Cross level changes will be implemented in a single step from the current level to the new level. The level change takes effect on a zero crossing to minimize audible artifacts. If the signal does not encounter a zero crossing, the level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 kHz sample rate). Zero crossing is independently monitored and implemented for each channel. The ACCR and ACCL bits in the Converter Status Report register indicate when a level change has occurred for the right and left channel. 76543210 Reserved MUTC MUTR MUTL SOFT Reserved RMP1 RMP0 00000000

5.2.4 SOFT RAMP STEP RATE (RMP)

The rate of change for the Soft Ramp function is adjustable through the RMP bits.

5.3 Left Channel Output Attenuator Level (address 03h)

5.4 Right Channel Output Attenuator Level (address 04h)

5.4.1 ATTENUATION LEVEL (ATT7-ATT0)

attenuation and settings greater than 227 (decimal value) will mute the selected DAC output. Table 1. Example Volume Settings

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5.5 DSP Port Mode (address 05h)

5.5.1 DE-EMPHASIS CONTROL (DEM)

Default = 00 00 - 44.1 kHz de-emphasis setting 01 - 48 kHz de-emphasis setting 10 - 32 kHz de-emphasis setting 11 - De-emphasis disabled Function: Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re- sponse at 32, 44.1 or 48 kHz sample rates, see Figure 15.

5.5.2 SERIAL INPUT/OUTPUT DATA SCLK POLARITY SELECT (DSCK)

Default = 0 0 - Data valid on rising edge of SCLK 1 - Data valid on falling edge of SCLK Function: This function selects the polarity of the SCLK edge used to clock data in and out of the serial audio port.

5.5.3 SERIAL DATA OUTPUT FORMAT (DOF)

Default = 00 00 - I 2S compatible 01 - Left justified 10 - Right justified, 24-bit 11 - Right justified, 20-bit Function: The required relationship between the left/right clock, serial clock and output serial data is defined by the Serial Data Output Format, and the options are detailed in Figures 8-11. Note: If the format selected is Right-Justified, SCLK must be 64 Fs when operating in slave mode.

5.5.4 SERIAL DATA INPUT FORMAT (DIF)

Default = 00 00 - I2S compatible 01 - Left justified 10 - Right justified, 24-bit 11- Right justified, 20-bit Function: The required relationship between the left/right clock, serial clock and input serial data is defined by the Serial Data Input Format, and the options are detailed in Figures 8-11. 76543210 Reserved DEM1 DEM0 DSCK DOF1 DOF0 DIF1 DIF0 00000000

5.6 Converter Status Report (Read Only) (address 06h)

5.6.1 LEFT AND RIGHT CHANNEL ACCEPTANCE BIT (ACCR-ACCL)

Default = 0 0 - Requested setting valid 1 - New setting loaded Function: The ACCR and ACCL bits indicate when a change in the Output Attenuator Level has occurred for the left and right channels, respectively. The value will be high when a new setting is loaded into the Output Attenuator Level registers. The value will return low when the requested attenuation setting has taken effect.

5.6.2 LEFT AND RIGHT CHANNEL ADC OUTPUT LEVEL (LVR AND LVL)

Default = 000 000 - Normal output levels 001 - -6 dB level 010 - -5 dB level 011 - -4 dB level 100 - -3 dB level 101 - -2 dB level 110 - -1 dB level 111 - Clipping Function: The analog-to-digital converter is continually monitoring the peak digital signal output for both the left and right channel, prior to the digital limiter. The maximum output value is stored in the LVL and LVR bits. The LVL and LVR bits are ‘sticky’, so they are reset after each read is performed.

5.7 Master Clock Control (address 07h)

5.7.1 MASTER CLOCK CONTROL (MCK)

Default = 00 00 - XTI = 256 Fs for Master Mode 01 - XTI = 384 Fs for Master Mode 10 - XTI = 512 Fs for Master Mode Function: The MCK bits allow for control of the Master Clock, XTI, input frequency. Note: These bits are not valid when operating in slave mode. 76543210 ACCR ACCL LVR2 LVR1 LVR0 LVL2 LVL2 LVL0 00000000 76543210 Reserved Reserved Reserved Reserved Reserved Reserved MCK1 MCK0 00000000

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1. PIN DESCRIPTIONS — CS4223

20 AINL+

16 AINR-

or 512x Fs in Slave Mode and 256x in Master Mode. options are detailed in Figures 8 - 11. serial data is defined by the DIF1-0 pins. The options are detailed in Figures 8 - 11. VD 6 Digital Power (Input)- Positive power supply for the digital section. Typically 5.0 VDC. DGND 7 Digital Ground (Input)- Digital ground for the digital section. SDOUT 8 Serial Data Output (Output)- Two's complement MSB-first serial data is output on this pin. the DIF1-0 pins. The options are detailed in Figures 8 - 11. Table 2. Common Clock Frequencies

DIF1-0 pins. The options are detailed in Figures 8 - 11. filter. 32, 44.1, or 48 kHz sample rate selection defined in Table 4. coupled into the device, see Figure 12 for optional line input buffer. coupled into the device, see Figure 12 for optional line input buffer. VA 21 Analog Power (Input)- Positive power supply for the analog section. Nominally +5 Volts. AGND 22 Analog Ground (Input)- Analog ground reference. ferential) is specified in the Analog Characteristics specification table. ential) is specified in the Analog Characteristics specification table.

27 Reset (Input) - When low, the device enters a low power mode and all internal registers are

00 I2S, up to 24-bit data 08

Table 3. Digital Interface Format - DIF1 and DIF0 Table 4. De-emphasis Control

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1. PIN DESCRIPTIONS — CS4224

or 512x through the Control Port. (05h) register. The options are detailed in Figures 8 - 11. VD 6 Digital Power (Input)- Positive power supply for the digital section. Typically 5.0 VDC. DGND 7 Digital Ground (Input)- Digital ground for the digital section. Table 5. Common Clock Frequencies

SDOUT 8 Serial Data Output (Output)- Two's complement MSB-first serial data is output on this pin. The required relationship between the le ft/right clock, serial clock and serial data is defined by the DSP Port Mode (05h) register. The options are detailed in Figures 8 - 11. SDIN 9 Serial Data Input (Input)- Two's complement MSB-first serial data is input on this pin. The required relationship between the left/right clock, serial clock and serial data is defined by the DSP Port Mode (05h) register. The options are detailed in Figures 8 - 11. SCL/CCLK 10 Serial Control Port Clock ( Input)- Clocks the serial control bits into and out of the CS4224. In I 2C mode, SCL requires an external pull-up resistor according to the I 2C specification. SDA/CDIN 11 Serial Control Port Data ( Input/Output)- S D Ai sad a t aI / Ol i n ei nI2C mode and requires an external pull-up resistor according to the I 2C specification. CDIN in the input data line for the serial control port in SPI mode. AD0/CS 12 Address Bit/Control Chip Select ( Input)- In I2C mode, AD0 is a chip address bit. In SPI mode, CS is used to enable the control port interface on the CS4224. The CS4224 control port interface is defined by the SPI /I2C pin. VL 13 Logic Power (Input)- Positive power supply for the digital interface section. Typically 3.0 to 5.0 VDC. AINR-, AINR+ 16,17 Differential Right Channel Analog Input ( Input)- The full scale analog input level (differen- tial) is specified in the Analog Characteristics specification table and may be AC coupled or DC coupled into the device, see Figure 12 for optional line input buffer. I2C/SPI

18 Control Port Format (Input) - When this pin is high, I 2C mode is selected, when low, SPI is

selected. AINL-, AINL+ 19,20 Differential Left Channel Analog Input (Input)- The full scale analog input level (differential) is specified in the Analog Characteristics specification table and may be AC coupled or DC coupled into the device, see Figure 12 for optional line input buffer. VA 21 Analog Power (Input)- Positive power supply for the analog section. Typically 5.0 VDC. AGND 22 Analog Ground (Input)- Analog ground reference. AOUTR-, AOUTR+ 23, 24 Differential Right Channel Analog Outputs ( Output)- The full scale analog output level (dif- ferential) is specified in the Analog Characteristics specification table. AOUTL-, AOUTL+ 25, 26 Differential Left Channel Analog Outputs ( Output)- The full scale analog output level (dif- ferential) is specified in the Analog Characteristics specification table. RST reset, including the control port. When high, the control port becomes operational and normal operation will occur.

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1. APPLICATIONS

8.1 Overview

The CS4223 is a stand-alone device controlled through dedicated pins. The CS4224 is controlled with an external microcontroller using the serial control port.

8.2 Grounding and Power Supply

As with any high resolution converter, the CS4223/4 requires careful attention to power sup- ply and grounding arrangements to optimize per- formance. Figures 4 and 5 shows the recommended power arrangement with VA, VD and VL connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but a de- coupling capacitor should still be used on each supply pin.

8.3 High Pass Filter

The operational amplifiers in the input circuitry driv- ing the CS4223/4 may generate a small DC offset into the A/D converter. The CS4223/4 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC lev- el, possibly yielding "clicks" when switching be- tween devices in a multichannel system.

8.4 Analog Outputs

The recommended off-chip analog filter is either a 2nd order Butterworth or a 3rd order Butterworth, if greater out-of-band noise filtering is desired. The CS4223/4 DAC interpolation filter has been pre- compensated for an external 2nd order Butter- w o r t hf i l t e rw i t ha3d Bc o r n e ra tF s ,o ra3 r do r d e r B u t t e r w o r t hf i l t e rw i t ha3d Bc o r n e ra t0 . 7 5F st o provide a flat frequency response and linear phase o v e rt h ep a s s b a n d( s e eF i g u r e1 4f o rF s=4 8k H z ) . If the recommended filter is not used, small fre- quency response magnitude and phase errors will occur. In addition to providing out-of-band noise at- tenuation, the output filters shown in Figure 14 pro- vide differential to single-ended conversion. 8.5 Master vs. Slave Mode The CS4223/4 may be operated in either master mode or slave mode. In master mode, SCLK and LRCK are outputs which are internally derived from MCLK. The device will operate in master mode w h e na4 7kΩ pulldown resistor is present on SD- OUT at startup or after reset, see Figure 5. LRCK a n dS C L Ka r ei n p u t st ot h eC S 4 2 2 3 / 4w h e no p e r - ating in slave mode. See Figures 8-11 for the avail- able clocking modes.

8.6 De-emphasis

The CS4223/4 includes digital de-emphasis for 32, 44.1, or 48 kHz sample rates. The frequency re- sponse of the de-emphasis curve, as shown in Fig- ure 15, will scale proportionally with changes in samples rate, Fs. The de-emphasis feature is in- cluded to accommodate older audio recordings that utilize pre-emphasis as a means of noise re- duction. De-emphasis control is achieved with the DEM1/0 pins on the CS4223 or through the DEM1-0 bits in the DSP Port Mode Byte (#5) on the CS4224.

8.7 Power-up / Reset / Power Down

Upon power up, the user should hold RST =0f o r approximately 10 ms. In this state, the control port is reset to its default settings and the part remains in the power down mode. At the end of RST ,t h e device performs an offset calibration which lasts approximately 50 ms after which the device enters normal operation. In the CS4224, a calibration may also be initiated via the CAL bit in the ADC Control Byte (#1). The CALP bit in the ADC Control Byte is a read only bit indicating the status of the calibra- tion. R e s e t / P o w e rD o w ni sa c h i e v e db yl o w e r i n gt h e RST pin causing the part to enter power down. Once RST goes high, the control port is functional and the desired settings should be loaded. The CS4223/4 will also enter power down mode if the master clock source stops for approximately 10 µs or if the LRCK is not synchronous to the master clock. The control port will retain its current settings. The CS4223/4 will mute the analog outputs and enter the power down mode if the supply drops be- low approximately 4 volts.

8.8 Control Port Interface (CS4224 only)

The control port is used to load all the internal set- tings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference prob- lems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI  and I2C ,w i t h the CS4224 operating as a slave device. The con- trol port interface format is selected by the SPI /I2C pin.

8.8.1 SPI Mode

In SPI mode, CS is the CS4224 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from the microcontroller and the chip ad- dress is 0010000. All signals are inputs and data is clocked in on the rising edge of CCLK. Figure 6 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write in- dicator (R/W ), which must be low to write. Register reading from the CS4224 is not supported in the SPI mode. The next 8 bits form the Memory Ad- dress Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits a r et h ed a t aw h i c hw i l lb ep l a c e di n t oar e g i s t e r designated by the MAP. The CS4224 has a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, then the MAP will stay constant for successive writes. If INCR is set to a 1, then MAP will auto increment after each byte is written, allow- ing block writes of successive registers. Register reading from the CS4224 is not supported in the SPI mode.

8.8.2 I 2CM o d e

In I2C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 7. There is no CS pin. Pin AD0 forms the p a r t i a lc h i pa d d r e s sa n ds h o u l db et i e dt oV Do r DGND as desired. The upper 6 bits of the 7 bit ad- dress field must be 001000. In order to communi- cate with the CS4224, the LSB of the chip address field (first byte sent to the CS4224) should match the setting of the AD0 pin. The eighth bit of the ad- dress byte is the R/W bit (high for a read, low for a write). If the operation is a write, the next byte is the Memory Address Pointer which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the Memory Address Pointer will be output. Setting the auto in- crement bit in MAP, allows successive reads or writes of consecutive registers. Each byte is sepa- rated by an acknowledge bit.

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8.9 Memory Address Pointer (MAP)

8.9.1 AUTO-INCREMENT CONTROL (INCR)

8.9.2 REGISTER POINTER (MAP)

0010000 R/W

Figure 6. Control Port Timing, SPI mode

001000 ADDR

Figure 7. Control Port Timing, I 2Cm o d e

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Figure 11. Serial Audio Format 3 Figure 12. Optional Input Buffer Figure 13. Single-ended Input Application

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Figure 17. ADC Filter Response Figure 18. ADC Passband Ripple Figure 19. ADC Transition Band Figure 20. DAC Filter Response Figure 21. DAC Passband Ripple Figure 22. DAC Transition Band

10.PARAMETER DEFINITIONS Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering So- ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels. ADCs are measured at -1 dBFS as suggested in AES17-1991 Annex A and DACs are measured at 0 dBFS. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the rms analog output level with 1 kHz full scale digital input to the rms analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in deci- bels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and re- ferred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. Units in decibels. Interchannel Isolation A measure of crosstalk between channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in deci- bels. Gain Error The deviation from the nominal full scale output for a full scale input. Gain Drift The change in gain value with temperature. Units in ppm/ °C. Offset Error For the ADCs, the deviation in LSB's of the output from mid-scale with the selected inputs tied to a com- mon potential. For the DAC's, the differential output voltage with mid-scale input code. Units are in volts.

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11.PACKAGE DIMENSIONS Notes: 1. “D”and “E1”are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b”does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b”dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b”by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-150 Controlling Dimension is Millimeters 28L SSOP PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

• Notes