CS4222

CS4222 CIRRUS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 26

Technical content

Features

/c108 99 dB 20-bit A/D Converters /c108 99 dB 20-bit D/A Converters /c108 110 dB DAC Signal-to-Noise Ratio (EIAJ) /c108 Analog Volume Control - 0.5 dB Step Resolution - 113.5 dB Attenuation /c108 Soft Mute Capability /c108 Differential Inputs/Outputs /c108 On-chip Anti-aliasing and Output Smoothing Filters /c108 De-emphasis for 32, 44.1 and 48 kHz /c108 Stand-Alone or Control Port Mode /c108 Single +5 V power supply

Description

The CS4222 is a highly integrated, high performance, 20-bit, audio codec providing stereo analog-to-digital and stereo digital-to-analog converters using delta-sig- ma conversion techniques. The device operates from a single +5 V power supply, and features low power con- sumption. Selectable de-emphasis filter for 32, 44.1, and 48 kHz sample rates is also included. The CS4222 also includes an analog volume control ca- pable of 113.5 dB attenuation in 0.5 dB resolution. The analog volume control architecture preserves dynamic range during attenuation. Volume control changes are implemented using a "soft" ramping or zero crossing technique. Applications include reverb processors, musical instru- ments, DAT, and multitrack recorders. The CS4222 is packaged in a 28-pin plastic SSOP.

ORDERING INFORMATION

CS4222-KS -10° to +70° C 28-pin SSOP CDB4222 Evaluation Board I RST DGND SCL/CCLK DEM1 DEM0 SDA/CDIN AD0/CS AGND SMUTE VD AOUTL+ LRCK SCLK SDIN SDOUT Serial Audio Data Interface Control Port Digital Filters with De-EmphasisDigital Filters Right DAC Left DAC Right ADC Left ADC Volume Control Volume Control Analog Low Pass and Output Stage MCLK VA AOUTL- AOUTR+ AOUTR- AINL- AINL+ AINR- AINR+ JAN ‘97 DS236PP3

ANALOG CHARACTERISTICS ( TA = 25°C; VA, VD = +5V; Full Scale Input Sine wave,

997 Hz; Fs = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in "Recom-

mended Connection Diagram"; SPI mode, Format 0, unless otherwise specified.) Parameter Symbol Min Typ Max Units Analog Input Characteristics ADC Resolution - - 20 Bits Total Harmonic Distortion THD 0.003 - % Dynamic Range (A-weighted): (unweighted): TBD TBD dB dB Total Harmonic Distortion + Noise -1 dB (Note 1) THD+N - -90 TBD dB Interchannel Isolation (1 kHz) - 90 - dB Interchannel Gain Mismatch - 0.1 - dB Offset Error (with High Pass Filter) (HPF defeated with CAL) TBD LSB LSB Full Scale Input Voltage (Differential) 1.9 2.0 2.1 Vrms Gain Drift - 100 - ppm/°C Input Resistance 10 - - kΩ Input Capacitance - - 15 pF Common Mode Input Voltage - 2.3 - V A/D Decimation Filter Characteristics Passband (Note 2) 0 - 21.8 kHz Passband Ripple - - ±0.01 dB Stopband (Note 2) 30 - 6114 kHz Stopband Attenuation (Note 3) 80 - - dB Group Delay (Fs = Output Sample Rate) (Note 4) t gd -1 5 / F s- s Group Delay Variation vs. Frequency Δ tgd --0 µs High Pass Filter Characteristics Frequency Response: -3 dB (Note 2) -0.1 dB 3.7 Hz Hz Phase Deviation @ 20 Hz (Note 2) - 10 - Degree Passband Ripple - - 0 dB Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms) 2. Filter characteristics scale with output sample rate. For output sample rates, Fs, other than 48 kHz, the 0.01 dB passband edge is 0.4535xFs and the stopband edge is 0.625xFs. 3. The analog modulator samples the input at 6.144 MHz for an Fs equal to 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency ( n x 6.144 MHz ±21.8 kHz where n = 0,1,2,3...). 4. Group delay for Fs = 48 kHz, t gd = 15/48 kHz = 312µs * Parameter definitions are given at the end of this data sheet. Specifications are subject to change without notice. CS4222

2 DS236PP3

ANALOG CHARACTERISTICS (Continued) Parameter Symbol Min Typ Max Units Analog Output Characteristics - Minimum Attenuation, 10 kΩ , 100 pF load; unless otherwise specified. DAC Resolution - - 20 Bits Signal-to-Noise, Idle-Channel Noise (DAC muted, A-weighted) TBD 110 - dB Dynamic Range (DAC not muted, A-weighted) (DAC not muted, unweighted) TBD TBD dB dB Total Harmonic Distortion THD - 0.003 - % Total Harmonic Distortion + Noise THD+N - -88 TBD dB Interchannel Isolation (1kHz) - 90 - dB Interchannel Gain Mismatch - 0.1 - dB Attenuation Step Size (All Outputs) 0.35 0.5 0.65 dB Programmable Output Attenuation Span 110 113.5 - dB Differential Offset Voltage - ±10 -m V Common Mode Output Voltage - 2.3 - V Full Scale Output Voltage 1.9 2.0 2.1 Vrms Gain Drift - 100 - ppm/°C Out-of-Band Energy (Fs/2 to 2Fs) - -60 - dBFS Analog Output Load Resistance: Capacitance: 100 kΩ pF Combined Digital and Analog Filter Characteristics Frequency Response 10 Hz to 20 kHz - ±0.1 -d B Deviation from Linear Phase - ±0.5 - Degrees Passband: to 0.01 dB corner (Notes 5,6) 0 - 21.8 kHz Passband Ripple (Note 6) - - ±0.01 dB Stopband (Notes 5,6) 26.2 - - kHz Stopband Attenuation (Notes 7) 70 - - dB Group Delay (Fs = Input Word Rate) t gd -1 6 / F s - s Power Supply Power Supply Current VA VD Total Power Down 0.2 TBD TBD mA mA mA Power Supply Rejection Ratio (1 kHz, 10 mV rms)- 5 0 - d B Notes: 5. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 48 kHz, the 0.01 dB passband edge is 0.4535xFs and the stopband edge is 0.5465xFs. 6. Digital filter characteristics. 7. Measurement bandwidth is 10Hz to 3Fs. Specifications are subject to change without notice CS4222 DS236PP3 3

SWITCHING CHARACTERISTICS (TA = 25°C; VA, VD = +5V ±5%, outputs loaded with 30pF) Parameter Symbol Min Typ Max Units Audio ADC’s & DAC’s Sample Rate Fs 4 - 50 kHz MCLK Frequency (MCLK = 256, 384, or 512 Fs) 1.024 - 26 MHz MCLK Pulse Width High MCLK = 512 Fs MCLK = 384 Fs MCLK = 256 Fs ns ns ns MCLK Pulse Width Low MCLK = 512 Fs MCLK = 384 Fs MCLK = 256 Fs ns ns ns MCLK Jitter Tolerance - 500 - ps RMS RST Low Time (Note 8) 10 - - ms SCLK Falling edge to SDOUT output valid (DSCK=0) t dpd -- 1 (384)Fs + 20 ns LRCK edge to MSB valid t lrpd - - 25 ns SDIN Setup Time Before SCLK Rising Edge (DSCK=0) t ds - - 25 ns SDIN Hold Time After SCLK Rising Edge (DSCK=0) t dh - - 25 ns SCLK Period t sckw 1 (128) Fs -- n s SCLK High Time t sckh 40 - - ns SCLK Low Time t sckl 40 - - ns SCLK Rising to LRCK Edge (DSCK=0) t lrckd 20 - - ns LRCK Edge to SCLK Rising (DSCK=0) t lrcks 40 - - ns Notes: 8. After powering up the CS4222, PDN should be held low for 10 ms to allow the power supply to settle. sckh sckl sckwt tt MSB MSB-1 *SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1. tdpd SDOUT LRCK SCLK* SDIN dhtdstlrpdt lrckstlrckdt Serial Audio Port Data I/O timing CS4222

4 DS236PP3

SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25°C VD, VA = 5V±5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30pF) Parameter Symbol Min Max Units SPI Mode (SPI/I2C = 0) CCLK Clock Frequency f sck -6 M H z RST rising edge to CS falling t srs 500 - ns CCLK edge to CS falling (Note 9) t spi 500 - ns CS High Time Between Transmissions t csh 1.0 - µs CS Falling to CCLK Edge t css 20 - ns CCLK Low Time t scl 66 - ns CCLK High Time t sch 66 - ns CDIN to CCLK Rising Setup Time t dsu 40 - ns CCLK Rising to DATA Hold Time (Note 10) t dh 15 - ns Rise Time of CCLK and CDIN (Note 11) t r2 - 100 ns Fall Time of CCLK and CDIN (Note 11) t f2 - 100 ns Notes: 9. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 10. Data must be held for sufficient time to bridge the transition time of CCLK. 11. For F SCK < 1 MHz tr2 tf2 tdsu tdh tschtscl CS CCLK CDIN tcss tcsh tspi tsrsRST CS4222 DS236PP3 5

SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25°C; VD, VA = 5V±5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30pF) Parameter Symbol Min Max Units I2C ® Mode (SPI/I2C = 1) (Note 12) SCL Clock Frequency f scl - 100 kHz RST Rising Edge to Start t irs 500 - ns Bus Free Time Between Transmissions t buf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low Time t low 4.7 - µs Clock High Time t high 4.0 - µs Setup Time for Repeated Start Condition t sust 4.7 - µs SDA Hold Time from SCL Falling (Note 13) t hdd 0- µs SDA Setup Time to SCL Rising t sud 250 - ns Rise Time of Both SDA and SCL Lines t r -1 µs Fall Time of Both SDA and SCL Lines t f - 300 ns Setup Time for Stop Condition t susp 4.7 µs Notes: 12. Use of the I2C ® bus interface requires a license from Philips. I2C ® is a registered trademark of Philips Semiconductors. 13. Data must be held for sufficient time to bridge the 300ns transition time of SCL. CS4222

6 DS236PP3

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.) Parameter Symbol Min Typ Max Units Power Supplies Digital VD -0.3 - 6.0 V Analog VA -0.3 - 6.0 V Input Current (Note 14) - - ±10 mA Analog Input Voltage (Note 15) -0.7 - VA+0.7 V Digital Input Voltage (Note 15) -0.7 - VD+0.7 V Ambient Temperature (Power Applied) -55 - +125 °C Storage Temperature -65 - +150 °C Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Note: 14. Any pin except supplies. Transient currents of up to ±100mA on the analog input pins will not cause SCR latch-up. 15. The maximum over or under voltage is limited by the input current. RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, all voltages with respect to 0V.) Parameter Symbol Min Typ Max Units Power Supplies Digital VD 4.75 5.0 5.25 V Analog VA 4.75 5.0 5.25 V VA - VD -- 0 . 4 V Operating Ambient Temperature T A -10 25 70 °C DIGITAL CHARACTERISTICS (TA = 25 °C; VA, VD = 5V ± 5%) Parameter Symbol Min Typ Max Units High-level Input Voltage V IH 2.8 - VD+0.3 V Low-level Input Voltage V IL -0.3 - 1.0 V High-level Output Voltage at I0 = -2.0 mA V OH VD-1.0 - - V Low-level Output Voltage at I0 = 2.0 mA V OL -- 0 . 4 V Input Leakage Current (Digital Inputs) - - 10 µA Output Leakage Current (High Impedance Digital Outputs) - - 10 µA CS4222 DS236PP3 7

26 Analog

23 Analog

2 RST

Figure 1. Recommended Connection Diagram

8 DS236PP3

all located in the ADC control byte (#1). Table 2. High Pass Filter Characteristics

0.75 Fs to provide a flat frequency response and

PDDA bit in the DAC control register (#2). Figure 3. Full Scale Input/Output Voltage

10 DS236PP3

the SOFT bit in the DAC bit Control Byte (#2). (10.7 ms to 21.3 ms at 48 kHz sample rate). the SOFT bit in the DAC Control Byte (#2). to the volume control changes. digital filters and the delta-sigma modulator. SCLK and LRCK derived from the master clock. Table 3. Common Clock Frequencies

12 DS236PP3

to the system sample rate, Fs. put format is I2S compatible. static if no operation is required. Figure 8. Control Port Timing, SPI mode

14 DS236PP3

be placed into register designated by the MAP. ity, enabled by the INCR bit in the MAP register. In I2C ® mode, SDA is a bidirectional data line. trademark of Philips Semiconductor.

001000 ADDR

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP. Figure 9. Control Port Timing, I2C ® Mode

control is defined in Table 4.

11 O F F

Table 4. De-Emphasis filter control the status of the calibration. RST pin causing the part to enter power down. tional and the desired settings should be loaded. will retain its current settings. below approximately 4 volts. Figure 10. De-emphasis Curve.

16 DS236PP3

band for the CS4222 ADC’s and DAC’s. Figure 11. Suggested Layout Guideline (See CDB4222 Data Sheet)

Figure 12. ADC Filter Response. Figure 13. ADC Passband Ripple. Figure 14. ADC Transition Band. Figure 15. DAC Frequency Response. Figure 16. DAC Passband Ripple. Figure 17. DAC Transition Band.

18 DS236PP3

Memory Address Pointer (MAP) B7 B6 B5 B4 B3 B2 B1 B0 INCR 0 0 0 0 MAP2 MAP1 MAP0 MAP2-MAP0 Register Pointer INCR Auto Increment Control Bit 0 - No auto increment 1 - Auto increment on This register defaults to 00h. Reserved Byte (0) This byte is reserved for internal use and must be set to 00h for normal operation. This register defaults to 00h. ADC Control Byte (1) B7 B6 B5 B4 B3 B2 B1 B0 PDAD HPDR HPDL ADMR ADML CAL CALP CLKE PDAD Power Down ADC 0 - Normal 1 - Power down HPDR-HPDL High pass filter defeat, right and left 0 - High pass filters active 1 - High pass filters defeated ADMR-ADML ADC Muting, right and left 0 - Normal 1 - Output muted CAL Calibration control bit 0 - Normal operation 1 - Rising edge initiates calibration The following bits are read only: CALP Calibration status 0 - Calibration done 1 - Calibration in progress CLKE Clocking Error 0 - No error 1 - error This register defaults to 00h. DAC Control Byte (2) B7 B6 B5 B4 B3 B2 B1 B0 PDDA MUTC MUTR MUTL SOFT 0 RMP1 RMP0 PDDA Power Down DAC 0 - Normal 1 - Power down MUTC Controls mute on consecutive zeros function 0 - 512 consecutive zeros will mute DAC 1 - DAC output will not mute on zeros. MUTR-MUTL Mute control bits 0 - Normal output level 1 - Selected DAC output muted SOFT Soft Mute Control 0 - Volume control changes, muting and mute-on-zeros occur with "ramp" 1 - Volume control changes, muting and mute-on-zeros occur on zero crossings RMP1-0 Soft Volume 0.5 dB step rate 0 - 1 step per 8 LRCK’s 1 - 1 step per 4 LRCK’s 2 - 1 step per 16 LRCK’s 3 - 1 step per 32 LRCK’s This register defaults to 00h. CS4222 DS236PP3 19

Output Attenuator Data Byte (3, 4) B7 B6 B5 B4 B3 B2 B1 B0 ATT7 ATT6 A TT5 ATT4 ATT3 ATT2 ATT1 ATT0 A TT7-A TT0 Sets attenuator level 0 - No attenuation 227 - 113.5 dB attenuation >227 - DAC muted ATT0 represents 0.5 dB of attenuation This register defaults to 00h. DSP Port Mode Byte (5) B7 B6 B5 B4 B3 B2 B1 B0 DEM2 DEM1 DEM0 DSCK DDO DDF2 DDF1 DDF0 DEM2-0 Selects de-emphasis control source 0 - De-emphasis controlled by pins 1 - 44.1 kHz de-emphasis setting 2 - 48 kHz de-emphasis setting 3 - 32 kHz de-emphasis setting 4 - De-emphasis disabled 5 - Not used 6 - Not used 7 - Not used DSCK Set the polarity of clocking data 0 - Data valid on rising edge of SCLK 1 - Data valid on falling edge of SCLK DDO Data output format 0 - I 2S compatible 1 - Left justified DDI2-DDI0 Data input format 0 - I2S compatible 1 - Left justified 2 - Right justified, 20-bit 3 - Right justified, 18-bit 4 - Right justified, 16-bit 5 - Not used 6 - Not used 7 - Not used This register defaults to 00h. Converter Status Report Byte (Read Only) (6) B7 B6 B5 B4 B3 B2 B1 B0 ACCR ACCL LVR2 L VR1 L VR0 L VL2 L VL2 L VL0 ACCR-ACCL Acceptance bit 0 - ATT7-0 has been accepted 1 - New setting waiting for zero crossing LVL2-0,L VR2-0 Left and Right ADC output level 0 - Normal output levels 1 - -6 dB level 2 - -5 dB level 3 - -4 dB level 4 - -3 dB level 5 - -2 dB level 6 - -1 dB level 7 - Clipping LVL2-0 and LVR2-0 bits are ’sticky’. They constantly monitor the ADC output for the peak levels and hold the maximum output. They are reset to 0 when read. This register is read only. CS4222

20 DS236PP3

V A - Positive Analog Power, Pin 21. Positive analog supply. Nominally +5 volts. VD - Positive Digital Power, Pin 6. Positive supply for the digital section. Nominally +5 volts. AGND - Analog Ground, Pin 22. Analog ground reference. DGND - Digital Ground, Pin 7. Digital ground for the digital section. Analog Inputs AINR-, AINR+ - Differential Right Channel Analog Input, Pins 16 and 17. Analog input connections of the right channel differential inputs. Typically 2 Vrms differential (1 Vrms for each input pin) for a full-scale analog input signal. AINL-, AINL+ - Differential Left Channel Analog Input, Pins 19 and 20. Analog input connections of the left channel differential inputs. Typically 2 Vrms differential (1 Vrms for each input pin) for a full-scale analog input signal. NC NC SMUTE RST MCLK AOUTL- LRCK AOUTL+ SCLK AOUTR+ VD AOUTR- DGND AGND SDOUT VA SDIN AINL+ SCL/CCLK AINL- SDA/CDIN DEM1 AD0/CS AINR+ DEM0 AINR- NC NC CS4222 DS236PP3 21

AOUTR-, AOUTR+ - Differential Right Channel Analog Outputs, Pins 23 and 24. Analog output connections for the Right channel differential outputs. Nominally 2 Vrms (differential) for full-scale digital input signal. AOUTL-, AOUTL+ - Differential Left Channel Analog Outputs, Pins 25 and 26. Analog output connections for the Left channel differential outputs. Nominally 2 Vrms (differential) for full-scale digital input signal. Digital Inputs MCLK - Master Clock, Pin 3. Clock source for the delta-sigma modulator sampling and digital filters. The frequency of this clock must be either 256x, 384x, or 512x Fs. LRCK - Left/Right Clock, Pin 4. LRCK determines which channel, left or right, is to be input/output on SDIN/SDOUT. Although the outputs for each ADC channel are transmitted at different times, Left/Right pairs represent simultaneously sampled analog inputs. LRCK is an input clock whose frequency must be equal to Fs. SCLK - Serial Data Clock, Pin 5. Clocks the individual bits of the serial data out from SDOUT and in from SDIN. SDIN - Serial Data Input, Pin 9. Two’s complement MSB-first serial data of either 16, 18, or 20 bits is input on this pin. The data is clocked into the CS4222 via the SCLK clock and the channel is determined by the LRCK clock. The default interface format on power-up is an I 2S compatible 20-bit interface. This may be changed by writing the control port (DSP Port Mode Byte #5). DEM1, DEM0 - De-Emphasis Select, Pins 18 and 13. Controls the activation of the standard 50/15 µs de-emphasis filter. 32, 44.1, or 48 kHz sample rate selection defined in Table 4. SMUTE - Soft Mute, Pin 2. SMUTE low activates a muting function for both the left and right channel D/A converter outputs. Soft muting is achieved by ramping down the volume in 0.5 dB steps until achieving mute if SOFT bit (DAC Control Byte #2) is set to 0 (default). Digital Outputs SDOUT - Serial Data Output, Pin 8. Two’s complement MSB-first serial data of 20 bits is output on this pin. The data is clocked out via the SCLK clock and the channel is determined by LRCK. CS4222

22 DS236PP3

SCL/CCLK - Serial Control Interface Clock, Pin 10. SCL/CCLK is the serial control interface clock and is used to clock control bits into and out of the CS4222 This pin should be tied to DGND in stand-alone mode. AD0/ CS - Address Bit/Control Port Chip Select, Pin 12. In I2C® mode, AD0 is a chip address bit. In SPI mode, CS is used to enable the control port interface on the CS4222. The CS4222 will enter SPI mode if a negative transition is ever seen on this pin after power up. This pin should be tied to DGND in stand-alone mode. SDA/CDIN - Serial Control Data In, Pin 11. SDA/CDIN is the input data line for the control port interface. This pin should be tied to DGND in stand-alone mode. Miscellaneous Pins RST - Reset, Pin 27. When low, the CS4222 enters a low power mode and all internal states are reset, including the control port. When high, the control port becomes operational and normal operation will occur. NC - No Connect, Pins 1, 14, 15 and 28 These pins are not connected internally and should be tied to DGND to minimize noise coupling. PARAMETER DEFINITIONS Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60dBFS signal. 60dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 20Hz to 20kHz), including distortion components. Expressed in decibels. ADCs are measured at -1 dBFS as suggested in AES17-1991 Annex A and DACs are measured at 0 dBFS. CS4222 DS236PP3 23

Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the rms analog output level with 1kHz full scale digital input to the rms analog output level with all zeros into the digital input. Measured A-weighted over a 10Hz to 20kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. Units in decibels. Interchannel Isolation A measure of crosstalk between channels. Measured for each channel at the converter’s output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 20Hz to 20kHz relative to the amplitude response at 1kHz. Units in decibels. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in decibels. Gain Error The deviation from the nominal full scale output for a full scale input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSB’s of the output from mid-scale with the selected inputs tied to a common potential. For the DAC’s, the differential output voltage with mid-scale input code. Units are in volts. CS4222

24 DS236PP3

E A A D E A SID E VIEW EN D VIEW TO P VIEW Seating Plane N otes: 1. "D" and "E " are reference datums and do not include mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20mm per side. 2. Dimension b does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13mm total in excess of b dimension at maximum material condition. Dambar intrusion shall not reduce dimension b by more than 0.07mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25mm from lead tips. N 132 Dimensions N MILLIMETERS MIN NOM MAX 6.90 7.20 7.50 9.90 10.20 10.50 Note DIM MILLIMETERS MIN NOM MAX A A A b D E e E L N -- 2.13 0.05 0.15 0.25 1.62 1.75 1.88 0.22 0.30 0.38 see other table 5.00 5.30 5.60 7.40 7.80 8.20 0.63 0.90 1.03 see other table 0° 4° 8° Note 2, 3 e b 2 0.61 0.65 0.69 L INCHES MIN NOM MAX - - 0.084 0.002 0.006 0.010 0.064 0.070 0.074 0.009 0.012 0.015 see other table 0.197 0.209 0.220 0.291 0.307 0.323 0.025 0.035 0.040 see other table 0°4 ° 8 ° 0.024 0.026 0.027 D INCHES MIN NOM MAX 0.272 0.283 0.295 0.390 0.402 0.413 CS4222 DS236PP3 25