CS4215-KL

CS4215 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

• Sample Frequencies from 4 kHz to 50 kHz
• 16-bit Linear, 8-bit Linear, µ-Law, or A-Law Audio Data Coding
• Programmable Gain for Analog Inputs
• Programmable Attenuation for Analog Outputs
• On-chip Oscillators
• +5V Power Supply
• Microphone and Line Level Analog Inputs
• Headphone, Speaker, and Line Outputs
• On-chip Anti-Aliasing/Smoothing Filters
• Serial Digital Interface General Description The CS4215 is a single-chip, stereo, CMOS multime- dia codec that supports CD-quality music, FM radio-quality music, telephone-quality speech, and modems. The analog-to-digital and digital-to-analog converters are 64×oversampled delta-sigma converters with on-chip filters which adapt to the sample fre- quency selected. The +5V only power requirement makes the CS4215 ideal for use in workstations and personal computers. Integration of microphone and line level inputs, input and output gain setting, along with headphone and monitor speaker driver, results in a very small footprint. Ordering Information: CS4215-KL 0 °C to 70°C 44-pin PLCC CS4215-KQ 0 °C to 70°C 100-pin TQFP CDB4215 Evaluation Board 16-Bit Multimedia Audio Codec Semiconductor Corporation CS4215 LINL LINR MINL MINR M U X SDIN Gain 8XTL1IN XTL1OUT XTL2IN XTL2OUT CMOUT CLKIN CLKOUT Clock Generator PIO0 PIO1 PDN VA1 VA2 VD1 VD2 AGND1 AGND2 DGND1 DGND2 Control Interface and Registers A/D A/D RESET D/C Serial Input/Output SDOUT SCLK FSYNC TSOUT TSIN MOUT1 VREF LOUTR LOUTL MOUT2 Attenuator Output D/A D/A Voltage Reference HEADL HEADR HEADCMute Monitor Attenuator µ -law A-law encode unsigned µ -law A-law decode unsigned SEPT ’93 DS76F2 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 Copyright  Crystal Semiconductor Corporation 1993 (All Rights Reserved) This data sheet was written for Revision E CS4215 codecs and later. For differences between Revision E and previous versions, see Appendix A. The CS4215 is an MwaveTM audio codec.

ANALOG CHARACTERISTICS ( TA = 25°C; VA1, VA2, VD1, VD2 = +5V; Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2; Full Scale Input Sine wave, No Gain, No Attenuation 1 kHz; Conversion Rate = 48 kHz; No Gain, No Attenuation, SCLK = 3.072 MHz; Measurement Bandwidth is 10 Hz to 20 kHz; Slave mode; Unless otherwise specified.) Parameter * Symbol Min Typ Max Units Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified. ADC Resolution 16 - - Bits ADC Differential Nonlinearity - - ±0.9 LSB Instantaneous Dynamic Range Line Inputs IDR 80 84 - dB Mic Inputs 72 78 - dB Total Harmonic Distortion Line Inputs THD - - 0.012 % Mic Inputs - - 0.032 % Interchannel Isolation Line to Line Inputs - 80 - dB Line to Mic Inputs - 60 - dB Interchannel Gain Mismatch Line Inputs - - 0.5 dB Mic Inputs - - 0.5 dB Frequency Response (Note 1) (0 to 0.45 Fs) -0.5 - +0.2 dB Programmable Input Gain Line Inputs -0.2 - 23.5 dB Mic Inputs 19.8 - 44 dB Gain Step Size - 1.5 - dB Absolute Gain Step Error - - 0.75 dB Offset Error Line Inputs (AC Coupled) - ±150 ±400 with HPF = 0 Line Inputs (DC Coupled) - ±10 ±150 LSB (No Gain) Mic Inputs - ±400 - Offset Error Line Inputs (AC Coupled) - 0 ±5 with HPF = 1 (Notes 1,2) Line Inputs (DC Coupled) - 0 ±5L S B (No Gain) Mic Inputs - 0 ±5 Full Scale Input Voltage: (MLB=0) Mic Inputs 0.250 0.28 0.310 Vpp (MLB=1) Mic Inputs 2.50 2.8 3.10 V pp Line Inputs 2.50 2.8 3.10 V pp Gain Drift - 100 - ppm/ °C Input Resistance (Note 3) 20 - - k Ω Input Capacitance - - 15 pF CMOUT Output Voltage (Note 4) 1.9 2.1 2.3 V (Maximum output current = 400 µA) Specifications are subject to change without notice. * Parameter definitions are given at the end of this data sheet. Mwave  is a trademark of the IBM Corporation. Notes: 1. This specification is guaranteed by characterization, not production testing. 2. Very low frequency signals will be slightly distorted when using the HPF. 3. Input resistance is for the input selected. Non-selected inputs have a very high (>1MΩ ) input resistance. 4. DC current only. If dynamic loading exists, then CMOUT must be buffered or the performance of ADC’s and DAC’s may be degraded. CS4215

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ANALOG CHARACTERISTICS (Continued) Parameter * Symbol Min Typ Max Units Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified. DAC Resolution 16 - - Bits DAC Differential Nonlinearity - - ±0.9 LSB Total Dynamic Range TDR - 95 - dB Instantaneous Dynamic Range (OLB = 1) (All Outputs) IDR 80 85 - dB Total Harmonic Distortion Line Out (Note 5) - - 0.025 % (OLB = 1) Headphone Out (Note 6) THD - - 0.2 % Speaker Out (Note 6) - - 0.32 % Interchannel Isolation Line Out (Note 5) - 80 - dB Headphone Out (Note 6) - 40 - dB Interchannel Gain Mismatch Line Out - - 0.5 dB Headphone - - 0.5 dB Frequency Response (Note 1) (0 to 0.45 Fs) -0.5 - +0.2 dB Programmable Attenuation (All Outputs) 0.2 - -94.7 dB Attenuation Step Size - 1.5 - dB Absolute Attenuation Step Error - - 0.75 dB Offset Voltage Line Out - 10 - mV Full Scale Output Voltage Line Output (Note 5) 2.55 2.8 3.08 V pp with OLB = 0 Headphone Output (Note 6) 3.6 4.0 4.4 V pp Speaker Output-Differential (Note 6) 7.3 8.0 8.8 V pp Full Scale Output Voltage Line Output (Note 5) 1.8 2.0 2.2 V pp with OLB = 1 Headphone Output (Note 6) 1.8 2.0 2.2 V pp Speaker Output-Differential (Note 6) 3.6 4.0 4.4 V pp Gain Drift - 100 - ppm/ °C Deviation from Linear Phase - - 1 Degree Out of Band Energy (22 kHz to 100 kHz) Line Out - -60 - dB Power Supply Power Supply Current (Note 7) Operating - 110 140 mA Power Down - 0.5 2 mA Power Supply Rejection (1 kHz) - 40 - dB Notes: 5. 10 kΩ , 100 pF load. Headphone and Speaker outputs disabled. 6. 48 Ω , 100 pF load. For the headphone outputs, THD with 10kΩ , 100pF load is 0.02%. 7. Typically, 50% of the power supply current is supplied to the analog power pins (VA1, VA2) and 50% is supplied to the digital power pins (VD1, VD2). Values given are for unloaded outputs. CS4215 DS76F2 3

DIGITAL CHARACTERISTICS (TA = 25°C; VA1, VA2, VD1, VD2 = 5V) Parameter Symbol Min Max Units High-level Input Voltage V IH (VD1,VD2)-1.0 (VD1,VD2)+0.3 V Low-level Input Voltage V IL -0.3 1.0 V High-level Output Voltage at I0 = -2.0 mA V OH (VD1,VD2)-0.2 - V Low-level Output Voltage at I0 = 2.0 mA V OL -0 . 1 V Input Leakage Current (Digital Inputs) - 10 µA Output Leakage Current (High-Z Digital Outputs) - 10 µA D/A Interpolation Filter Characteristics Parameter Symbol Min Typ Max Units Passband (Fs is conversion freq.) 0 - 0.45Fs Hz Frequency Response -0.5 - +0.2 dB Passband Ripple - - ±0.1 dB Transition Band 0.45Fs - 0.55Fs Hz Stop Band ≥ 0.55Fs - - Hz Stop Band Rejection 74 - - dB Group Delay - 16/Fs - s Group Delay Variation vs. Frequency - - 0.1/Fs s A/D Decimation Filter Characteristics Parameter Symbol Min Typ Max Units Passband (Fs is conversion freq.) 0 - 0.45Fs Hz Frequency Response -0.5 - +0.2 dB Passband Ripple - - ±0.1 dB Transition Band 0.45Fs - 0.55Fs Hz Stop Band ≥ 0.55Fs - - Hz Stop Band Rejection 74 - - dB Group Delay - 16/Fs - s Group Delay Variation vs. Frequency - - 0.0 µs CS4215

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TS 1, Bit 7 TS 1, Bit 7 TS 1, Bit 6 SCLK t pd1 t pd1 t pd2TSOUT t pd2 TS 8, Bit 0TS 1, Bit 6 FSYNC out TSIN FSYNC in t s1 t h1 t h1t s1 TS 8, Bit 0 tsckltsckh t sckw SWITCHING CHARACTERISTICS (TA = 25°C; VA1, VA2, VD1, VD2 = +5V, outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2) Parameter Symbol Min Typ Max Units SCLK period Master Mode, XCLK = 1 (Note 8) t sckw -1 / ( F s*bpf) - s Slave Mode (XCLK = 0) tsckw 80 - - ns SCLK high time Slave Mode, XCLK = 0 (Note 9) tsckh 25 - - ns SCLK low time Slave Mode, XCLK = 0 (Note 9) tsckl 25 - - ns Input Setup Time t s1 15 - - ns Input Hold Time t h1 10 - - ns Input Transition Time 10% to 90% points - - 10 ns Output delay tpd1 - - 28 ns SCLK to TSOUT tpd2 - - 30 ns Output to Hi-Z state Timeslot 8, bit 0 t hz - - 12 ns Output to non-Hi-Z Timeslot 1, bit 7 t nz 15 - - ns Input Clock Frequency Crystals - - 27 MHz CLKIN (Note 10) 1.024 - 13.5 MHz Input Clock (CLKIN) low time 30 - - ns Input Clock (CLKIN) high time 30 - - ns Sample rate Fs 4 - 50 kHz RESET low time (Note 11) 500 - - ns Notes: 8. In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf), the SCLK duty cycle is 50%. When BSEL1,0 is set to 256 bpf, SCLK will have the same duty cycle as CLKOUT. See Internal Clock Generation section. 9. In Slave mode, FSYNC and SCLK must be derived from the master clock running the codec (CLKIN, XTAL1, XTAL2). 10. Sample rate specifications must not be exceeded. 11. After powering up the CS4215, RESET should be held low for 50 ms to allow the voltage reference to settle. CS4215 DS76F2 5

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.) Parameter Symbol Min Max Units Power Supplies: Digital VD1,VD2 -0.3 6.0 V Analog VA1,VA2 -0.3 6.0 V Input Current (Except Supply Pins) - ±10.0 mA Analog Input Voltage -0.3 (VA1, VA2)+0.3 V Digital Input Voltage -0.3 (VD1, VD2)+0.3 V Ambient Temperature (Power Applied) -55 +125 °C Storage Temperature -65 +150 °C Warning: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, all voltages with re- spect to 0V.) Parameter Symbol Min Typ Max Units Power Supplies: Digital (Note 8) VD1,VD2 4.75 5.0 5.25 V Analog (Note 8) VA1,VA2 4.75 5.0 5.25 V Operating Ambient Temperature T A 02 5 7 0 °C Note: 8. VD - VA must be less than 0.5 Volts (one diode drop). CS4215

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Note: AGND and DGND pins must be on the same ground plane.

16.9344 MHz

24.576 MHz

pins should be left floating. Figure 1. Recommended Connection Diagram

direct headphone drive and mono speaker drive. cated to the device over a serial interface. cause slight distortions at very low frequencies. LINL and LINR are the line level input pins. Figure 3. AC Coupled Input. Figure 2. DC Coupled Input.

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will be amplified by the codec. ter 511 frames (10.6 ms at a 48 kHz frame rate).

7 R57

Figure 4. Optional Microphone Input Buffer

headphone outputs and a mono monitor speaker output. Output Level Attenuator The DAC outputs are routed through an attenu- ator, which provides 0 dB to 94.5 dB of attenuation, adjustable in 1.5 dB steps. Level changes are implemented using both analog and digital attenuation techniques. Level changes only take effect on zero crossings to minimize audible artifacts. The requested level change is forced if an analog zero crossing does not occur within 511 frames (10.6 ms at a 48 kHz frame rate). A separate zero crossing detector exists for each channel. Line Outputs LOUTR and LOUTL output an analog signal, centered around the CMOUT voltage. The mini- mum recommended load impedance is 8 k Ω . Figure 1 shows the recommended 1.0 µF DC blocking capacitor with a 40 kΩ resistor to ground. When driving impedances greater than 10 k Ω , this provides a high pass corner of 20 Hz. These outputs may be muted. Headphone Outputs HEADR and HEADL output an analog signal, centered around the HEADC voltage. The de- fault headphone output level (OLB = 0) contains an optional 3 dB gain over the line outputs which provides reasonable listening levels, even with small amplitude digital sources. These out- puts have increased current drive capability and can drive a load impedance as low as 48 Ω . Ex- ternal 12 Ω series resistors reduce output level variations with different impedance headphones. The common return line from driving head- phones should be connected to HEADC, which is biased to the CMOUT voltage. This removes the need for AC coupling, and also controls where the return currents flow. All three head- phone output lines are short-circuit protected. These outputs may be muted. Speaker Output MOUT1 and MOUT2 differentially drive a small loudspeaker, whose impedance should be greater than 32 Ω . The signal is a summed version of the right and left line output, tapped off prior to the mute function, but after the attenuator. The speaker output may be independently muted. With OLB = 0, the speaker output also contains a 3 dB gain over the line outputs. When OLB = 1, the speaker outputs are driven at the same level as the line outputs. Some small speakers distort heavily when pre- sented with low frequency energy. A high-pass filter helps eliminate the low frequency energy and can be implemented by AC coupling both speaker terminals with a resistor to ground, on the speaker side of the DC blocking capacitors. The values selected would depend on the speaker chosen, but typical values would be 22 µF for the capacitors, with the positive side connected to the codec, and 50 kΩ resistors. This circuit is contained on the CDB4215 evaluation board as shown in the end of this data sheet. Input Monitor Function To allow monitoring of the input audio signal, the output of the ADCs can be routed through a monitor path attenuator, then digitally mixed into the input data for the DACs (see the front page block diagram). Changes in the input gain or output level settings directly affect the monitor level. If full scale data from the ADCs is added to full scale digital data from the serial interface, clipping will occur. Calibration Both output offset voltage and input offset error are minimized by an internal calibration cycle. At least one calibration cycle must be invoked CS4215

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to settle, before initiating a calibration cycle. selected (microphone or line, using the IS bit).

194 FSYNC cycles and SDOUT data bits will be

Two pins are provided for parallel input/output.

1. CONTROL MODE READ - The PIO pins are sampled by a rising edge of SCLK.
2. DATA MODE READ, WRITE - are tied to the rising edge of FSYNC and CLKOUT.

They are independent of SCLK.

1. CONTROL MODE READ - The data is sent out, via SDOUT, the same frame.
2. DATA MODE READ - The data is sent out via SDOUT on the next frame.

1 SCLK

8.5 CLKOUT's

11 CLKOUT's

Figure 5. PIO Pin Timing

to the selected master clock. ing (equivalent to a 40 pF capacitor on each leg). Crystal, telephone number (714) 991-1580. then CLKOUT has the timing shown in Figure 6. ceiver, or an already existing system clock. ratios off the CLKIN frequency. Figure 6. CLKOUT duty cycle using the on-chip

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case, it must be 256 times Fs. of the ‘CHI’ bus from A T&T/Intel. SCLK frequency is always equal to the bit rate.

2 SCLKs before the start of a new frame (see

or 4 CS4215s connected to the same bus. Figure 7. Multiple CS4215’s

Figure 8. Serial Interface Timing for 2 CS4215’s Figure 9. Frame Sync and Bit Offset Timing Figure 10. Control Mode Timing for 2 CS4215’s

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bits) to communicate all data (see Figure 9). equal to the register number (see Figure 10).

1 Status

2 Data Format

3 Serial Port Control

5 Parallel Port

6 RESERVED

7 Revision

8 RESERVED

Table 1. Control Registers

may drive them low even when they have been programmed as highs. Therefore, the value read back may differ from the value written. In the data mode, (D/C=1), this register can be read and written to through the serial port as part of the Input Settings Registers. In control mode, (D/C=0) these bits can only be read. CS4215

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Read back and verify control information. not a run-time conditional branch. ignore any further bus activity. Figure 11. Control Mode Flow Chart

RSRV Reserved Bits Must be written as 0. CLB Control Latch Bit 1 R Ensures proper transition between control and data mode. OLB Output Level Bit 0 R Line full scale outputs are 2.8 Vpp (1Vrms) Headphone full scale output is 4.0 Vpp. Speaker full scale output is 8.0 Vpp. Line and Headphone full scale outputs are 2.0 Vpp. Speaker full scale output is 4.0 Vpp. MLB Microphone Level 0 R 20 dB Fixed Gain Enabled Full scale microphone inputs are 0.288 Vpp. 20 dB Fixed Gain Disabled Full scale inputs are 2.88 Vpp. Control Time Slot 1, Status Register D7 D6 D5 D4 D3 D2 D1 D0

001 M L B O L B C L BR S R V

Reset (R) Control Time Slot 2, Data Format Register D7 D6 D5 D4 D3 D2 D1 D0 HPF RSRV DFR2 DFR1 DFR0 ST DF1 DF0 0X000001 Register Reset (R) BIT NAME VALUE FUNCTION DF1-0 Data Format Selection 0 0 0 1 1 0 1 1 R 16-bit 2 ’s-complement linear. 8-bit µ−Law. 8-bit A-Law. 8-bit unsigned linear. ST Stereo Bit 0 R Mono Mode. Stereo Mode. DFR2-0 Data Conversion Frequency Selection 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R XT AL1(kHz) XT AL2 (kHz) CLKIN (÷) 24.576 MHz 16.9344 MHz 3072 8 5.5125 1536 16 11.025 896 27.42857 18.9 768 32 22.05 448 NA 37.8 384 NA 44.1 512 48 33.075 2560 9.6 6.615 RSRV Reserved Bit Must be written as 0 HPF High Pass Filter 0 R Disabled. Enabled. A Digital High Pass Filter is used to force the ADC DC offset to zero. CS4215

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Enable the serial data output. Disable (high-impedance state) serial data output. XCLK T ransmit Clock 0 R Receive SCLK and FSYNC from external source SLAVE Mode Generate SCLK and FSYNC MASTER Mode BSEL1-0 Select Bit Rate 0 0 0 1 1 0 1 1 R 64 bits per frame. 128 bits per frame. 256 bits per frame. Reserved. MCK2-0 Clock Source Select 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 R SCLK is master clock, 256 bits per frame. BSEL must equal 2, and XCLK must equal 0. XT AL1, 24.576 MHz, is clock source. XT AL2, 16.9344 MHz, is clock source. CLKIN is clock source, and must be 256xFs. CLKIN is clock source, DFR2-0 select sample frequency. ITS Immediate Three- State R SCLK and FSYNC three-state up to 12 clocks after D/C goes low. SCLK and FSYNC three-state immediately after D/C goes low. Control Time Slot 3, Serial Port Control Register D7 D6 D5 D4 D3 D2 D1 D0 ITS MCK2 MCK1 MCK0 BSEL1 BSEL0 XCLK XEN 00001001 Register Reset (R) Control Time Slot 4, Test Register D7 D6 D5 D4 D3 D2 D1 D0 TEST ENL DAD 00000000 Register Reset (R) BIT NAME VALUE FUNCTION DAD Loopback Mode 0 R Digital-Digital Loopback. Digital-Analog-Digital Loopback. ENL Enable Loopback Te s t i n g R Disable. Enable. TEST T est bits The TEST bits must be written as zero, otherwise special factory test modes may be invoked. CS4215 DS76F2 19

Control Time Slot 5, Parallel Port Register D7 D6 D5 D4 D3 D2 D1 D0 PIO1 PIO0 RSRV 11XXXXXX Register Reset (R) BIT NAME VALUE FUNCTION RSRV Reserved Bits Must be written as 0. PIO1-0 Parallel I/O Bits 1 1 3 R See the Parallel Input/Output Section. Control Time Slot 6, Reserved Register D7 D6 D5 D4 D3 D2 D1 D0 RSRV XXXXXXXX Register Reset (R) Control Time Slot 7, Version Register D7 D6 D5 D4 D3 D2 D1 D0 RSRV VER3 VER2 VER1 VER0 XXXX0010 Register Reset (R) BIT NAME VALUE FUNCTION VER3-0 Device Version Number 0 0 0 0 0 0 0 1 0 0 1 0 R "C". See Appendix A. "D". See Appendix A. "E". This Data Sheet RSRV Reserved Bits Must be written as 0. BIT NAME VALUE FUNCTION RSRV Reserved Bits Must be written as 0. Control Time Slot 8, Reserved Register D7 D6 D5 D4 D3 D2 D1 D0 RSRV XXXXXXXX Register Reset (R) BIT NAME VALUE FUNCTION RSRV Reserved Bits Must be written as 0. CS4215

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signal levels and A-Law is equivalent to 12 bits. both µ-Law and A-Law, is equivalent to 6 bits. upper 13 (12) bits to 8 bits for the ADCs. time slot 1 is used for the data. tions for the 4 data modes and for control mode. 1 1 1 1 1 1 63 R 1.5dB attenuation steps. LO5 is the MSB. R Analog line outputs off (muted). R Headphone output off (muted). Figure 14. Companded Data Formats

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Data Time Slot 8, Input Setting D7 D6 D5 D4 D3 D2 D1 D0 MA3 MA2 MA1 MA0 RG3 RG2 RG1 RG0 11110000 Register Reset (R) BIT NAME VALUE FUNCTION RG3-0 Right Channel Input Gain Setting 0 0 0 0 R 1.5dB gain steps. RG3 is the MSB. 0 = no gain, 1111 = 22.5dB gain. MA3-0 Monitor Path Attenuation 1 1 1 1 15 R 6dB attenuation steps. MA3 is the MSB. 0 = no attenuation, 1111 = mute. BIT NAME VALUE FUNCTION LG3-0 Left Channel Input Gain Setting 0 0 0 0 R 1.5dB gain steps. LG3 is the MSB. 0 = no gain, 1111 = 22.5dB gain. IS Input Select 0 R Line level inputs (LINL, LINR). Microphone level inputs (MINL, MINR). OVR Overrange 0 R When read as 1, this bit indicates that an input over- range condition has occurred. The bit remains set until cleared by writing 0 into the register. Writing a 1 enables the overrange detection. The bit will remain 0 until an over-range occurs. Serial port clear has priority over internal settings. PIO1-0 Parallel I/O 1 1 3 R Parallel input/output bits. Data Time Slot 7, Input Setting D7 D6 D5 D4 D3 D2 D1 D0 PIO1 PIO0 OVR IS LG3 LG2 LG1 LG0 11000000 Register Reset (R) Data Time Slot 6, Output Setting D7 D6 D5 D4 D3 D2 D1 D0 ADI SE RO5 RO4 RO3 RO2 RO1 RO0 10111111 Register Reset (R) BIT NAME VALUE FUNCTION RO5-0 Right Channel Output Attenuation Setting 1 1 1 1 1 1 63 R 1.5dB attenuation steps. RO5 is the MSB. 0 = no attenuation. 111111 = -94.5dB Not used in mono modes. SE Speaker Enable 0 R Speaker off (muted). Speaker on. ADI A/D Data Invalid 0 R A/D data valid. A/D data invalid. Busy in calibration. CS4215 DS76F2 23

16 Bit Stereo

16 Bit Mono

8 Bit Stereo

8 Bit Mono

Figure 1 5. Time Slot/Register Overview CS4215

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internal voltage reference time to settle. Figure 16. DD, DAD & ADA Loopback Paths

trated in the top portion of Figure 16. Figure 17. Optional Power Supply Arrangement

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Figure 20. CS4215 Surface Mount Decoupling Layout Figure 19. CS4215 Decoupling Layout Guideline

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Figure 25. DAC Passband Ripple Figure 26. DAC Transition Band Figure 27. DAC Deviation from Linear Phase Figure 24. DAC Frequency Response

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Note: All unlabeled pins are No Connects 100 TSIN TSOUT FSYNC SCLK SDOUT SDIN DGND1 VD1 CLKIN CLKOUT XTL1IN MOUT1 MOUT2 AGND2 VA2 VA1 AGND1 VREF CMOUT XTL1OUT VD2 DGND2 XTL2IN XTL2OUT RESET PDN MINR LINR MINL LINL PIO1 PIO0 D/C LOUTR LOUTL HEADL HEADC HEADR CS4215 100-PIN TQFP (Q) Top View CS4215 DS76F2 31

V A1, V A2 - Analog Power Input, Pins 23(L), 24(L), 37(Q), 39 (Q) +5 V analog supply. AGND1, AGND2 - Analog Ground, Pins 22(L), 25(L), 35(Q), 41(Q) Analog ground. Must be connected to DGND1, DGND2 with zero impedance. VD1, VD2 - Digital Power Input, Pins 3(L), 8(L), 91(Q), 4(Q) + 5 V digital supply. DGND1, DGND2 - Digital Ground, Pin 2(L), 9(L), 89(Q), 6(Q) Digital ground. Must be connected to AGND1, AGND2 with zero impedance. CS4215 44-PIN PLCC (L) Top View 18 20 22 24 26 28 12464 0 4244 17 29 SDIN DGND1 SDOUT VD1 SCLK CLKIN FSYNC CLKOUT TSOUT XTL1IN TSIN XTL1OUT NC VD2 NC DGND2 PIO1 XTL2IN PIO0 XTL2OUT D/ C RESET NC PDN LOUTR NC LOUTL MINR HEADL LINR HEADC MINL HEADR LINL MOUT1 CMOUT MOUT2 NC NC VREF AGND2 AGND1 VA2 VA1 CS4215

32 DS76F2

LINL, LINR - Left and Right Channel Line Level Inputs, Pins 18(L), 16(L), 24(Q), 20(Q) Line level input connections for the right and left channels. MINL, MINR - Left and Right Channel Microphone Inputs, Pins 17(L), 15(L), 22(Q), 18(Q) Microphone level input connections for the right and left channels. Analog Outputs LOUTR, LOUTL - Line Level Outputs, Pins 33(L), 32(L), 66(Q), 64(Q) One pair of line level outputs are provided. The output level for right and left outputs can be independently varied. These outputs can be muted. HEADR, HEADL - Headphone Outputs, Pins 29(L), 31(L), 52(Q), 60(Q) HEADR and HEADL are intended to drive a pair of headphones. Additional current drive, along with an optional +3 dB of gain, ensures reasonable listening levels. These outputs can be muted. HEADC - Common Return for Headphone Outputs, Pin 30(L), 56(Q) HEADC is the return path for large currents when driving headphones from the HEADR and HEADL outputs. This pin is nominally at 2.1 V . CMOUT - Common Mode Output, Pin 19(L), 31(Q) Common mode voltage output. This signal may be used for level shifting the analog inputs. The load on CMOUT must be DC only, with an impedance of not less than 10kΩ . CMOUT should be bypassed with a 0.47 µF to AGND. CMOUT is nominally at +2.1V . MOUT1, MOUT2 - Mono Speaker Outputs, Pins 28(L), 27(L), 45(Q), 43(Q) Mono external loudspeaker differential output connections. The loudspeaker output is a mix of left and right line outputs. Independent muting of the speaker is provided. MOUT1 and MOUT2 output voltage is nominally at 2.1 V with no signal. VREF - V oltage Reference Output, Pin 21(L), 33(Q) The on-chip generated ADC/DAC reference voltage is brought out to this pin for decoupling purposes. This output must be bypassed with a 10 µF capacitor in parallel with a 0.1 µF capacitor to the adjacent AGND1 pin. No other external load may be connected to this output. Digital Interface Signals SDIN - Serial Data Input, Pin 1(L), 87(Q) Audio data for the DACs and control information for all functions is presented to the CS4215 on this pin. SDOUT - Serial Data Output, Pin 44(L), 85(Q) Audio data from the ADCs and status information concerning all functions is written out by the CS4215 onto this pin. CS4215 DS76F2 33

SCLK - Serial Port Clock, Pin 43(L), 83(Q) SCLK rising causes the data on SDOUT to be updated. SCLK falling latches the data on SDIN into the CS4215. The SCLK signal can be generated off-chip, and input into the CS4215. Alternatively, the CS4215 can generate and output SCLK in data mode. FSYNC - Frame Sync Signal, Pin 42(L), 81(Q) The Frame Synchronizing Signal is sampled by SCLK, with a rising edge indicating a new frame is about to start. FSYNC frequency is always the system sample rate. Each frame may have 64, 128 or 256 data bits, allowing for 1, 2 or 4 CS4215s connected to the same bus. FSYNC may be input to the CS4215, or may be generated and output by the CS4215 in data mode. When FSYNC is an input, it must be high for at least 1 SCLK period. FSYNC can stay high for the rest of the frame, but must return low at least 2 SCLKs before the next frame starts. TSIN - Time Slot Input, Pin 40(L), 77(Q) TSIN high for at least 1 SCLK cycle indicates to the CS4215 that the next time slot is allocated for it to use. TSIN is normally connected to the TSOUT pin of the previous device in the chain. TSIN should be connected to FSYNC for the 1st (or only) CS4215 in the chain. TSOUT - Time Slot Output, Pin 41(L), 79(Q) TSOUT goes high for 1 SCLK cycle, indicating that the CS4215 is about to release the data bus. Normally connected to the TSIN pin on the next device in the chain. D/C - Data/Control Select Input, Pin 35(L), 70(Q) When D/ C is low, the information on SDIN and SDOUT is control information. When D/C is high, the information on SDIN and SDOUT is data information. PDN - Power Down Input, Pin 13(L), 16(Q) When high, the PDN pin puts the CS4215 into the power down mode. In this mode HEADC and CMOUT will not supply current. Power down causes all the control registers to change to the default reset state. In the power down mode, the TSOUT pin remains active, and follows TSIN delayed by less than 10 ns. RESET - Active Low Reset Input, Pin 12(L), 14(Q) Upon reset, the values of the control information (when D/C = 0) will be initialized to the values given in the Reset Description section of this data sheet. Clock and Crystal Pins XTL1IN, XTL1OUT, XTL2IN, XTL2OUT - Crystals 1 and 2 Inputs and Outputs, Pins 6(L), Input and output connections for crystals 1 and 2. One of these oscillators may provide the master clock to run the CS4215. CLKIN - External Clock Input, Pin 4(L), 93(Q) External clock input optionally used to clock the CS4215. The CLKIN frequency must be 256 times the maximum sample rate (FSYNC frequency). CS4215

34 DS76F2

CLKOUT - Master Clock Output, Pin 5(L), 95(Q) Master clock output, whose frequency is always 256 times the system sample rate (FSYNC frequency). CLKOUT is active only in data mode and is low during control mode. Miscellaneous Pins PIO0, PIO1 - Parallel Input/Output, Pins 36(L), 37(L), 72(Q), 74(Q) These pins are provided as general purpose digital parallel input/output and have open drain outputs. An external pull-up resistor is required. They can be read in control mode, and read and written to in data mode. Note: All unlabeled pins are No Connects which should be left floating. CS4215 DS76F2 35

The number of bits in the input words to the DACs, and in the output words in the ADCs. Differential Nonlinearity The worst case deviation from the ideal codewidth. Units in LSB. Total Dynamic Range The rms value of a full scale signal to the lowest obtainable noise floor. It is measured by comparing a full scale signal to the lowest noise floor possible in the codec (ie. attenuation bits for the DACs at full attenuation.) Units in dB. Instantaneous Dynamic Range The dynamic range available at any instant in time. It is measured using S/(N+D) with a 1 kHz, -60 dB input signal, with 60 dB added to compensate for the small input signal. Use of a small input signal reduces to harmonic distortion components of the noise to insignificance. Units in dB. Total Harmonic Distortion THD is the ratio of the rms value of a signal’s first five harmonic components to the rms value of the signals fundamental component. THD is calculated for the ADCs using an input signal which is 3dB below typical full-scale, and is referenced to typical full-scale. A digital full-scale output is used to calculate THD for the DACs. Interchannel Isolation The amount of 1 kHz signal present on the output of the grounded input channel with 1 kHz 0 dB signal present on the other channel. Units in dB. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units in dB. Frequency Response Worst case variation in output signal level versus frequency over 10 Hz to 20 kHz. Units in dB. Step Size Typical delta between two adjacent gain or attenuation values. Units in dB. Absolute Step Error The deviation of a gain or attenuation step from a straight line passing through the no-gain/attenuation value and the full-gain/attenuation value (i.e. end points). Units in dB. CS4215

36 DS76F2

The ratio of the rms sum of the energy from 0.46xFs to 2.1xFs compared to the rms full-scale signal value. Tested with 48kHz Fs giving an out-of-band energy range of 22kHz to 100kHz. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input at CMOUT. For the DACs, the deviation of the output from CMOUT with mid-scale input code. Units in volts. CS4215 DS76F2 37

This data sheet describes version 2 of the CS4215. Therefore, this appendix is included to describe the differences between versions 0,1 and version 2. This information is only useful for users that still have version 0 and version 1 devices since version 2 devices will supplant the earlier versions. The version number can be found in control mode, time slot 7. The version can also be identified by the revision letter stamped on the top of the actual chip. The revision letter immediately precedes the data code on the second line of the package marking (See General Information section of the Crystal Data Book). V ersion 0 corresponds to chip revision C, version 1 corresponds to chip revision D, and version 2 cor- responds to chip revision E. Future chip revisions (ie. F, G, H) may still be version 2 since the version number only changes if there is a register change to the part that will affect driver software. The Functional Differences Between Version 0(Rev. C) and Version 1(Rev. D) 1. FSYNC on version 0 must be ONLY one SCLK period high, whereas on version 1 FSYNC must be A T LEAST one SCLK period high. 2. When driving an external CMOS clock into one of the XTL-IN pins, version 0 devices must have a series resistor of at least 1kΩ between the CS4215 and the clock source. The resistor is needed be- cause the codec will put XTL-IN to ground (on version 0 only) when that crystal is not selected, as is the case on power-up. In version 1 the XTL-IN pins are floated when not selected; therefore, the series resistor is not needed on version 1. V ersion 1 will work properly if the resistor is included. 3. The OLB and ITS bits do not exist on version 0. Writing these bits as zero makes both versions function identically; therefore, version 1 is backwards compatible with version 0. 4. When entering control mode, CLKOUT stops 4 to 12 clocks later and may start up briefly when switching master clock sources on version 0. On version 1 CLKOUT stops within two clocks and doesn’t start up until data mode is entered. 5. In version 0 the headphone and speaker outputs are not short-circuit protected, whereas in version 1 they are short-circuited protected. The functional differences between Version 1(Rev. D) and Version 2(Rev. E) 1. The MLB, HPF, and MCK2 bits in control mode do not exist in version 0 or version 1. Writing these bits as zero makes all versions functionally identical; therefore, version 2 is backwards compat- ible with previous versions. 2. The A/D invalid bit, ADI, in data mode does not exist in version 0 or version 1. 3. The 8-bit unsigned data format (DF1,0=3) does not exist in version 0 or version 1. 4. SDOUT contained random data during calibration in versions 0 and 1. SDOUT outputs zeros dur- ing calibration in version 2. CS4215

38 DS76F2

• •Easy DSP Hook-Up
• •Correct Grounding and Layout
• •Microphone Pre-Amplifier
• •Line Input Buffer
• •Digital Patch Area General Description The CDB4215 evaluation board allows easy evaluation of the CS4215 audio multimedia codec. Analog inputs provided include two 1/4" microphone jacks and two BNC line inputs. Analog outputs provided are two BNC line outputs, one stereo 1/4" headphone jack and one pair of speaker terminals. Digital interfacing is facilitated by two buffered ribbon cable headers. One contains the serial port and the other contains the codec control pins. ORDERING INFORMATION: CDB4215 JUL ’93 DS76DB3 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445 7222 Fax: (512) 445 7581 CS4215 Evaluation Board Semiconductor Corporation CDB4215 Copyright  Crystal Semiconductor Corporation 1992 (All Rights Reserved) CS4215 +5VA Digital I/O Buffers PIO Indicators Digital Patch Area Line Inputs Microphone Jacks Line Outputs Headphone Jack Speaker Terminals CLKOUT AGND +5VDDGND CLKIN A = 23 dB A = - 6 dB Serial Port Header Control Pin Header

The CDB4215 is designed to provide an easy platform for evaluating the performance of the CS4215 Multimedia Audio Codec. The board provides a buffered serial interface for easy con- nection to the serial port of a DSP or other serial device. A single +5 V power supply is all that is required to power the evaluation board. The line input buffers are designed to accept standard CD-level inputs of 2 VRMS and BNC- to-phono adapters are included to support various test setups. The microphone inputs con- sist of two 1/4" mono jacks that are designed to accept standard single-ended dynamic or con- denser microphones. The line outputs are supplied via BNC jacks with two more BNC-to-phono adapters. The headphone output is supplied via a 1/4" stereo jack and will drive headphones of 48 Ω or greater. This includes most "walkman" style headphones. Speaker terminals are provided and can be connected to speakers with an impedance of 32 Ω or greater. The film plots of the board are included to pro- vide an example of the optimum layout, grounding, and decoupling arrangement for the CS4215. POWER SUPPLY CIRCUITRY Figure 1 illustrates a portion of the CDB4215 schematic and includes the CS4215 codec along with power supply circuitry. Power is supplied to the board via two sets of binding posts, one for digital and one for analog. The analog supply must be +5 V olts and supplies power for the en- tire codec (both digital and analog power supply pins) along with the analog input buffers for the line and microphone inputs. The digital supply is also +5 V olts and supplies power to the digital header buffer circuitry. Space for a ferrite bead inductor, L1, has been provided so that the board may be modified to power the codec from the digital supply. Selection of L1 will depend on the characteristics of the noise on the digital sup- ply used. ANALOG INPUTS The analog inputs consist of a pair of 1/4" jacks for two microphones, and a pair of BNC’s for line level inputs. BNC-to-phono adapters are in- cluded to allow testing of the line inputs using coax or standard audio cables. The line-level inputs go through a buffer, Fig- ure 2, with a gain of 0.5 which allows input signals of up to 2 VRMS . The two microphone inputs are single-ended and are designed to work with both condenser and dynamic mics. The microphone input buffer cir- cuit, shown in Figure 3, has a gain of 23 dB thereby defining a full-scale input voltage to the mic jacks of 19.5 mVpp. ANALOG OUTPUTS The CDB4215 includes three analog output paths: a pair of line output BNC’s, a stereo 1/4" headphone jack, and a pair of mono speaker ter- minals. The CS4215 drives the line outputs into an R-C filter and then to a pair of BNC’s. As with the line inputs, BNC-to-phono adapters are provided for flexibility. The line outputs can drive an im- pedance of 10 kΩ or more, which is the typical input impedance of most audio gear. The stereo headphone output can drive head- phones with an impedance of 48 Ω or greater. This includes most "walkman" style headphones. CDB4215

40 DS76DB3

Figure 1. CS4215 & Power Supplies

Figure 3. Microphone Input Buffer Figure 2. Line Input Buffer

42 DS76DB3

Speaker terminals are provided and are labeled MOUT1 and MOUT2. Speakers connected to the terminals must have an impedance of 32 Ω or greater. DC blocking capacitors are included to form a high-pass filter with the speaker imped- ance. This filter blocks very low frequency signals which can heavily distort some inexpen- sive speakers. SERIAL INTERFACE The CDB4215 is primarily designed to evaluate the CS4215 is single chip mode, i.e. only one codec on the serial bus. This is the default state for the CDB4215 and is defined by having the P4 jumper in the "1CHIP" position, see Figure 4, which connects FSYNC to TSIN. This connec- tion defines the board codec’s time slots as the first 64 bits of the frame. The only signals that need to be connected to the DSP are the five sig- nals on header J15. The serial interface is illustrated in Figure 4. If the goal is to connect multiple CDB4215s on the same serial port, jumper P4 must be in the "MULTI" position which disconnects TSIN from FSYNC. The MULTI position also connects an unbuffered SDOUT to header J14. This header pin, SDOUTUB, must be used in lieu of SDOUT since SDOUT is buffered and does not go high impedance during other codec’s time slots. Using the multi-chip scenario, the TSIN header pin must be connected to the previous codec’s TSOUT line and the first codec’s TSIN must be connected, via the header, to FSYNC. Note that when P4 is in the 1CHIP mode, the SDOUTUB pin on header J14 is not connected to the SDOUT pin on the CS4215 and is float- ing. There are two scenario’s that must be addressed when connecting the CDB4215 to a DSP: one is when the codec is the master in data mode and the other is when the codec is a slave in data mode. In control mode the codec is always a slave and FSYNC and SCLK must be driven from the DSP . Since the evaluation board buffers all the signals between the codec and the DSP , the board must "know" which of the two modes is being used. Jumper P3 selects the particular mode. Codec Master Data Mode When the codec is to be programmed as a mas- ter in data mode, the direction of FSYNC and SCLK have to be changed between control mode and data mode. In this case the P3 jumper must be set for "M/S" which uses the D/ C signal to control the direction of the buffers (U7) for SCLK and FSYNC. When P3 is set to M/S, the buffers drive the J15 header in data mode and receives FSYNC and SCLK from the header in control mode. Codec Slave Data Mode When the codec is to be programmed as a slave in data mode, FSYNC and SCLK are always in- puts to the codec. In this mode P3 must be set to "SLA VE" which configures the FSYNC and SCLK buffers to always receive FSYNC and SCLK from the J15 header. As stated in the CS4215 data sheet, when the codec is programmed in slave mode, XCLK = 0 in control mode, SCLK and FSYNC are inputs and must be derived from the same clock used as the master clock for the codec. Although SCLK and FSYNC must be frequency locked to the master clock, there is no phase requirement. CONTROL PINS All control pins, located on header J14, are de- fined as pins that are not essential to the DSP serial port when used in 1CHIP mode. CDB4215 DS76DB3 43

100 Ohm Dip

Figure 4. Digital Interface

44 DS76DB3

Figure 6. CDB4215 Board Silkscreen (Not to Scale)

46 DS76DB3

Figure 7. CDB4215 Compont Side Layout (Not to Scale)

Figure 8. CDB4215 Solder Side Layout (Not to Scale)

48 DS76DB3

D D2/E2 44 pin PLCC NO. OF TERMINALS D2/E2 MAXMIN MAX MIN MILLIMETERS INCHES DIM A D/E 17.6517.40 0.685 B e AA1 B e 0.695 16.6616.51 0.650 0.656 4.574.20 0.180 0.165 0.530.33 0.021 0.013 2.29 0.090 16.0014.99 0.590 0.630 1.19 1.35 0.047 0.053 NOM 17.53 16.59 4.45 0.41 2.79 15.50 1.27 NOM 0.690 0.653 0.175 0.016 0.110 0.610 0.050 3.04 0.120 D1/E1

0.006 0.618 0.547 0.000 MIN 0.642 0.555 0.065 MAX 0.010 0.40 0.016 0.012 0.028 0.015 0.025 DIM D C B A L e 0° 12° 0.14 15.70 13.90 0.00 MIN 0.30 0.375 16.30 14.10 1.66 MAX 0.26 0.70 0.625 12° 100 pin TQFP 0.60 0.024 E D 0.618 0.547 0.642 0.555 E 15.70 13.90 16.30 14.10 e B C A1 A L Terminal Detail 1 0.51 0.20 16.00 14.00 NOM 0.51 0.5 16.00 14.00 0.020 0.008 0.630 0.551 NOM 0.020 0.020 0.630 0.551 - - --A1 M M 1.00 BSC 0.039 BSC

• Notes •

Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation