CS4202

CS4205_05 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

!Integrated Asynchronous I2S Input Port (ZV Port) !Integrated High-Performance Microphone Pre-Amplifier !Integrated Digital Effects Processing for Bass and Treble Response !Digital Docking Including an I2S Output, 3 Synchronous I2S Inputs !Performance Oriented Digital Mixer !SRS© 3D Stereo Enhancement !On-chip PLL for use with External Clock Sources !Dedicated Microphone Analog-to-Digital Converter !Sample Rate Converters !S/PDIF Digital Audio Output !AC ’97 2.1 Compliant !PC Beep Bypass !20-bit Stereo Digital-to-Analog Converters !18-bit Stereo Analog-to-Digital Converters !Three Analog Line-level Stereo Inputs for LINE IN, VIDEO, and AUX !High Quality Pseudo-Differential CD Input !Extensive Power Management Support !Meets or Exceeds the Microsoft® PC 99 and PC 2001 Audio Performance Requirements

Description

The CS4205 is an AC ’97 2.1 compliant stereo audio co- dec designed for PC multimedia systems. It uses industry leading CrystalClear ® delta-sigma and mixed signal technology. The CS405 is the first Cirrus AC ’97 audio codec to feature digita l centric mixing and digital effects. This advanced technology and these features are designed to help enable the design of PC 99 and PC 2001 compliant high-quality audio systems for desk- top, portable, and entertainment PCs. Coupling the CS4205 with a PCI audio accelerator or core logic supporting the AC ’97 interface implements a cost effective, superior quality audio solution. The CS4205 surpasses PC 99, PC 2001, and AC ’97 2.1 au- dio quality standards. ORDERING INFO CS4205-KQZ, Lead Free 48-pin TQFP 9x9x1.4 mm SIGNAL PROCESSING ENGINE LINE CD AUX VIDEO MIC1 MIC2 PHONE PC_BEEP LINE_OUT MONO_OUT ANALOG INPUT MUX AND OUTPUT MIXER AC-LINK AND AC '97 REGISTERS PCM_DATA GAIN / MUTE CONTROLS INPUT MUX Σ OUTPUT MIXER MIXER / MUX SELECTS AC- LINK PWR MGTTESTSYNC BIT_CLK SDATA_OUT SDATA_IN RESET# PCM_DATASRC SRC ID0# ID1# GPIO S/PDIF SERIAL DATA PORT ZV PORT GPIO0/LRCLK GPIO1/SDOUT EAPD/SCLK SPDO/SDO2 18 bit ADC (2ch) 20 bit DAC (2ch) Σ INPUT MIXER AC '97 REG GPIO[2:4]/SDI[1:3] ZSCLK,ZSDATA,ZLRCLK 18 bit ADC (1ch) SRC MIC_PCM_DATA JULY '05 DS489PP4

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Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sale s Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained here- in and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SE- CURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IM- PLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PROD- UCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners.

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1. CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (Standard test conditions unless otherwise noted: Tambient = 25° C, AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; ZAL=100 kΩ/ 1000 pF load for Mono and Line Outputs; CDL = 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz, 18-bit linear coding for ADC functions, 20-bit linear coding for DAC functions; Mixer registers set for unity gain. Notes: 1. Z AL refers to the analog output pin loading and CDL refers to the digital output pin loading. 2. Parameter definitions are given in Section 15 , Parameter and Term Definitions. 3. Path refers to the signal path used to generate this data. These paths are defined in Section 15, Parameter and Term Definitions. 4. This specification is guaranteed by silicon characterization; it is not production tested. Parameter (Note 2) Symbol Path (Note 3) CS4205-KQZ UnitMin Typ Max Full Scale Input Voltage Line Inputs Mic Inputs (10dB = 0, 20dB = 0) Mic Inputs (10dB = 1, 20dB = 0) Mic Inputs (10dB = 0, 20dB = 1) Mic Inputs (10dB = 1, 20dB = 1) A-D A-D A-D A-D A-D 0.91 0.91 0.283 0.091 0.0283 1.00 1.00 0.315 0.10 0.0315 V RMS VRMS VRMS VRMS VRMS Full Scale Output Voltage Line and Mono Outputs D-A 0.91 1.0 1.13 V RMS Frequency Response (Note 4) Analog Ac = ± 0.25 dB DAC Ac = ± 0.25 dB ADC Ac = ± 0.25 dB FR A-A D-A A-D 20,000 20,000 20,000 Hz Hz Hz Dynamic Range Stereo Analog Inputs to LINE_OUT Mono Analog Input to LINE_OUT DAC Dynamic Range ADC Dynamic Range DR A-A A-A D-A A-D dB FS A dB FS A dB FS A dB FS A DAC SNR (-20 dB FS input w/ CCIR-RMS filter on output) SNR D-A - 70 - dB Total Harmonic Distortion + Noise (-3 dB FS input signal): Line Output DAC ADC (all inputs) THD+N A-A D-A A-D -90 -87 -84 -80 -80 -80 dB FS dB FS dB FS Power Supply Rejection Ratio (1 kHz, 0.5 V RMS w/ 5 V DC offset) (Note 4) 40 60 - dB Interchannel Isolation 70 87 - dB Spurious Tone (Note 4) - -100 - dB FS Input Impedance (Note 4) 10 - - kΩ

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ANALOG CHARACTERISTICS (Continued) MIXER CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V) RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V) Parameter (Note 2) Symbol Path (Note 3) CS4205-KQZ UnitMin Typ Max External Load Impedance Line Output, Mono Output 10 - - kΩ Output Impedance Line Output, Mono Output (Note 4) - 730 - Ω Input Capacitance (Note 4) - 5 - pF Vrefout 2.3 2.4 2.5 V Parameter Min Typ Max Unit Mixer Gain Range Span PC Beep Line In, Aux, CD, Video, Mic1, Mic2, Phone Mono Out, Line Out ADC Gain 45.0 46.5 46.5 22.5 dB dB dB dB Step Size All volume controls except PC Beep PC Beep 1.5 3.0 dB dB Parameter Min Typ Max Unit Power Supplies +3.3 V Digital +5 V Digital Analog -0.3 -0.3 -0.3 5.5 5.5 5.5 V V V Total Power Dissipation (Supplies, Inputs, Outputs) - - 1.25 W Input Current per Pin (Except Supply Pins) -10 - 10 mA Output Current per Pin (Except Supply Pins) -15 - 15 mA Analog Input voltage -0.3 - AVdd+ 0.3 V Digital Input voltage -0.3 - DVdd + 0.3 V Ambient Temperature (Power Applied) 0 - 70 °C Storage Temperature -65 - 150 °C Parameter Symbol Min Typ Max Unit Power Supplies +3.3 V Digital +5 V Digital Analog DVdd1, DVdd2 DVdd1, DVdd2 AVdd1, AVdd2 3.135 4.75 4.75 3.3 3.465 5.25 5.25 V V V Operating Ambient Temperature 0 - 70 °C

DIGITAL CHARACTERISTICS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V) Parameter Symbol Min Typ Max Unit DVdd = 3.3V Low level input voltage V il - - 0.80 V High level input voltage V ih 2.15 - - V High level output voltage V oh 3.00 3.25 - V Low level output voltage V ol -0 . 0 3 0 . 3 5 V Input Leakage Current (AC-link inputs) -10 - 10 µA Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA Output buffer drive current BIT_CLK, SPDO/SDO2 SDATA_IN, EAPD/SCLK, GPIO0/LRCLK, GPIO1/SDOUT, GPIO2/SDI1, GPIO3/SDI2, GPIO4/SDI3 (Note 4) mA mA DVdd = 5.0 V Low level input voltage V il - - 0.80 V High level input voltage V ih 3.25 - - V High level output voltage V oh 4.50 4.95 - V Low level output voltage V ol - 0.03 0.35 V Input Leakage Current (AC-link inputs) -10 - 10 µA Output Leakage Current (Tri-stated AC-link outputs) -10 - 10 µA Output buffer drive current BIT_CLK, SPDO/SDO2 SDATA_IN, EAPD/SCLK, GPIO0/LRCLK, GPIO1/SDOUT, GPIO2/SDI1, GPIO3/SDI2, GPIO4/SDI3 (Note 4) mA mA

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AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: Tambient = 25° C, AVdd = 5.0 V, DVdd = 3.3 V; CL = 55 pF load. Parameter Symbol Min Typ Max Unit RESET Timing RESET# active low pulse width T rst_low 1.0 - - µs RESET# inactive to BIT_CLK start-up delay (XTL mode) (OSC mode) (PLL mode) Trst2clk - 4.0 4.0 2.5 µs µs ms 1st SYNC active to CODEC READY ‘set’ T sync2crd -6 2 . 5- µs Vdd stable to RESET# inactive T vdd2rst# 100 - - µs Clocks BIT_CLK frequency F clk - 12.288 - MHz BIT_CLK period T clk_period - 81.4 - ns BIT_CLK output jitter (depends on XTL_IN source) - - 750 ps BIT_CLK high pulse width T clk_high 36 40.7 45 ns BIT_CLK low pulse width T clk_low 36 40.7 45 ns SYNC frequency F sync - 48 - kHz SYNC period T sync_period -2 0 . 8- µs SYNC high pulse width T sync_high -1 . 3- µs SYNC low pulse width T sync_low -1 9 . 5- µs Data Setup and Hold Output propagation delay from rising edge of BIT_CLK T co 81 0 1 2 n s Input setup time from falling edge of BIT_CLK T isetup 10 - - ns Input hold time from falling edge of BIT_CLK T ihold 0-- n s Input signal rise time T irise 2-6 n s Input signal fall time T ifall 2-6 n s Output signal rise time (Note 4) T orise 246 n s Output signal fall time (Note 4) T ofall 246 n s Misc. Timing Parameters End of Slot 2 to BIT_CLK, SDATA_IN low (PR4) T s2_pdown -0 . 2 1 . 0 µs SYNC pulse width (PR4) Warm Reset T sync_pr4 1.0 - - µs SYNC inactive (PR4) to BIT_CLK start-up delay T sync2clk 162.8 285 - ns Setup to trailing edge of RESET# (ATE test mode) (Note 4) T setup2rst 15 - - ns Rising edge of RESET# to Hi-Z delay (Note 4) T off - - 25 ns

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Figure 4. Data Setup and Hold Figure 5. PR4 Powerdown and Warm Reset Figure 6. Test Mode

2.1 AC-Link

Figure 7. All clocking for the serial communication driven from the CS4205 on the SDATA_IN line. Definition, for detailed AC-link information. Figure 7. AC-link Connections

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2.2 Control Registers

The CS4205 contains a se t of AC ’97 compliant control registers, and a set of Cirrus Logic defined control registers. These re gisters control the basic functions and features of the CS4205. Read access- es of the control registers by the AC ’97 controller are accomplished with the requested register index in Slot 1 of a SDATA_OUT frame. The following SDATA_IN frame will contain the read data in Slot 2. Write operations are similar, with the register in- dex in Slot 1 and the write data in Slot 2 of a SDATA_OUT frame. The function of each input and output frame is detailed in Section 4, AC-Link Frame Definition. Individual register descriptions are found in Section 5, Register Interface.

2.3 Sample Rate Converters

The sample rate converters (SRC) provide high ac- curacy digital filters supporting sample frequencies other than 48 kHz to be captured from the CS4205 or played from the controller. AC ’97 requires sup- port for two audio rates (44.1 and 48 kHz) and four modem rates (8, 9.6, 13.714, and 16 kHz). In addi- tion, the Intel ® I/O Controller Hub (ICHx) specifi- cation [9] requires support for five more audio rates (8, 11.025, 16, 22.05, and 32 kHz) and specifies two optional modem rates (24, 48kHz). The CS4205 supports all thes e rates, as shown in Table 12 on page 38.

2.4 Mixers

The CS4205 input and output mixers are illustrated in Figure 8. The stereo input mixer sums together the analog inputs to the CS4205 according to the settings in the volume control registers. The stereo output mixer sums the out put of the stereo input mixer with the PC_BEEP and PHONE signals. The stereo output mix is then sent to the LINE_OUT pins of the CS4205. The mono output mixer gener- ates a monophonic sum of th e left and right audio channels from the stereo input mixer. The mono output mix is then sent to the MONO_OUT pin on the CS4205.

2.5 Input Mux

The input multiplexer controls which analog input is sent to the ADCs. The output of the input mux is converted to stereo 18-bi t digital PCM data and transmitted to the controller by means of the AC-link SDATA_IN signal.

2.6 Volume Control

The CS4205 volume registers control analog input levels to the input mixer and analog output levels, including the master volume level. The PC_BEEP volume control uses 3 dB steps with a range of 0 dB to -45 dB attenuation. All other analog volume con- trols use 1.5 dB steps. Th e analog inputs have a mixing range of +12 dB signal gain to -34.5 dB sig- nal attenuation. The analog output volume controls have a range of 0 dB to -46.5 dB attenuation for LINE_OUT and MONO_OUT.

2.7 Dedicated Mic Record Path

The CS4205 includes a dedicated microphone ADC that supports advanced functions such as speech recognition and internet telephony. The dedicated ADC allows re cording of a microphone input independent of the input mux settings. This enables simultaneous ca pture of microphone and independent stereo sources.

Figure 8. CS4205 Mixer Diagram

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3.1 Analog Centric Mode

Figure 9. Digital Signal Path Overview

3.2 Digital Centric Mode

3.3 Host Processing Mode

output of the digital mixer is captured by the host.

3.4 Multi-Channel Mode

Table 1. AC Mode Control Configurations

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Figure 10. Analog Centric Mode Figure 11. Digital Centric Mode Figure 12. Host Processing Mode Figure 13. Multi-Channel Mode

twelve 20-bit time-divis ion multiplexed slots. spective, not from the CS4205 perspective. frame with the asserti on of the SYNC signal. driven by the controller on the SDATA_OUT pin. latches this data in as the first bit of the frame.

12.288 MHz

Figure 14. AC-link Input and Output Framing

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4.1 AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4205 from the AC ’97 controller. Figure 14 illustrates the serial port timing. The PCM playback data being passe d to the CS4205 is shifted out MSB first in the most significant bits of each slot. Any PCM data from the AC ’97 controller that is not 20 bits wide should be left justified in its corresponding slot and dithered or zero-padded in the unused bit positions. Bits that are reserved should always be ‘cleared’ by the AC ’97 controller.

4.1.1 Serial Data Output Slot Tags (Slot 0)

Valid Frame The Valid Frame bit determines if any of the following slots contain either valid playback data for the CS4205 or data for read/write operations. When ‘set’, at least one of the other AC-link slots contains valid data. If this bit is ‘clear’, the remainder of the frame is ignored. Slot 1 Valid The Slot 1 Valid bit indicates a valid register read/write address for a primary codec. Slot 2 Valid The Slot 2 Valid bit indicates va lid register write data for a primary codec. Slot [3:11] Valid The Slot [3:11] Valid bi ts indicate the validity of data in their corresponding serial data output slots. If a bit is ‘set’, the corresponding output slot contains valid data. If a bit is ‘cleared’, the corresponding slot will be ignored. Slot 12 Valid The Slot 12 Valid bi t indicates if output Slot 12 contains valid GPIO control data. Codec ID[1:0] The Codec ID[1:0] bits determine which codec is being accessed during the current AC-link frame. Codec ID[1:0] = 00 indicates the primary codec is being accessed. Codec ID[1:0] = 01, 10, or 11 indicates one of three possible secondary codecs is being accessed. A Codec ID value of 01, 10, or 11 also indicates a valid read/write address and/or valid register write data for a secondary codec.

4.1.2 Command Address Port (Slot 1)

R/W Read/Write . When this bit is ‘set’, a read of the AC ’97 register specified by the register index bits will occur in the AC ’97 2.x audio codec. When the bit is ‘cleared’, a write will occur. For any read or write access to occur, the Valid Frame bit (F0) must be ‘set’ and the Codec ID[1:0] bits (F[14:15]) must match the Codec ID of the AC ’97 2.x audio codec being accessed. Ad- ditionally, for a primary codec, the Slot 1 Valid bit (F1) must be ‘set’ for a read access and both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘set’ for a write access. For a secondary codec, both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘cleared’ for read and write accesses. See Figure 14 for bit frame positions. RI[6:0] Register Index. The RI[6:0] bits contain the 7-bit register index to the AC ’97 registers in the CS4205. All registers are defined at word addressable boundaries. The RI0 bit must be ‘clear’ to access CS4205 registers. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Valid Frame Slot 1 Valid Slot 2 Valid Slot 3 Valid Slot 4 Valid Slot 5 Valid Slot 6 Valid Slot 7 Valid Slot 8 Valid Slot 9 Valid Slot 10 Valid Slot 11 Valid Slot 12 Valid Res Codec ID1 Codec ID0 Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W RI6 RI5 RI4 RI3 RI2 RI1 RI0 Reserved

4.1.3 Command Data Port (Slot 2)

WD[15:0] Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an ac- cess is a read, this slot is ignored. NOTE: For any write to an AC ’97 register, the write is defined to be an ‘atomic’ access. This means that when the Slot 1 Valid bit in output Slot 0 is ‘set’, the Slot 2 Valid bit in output Slot 0 should always be ‘set’ during the same audio frame. No write access may be split across 2 frames.

4.1.4 PCM Playback Data (Slots 3-11)

PD[19:0] Playback Data. The PD[19:0] bits contain the 20-bit PCM (2’s complement) playback data for the left and right DACs, serial data ports, and/or the S/PDIF transmitter. Table 14 on page 43 lists a cross reference for each function and its respective slot. The mapping of a given slot to the DAC, serial data port, or S/PDIF transmitter is determined by the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and by the SM[1:0] and AMAP bits in the AC Mode Control Register (Index 5Eh).

4.1.5 GPIO Pin Control (Slot12)

GPIO[4:0] GPIO Pin Control. The GPIO[4:0] bits contro l the CS4205 GPIO pins configured as outputs. Write accesses using GPIO pin control bits configured as outputs will be reflected on the GPIO pin output on the next AC-link frame. Write accesses using GPIO pin control bits con- figured as inputs will have no effect and are ignored. If the GPOC bit in the Misc. Crystal Con- trol Register (Index 60h) is ‘set’, the bits in output Slot 12 are ignored and GPIO pins configured as outputs are controlled through the GPIO Pin Status Register (Index 54h). B i t 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 987654 3 2 1 0 WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Reserved Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Not Implemented GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Reserved

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4.2 AC-Link Serial Data Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin from the CS4205 to the AC ’97 con- troller. The data format for the input frame is very similar to the output frame. Figure 14 on page 19 illus- trates the serial port timing. The PCM capture data from the CS4205 is shifted out MSB first in the most significant 18 bits of each slot. The least significant 2 bits in each sl ot will be ‘cleared’. If the host requests PCM data from the AC ’97 Controller that is less than 18 bits wide, the controller should dither and round or just round (but not trun- cate) to the desired bit depth. Bits that are reserved or not implemented in the CS4205 will always be returned ‘cleared’.

4.2.1 Serial Data Input Slot Tag Bits (Slot 0)

Codec Ready Codec Ready. The Codec Ready bit indicates the readiness of the CS4205 AC-link. Immedi- ately after a Cold Reset this bit will be ‘clear’. Once the CS4205 clocks and voltages are sta- ble, this bit will be ‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be attempted by the controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any other analog function. Those must be checked in the Powerdown Con- trol/Status Register (Index 26h) by the controller before any access is made to the mixer reg- isters. Any accesses to the CS4205 while Codec Ready is ‘clear’ are ignored. Slot 1 Valid The Slot 1 Valid bit indicates Slot 1 contains a valid read back address. Slot 2 Valid The Slot 2 Valid bit indicates Slot 2 contains valid register read data. Slot [3:8,11] Valid The Slot [3:8,11] Valid bits indicate Slot [3:8,11] contains valid capture data from the CS4205 ADCs. If a bit is ‘set’, the corresponding input slot contains valid data. If a bit is ‘cleared’, the corresponding slot will be ignored. Slot 12 Valid The Slot 12 Valid bit indicates Slot 12 contains valid GPIO status data.

4.2.2 Status Address Port (Slot 1)

RI[6:0] Register Index. The RI[6:0] bits echo the AC ’97 register address when a register read has been requested in the previous frame. The CS4205 will only echo the register index for a read access. Write accesses will not return valid data in Slot 1. SR[3:9,11] Slot Request. If SRx is ‘set’, this in dicates the CS4205 SRC does not need a new sample on the next AC-link frame for that particular slot. If SRx is ‘clear’, the SRC indicates a new sample is needed on the following frame. If the VRA bit in the Extended Audio Status/Control Register (Index 2Ah) is ‘clear’, the SR[3:9,11] bits are always 0. When VRA is ‘set’, the SRC is enabled and the SR[3:9,11] bits are used to request data. B i t 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Codec Ready Slot 1 Valid Slot 2 Valid Slot 3 Valid Slot 4 Valid Slot 5 Valid Slot 6 Valid Slot 7 Valid Slot 8 Valid 0 0 Slot 11 Valid Slot 12 Valid Reserved B i t 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Res RI6 RI5 RI4 RI3 RI2 RI1 RI0 SR3 SR4 SR5 SR6 SR7 SR8 SR9 0 SR11 0 Reserved

4.2.3 Status Data Port (Slot 2)

RD[15:0] Read Data. The RD[15:0] bits contain the register data requested by the controller from the previous read request. All read requests will return the read address in the input Slot 1 and the register data in the input Slot 2 on the following serial data frame.

4.2.4 PCM Capture Data (Slot 3-8,11)

CD[17:0] Capture Data. The CD [17: 0] bits contain 18-bit PCM (2’s complement) capture data. The data will only be valid when the respective slot valid bit is ‘set’ in input Slot 0. The mapping of a given slot to an ADC is determined by the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and the SM[1:0] and AMAP bits in the AC Mode Control Register (Index 5Eh). The definition of each slot can be found in Table 14 on page 43.

4.2.5 GPIO Pin Status (Slot 12)

GPIO[4:0] GPIO Pin Status. The GPIO[4:0] bits reflect the status of the CS4205 GPIO pins configured as inputs. The pin status of GPIO pins configured as outputs will be reflected back on the GPIO[4:0] bits of input Slot 12 in the next frame. The output GPIO pins are controlled by the GPIO[4:0] pin control bits in output Slot 12. BDI BIOS-Driver Interface. The BDI bit indicates that a BIOS event has occurred. This bit is a logic OR of all bits in the BDI Status Register (Index 7Ah) ANDed with their corresponding bit in the BDI Config Register (Index 6Eh, Address 0Ch). IEC Internal Error Condition. The IEC bit indicates that an internal error, such as an ADC over- range or a digital data overflow has occurred. This bit is a logic OR of all bits in the IEC Status Register (Index 6Eh, Address 0Bh). GPIO_INT GPIO Interrupt. The GPIO_INT bit indicates that a GPIO, BDI, or IEC interrupt event has oc- curred. The occurrence of a GPIO interrupt is determined by the GPIO interrupt requirements as outlined in the GPIO Pin Wakeup Mask Register (Index 52h) description. In this case, the GPIO_INT bit is cleared by writing a ‘0’ to the bit in the GPIO Pin Status Register (Index 54h) corresponding to the GPIO pin which generated the interrupt. The occurrence of a BDI interrupt is determined by the BDI interrupt requirements as outlined in the BDI Control Registers (Index 6Eh, Address 0Ch - 0Dh). In this case, the GPIO_INT bit is cleared by writing a ‘0’ to the bit in the BDI Status Register (Index 7Ah) that generated the interrupt. The occurrence of an IEC interrupt is determined by the IEC interrupt requirements as out- lined in the Internal Error Condition Control/Status Registers (Index 6Eh, Address 09h - 0Bh). In this case, the GPIO_INT bit is cleared by writing a ‘0’ to the bit in the IEC Status Register (Index 6Eh, Address 0Bh) corresponding to the IEC source which generated the interrupt. B i t 1 9 1 8 1 7 1 6 1 5 1 4 1 31 21 11 0 9 8 7 6 5 4 3210 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Reserved Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 0 0 B i t 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 87654 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Res BDI IEC GPIO _INT

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4.3 AC-Link Protocol Violation - Loss of

The CS4205 is designed to handle SYNC protocol violations. The following ar e situations where the SYNC protocol has been violated:

• The SYNC signal is not sampled high for exact- ly 16 BIT_CLK clock cycles at the start of an audio frame.
• The SYNC signal is not sampled high on the 256th BIT_CLK clock period after the previous SYNC assertion.
• The SYNC signal goes active high before the 256th BIT_CLK clock period after the previous SYNC assertion. Upon loss of synchronization with the controller, the CS4205 will ‘clear’ the Codec Ready bit in the serial data input frame un til two valid frames are detected. During this detection period, the CS4205 will ignore all register reads and writes and will discontinue the transmission of PCM capture data. In addition, if the LOSM bit in the Misc. Crystal Control Register (Index 60h) is ‘set’ (default), the CS4205 will mute all analog outputs. If the LOSM bit is ‘clear’, the analog outputs will not be muted.

Table 2. Register Overview for the CS4205

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Table 3. Indirectly Addressed Register Overview

5.1 Reset Register (Index 00h)

SE[4:0] SRS 3D Stereo Enhancement. SE[4:0] = 01 001, indicating this feature is present. ID8 18-bit ADC Resolution. The ID8 bit is ‘s et’, indicating this feature is present. ID7 20-bit DAC resolution. The ID7 bit is ‘s et’, indicating this feature is present. ID5 Loudness. The ID5 bit is ‘set’, indicating this feature is present. ID3 Simulated Stereo. The ID3 bit is ‘set ’, indicating this feature is present. ID2 Bass & Treble. The ID2 bit is ‘set’, indicating this feature is present. ID0 Dedicated Mic PCM in Channel. The ID0 bit is ‘set’, indicating this feature is present. Default 25ADh. The data in this register is read-only data. (Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS4205.

5.2 Master Volume Register (Index 02h)

Mute Master Mute. Setting this bit mu tes the LINE_OUT_L/R output signals. bit sets the left channel attenuation to -46.5 dB by forcing ML[4:0] to a ‘1’ state. ML[5:0] will read back 011111 when ML5 has been ‘set’. See Table 4 for further details. Default 8000h. This value corresponds to 0 dB attenuation and Mute ‘set’.

0 SE4 SE3 SE2 SE1 SE0 0 ID8 ID7 0 ID5 0 ID3 ID2 0 ID0

Table 4. Analog Mixer Output Attenuation

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5.3 Mono Volume Register (Index 06h)

Mute Mono Mute. Setting this bit mu tes the MONO_OUT output signal. Default 8000h. This value corresponds to 0 dB attenuation and Mute ‘set’.

5.4 Master Tone Control Register (Index 08h)

Signal Processing Engine Control Register (Index 6Eh, Address 08h). Signal Processing Engine Control Register (Index 6Eh, Address 08h). Default 0F0Fh. This value corresponds to bypass of bass and treble gain.

0000 B A 3 B A 2 B A 1 B A 0 0000 T R 3 T R 2 T R 1 T R 0

Table 5. Tone Control Values

5.5 PC_BEEP Volume Register (Index 0Ah)

Mute PC_BEEP Mute. Setting this bi t mutes the PC_BEEP input signal. PV[3:0] PC_BEEP Volume Control. The PV[3:0] bits control the gain levels of the PC_BEEP input source to the Input Mixer. Each step corresponds to 3 dB gain adjustment, with 0000 = 0 dB. The total range is 0 dB to -45 dB attenuation. Default 0000h. This value corresponds to 0 dB attenuation and Mute ‘clear’. This register has no effect on the PC_BEEP volume during RESET#.

5.6 Phone Volume Register (Index 0Ch)

Mute Phone Mute. Setting this bi t mutes the Phone input signal. GN[5:0] Phone Volume Control. The GN[4:0] bits cont rol the gain level of the Phone input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The total range is +12 dB to -34.5 dB attenuation. See Table 7 on page 31 for further attenuation levels. Default 8008h. This value corresponds to 0 dB attenuation and Mute ‘set’. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 M u t e 0000000000 P V 3 P V 2 P V 1 P V 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 M u t e 0000000000 G N 4 G N 3 G N 2 G N 1 G N 0

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5.7 Microphone Volume Register (Index 0Eh)

or MIC2 input pin is controlled by the MS bit in the General Purpose Register (Index 20h). 01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 6 for further details. Default 8008h. This value corresponds to 0 dB gain and Mute ‘set’. Table 6. Microphone Input Gain Values

5.8 Analog Mixer Input Gain Registers (Index 10h - 18h)

Mute Stereo Input Mute. Setting this bit mutes the resp ective input signal, both right and left inputs. 01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 7 for further details. 01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 7 for further details. Default 8808h. This value corresponds to 0 dB gain and Mute ‘set’. The Analog Mixer Input Gain Registers are listed in Table 8. Table 7. Analog Mixer Input Gain Values Table 8. Analog Mixer Input Gain Register Index

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5.9 Input Mux Select Register (Index 1Ah)

recording. See Table 9 for possible values. for recording. See Table 9 for possible values. Default 0000h. This value selects the Mic input for both channels.

00000 S L 2 S L 1 S L 0 00000 S R 2 S R 1 S R 0

000 Mic

001 CD Input

010 Video Input

011 Aux Input

100 Line Input

101 Stereo Mix

110 Mono Mix

111 Phone Input

Table 9. Input Mux Selection

5.10 Record Gain Register (Index 1Ch)

Mute Record Gain Mute. Se tting this bit mutes the input to the L/R ADCs. Default 8000h. This value corresponds to 0 dB gain and Mute ‘set’.

5.11 Record Gain Mic Register (Index 1Eh)

Mute Mic Record Gain Mute. When ‘set’, mutes the input to the microphone ADC. Default 8000h. This value corresponds to 0 dB gain and Mute ‘set’. Table 10. Record Gain Values

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5.12 General Purpose Register (Index 20h)

POP PCM Out Path. When ‘clear’, the PCM out path is mixed pre 3D. When ‘set’, the PCM out path is mixed post 3D. ST Stereo Enhancement Enable. When ‘set’, the ST bit enables the simulated stereo enhance- ment via the SRS Mono algorithm. 3D 3D Enable. When ‘set’, the 3D bit enables the 3D stereo enhancement via the SRS Stereo algorithm. LD Loudness Enable. When ‘set’, the LD bit enab les the loudness or “bass boost” via the equal- izer algorithm. MIX Mono Output Path. This bit co ntrols the source of the mono output driver. When ‘clear’, the output of the stereo-to-mono mixer is sent to the mono output. When ‘set’, the output of the microphone boost stage is sent to the mono output. The source of the stereo-to-mono mixer is controlled by the TMM bit in the AC Mode Control Register (Index 5Eh). The source of the microphone boost stage is controlled by the MS bit in the General Purpose Register (Index 20h). MS Microphone Select. The MS bit determines which of the two Mic inputs are passed to the mix- er. When ‘set’, the MIC2 input is selected. When ‘clear’, the MIC1 input is selected. LPBK Loopback Enable. When ‘set’, the LPBK bit enables the ADC/DAC Loopback Mode. This bit routes the output of the ADCs to the input of the DACs without involving the AC-link. Default 0000h 5.13 3D Control Register (Index 22h) CR[3:0] Center Control. The CR[3:0] bits control the amount of the sum signal, (L+R), that is added to the final left and right digital signals. DP[3:0] Depth Control. The DP[3:0 ] bits control the amount of processed difference signal, (L-R)p, that is added to the final left and right digital signals. Default 0000h. This value corresponds to -22.5 dB center and depth attenuation. This register is used to control the center and depth of the SRS stereo enhancement function in the effects engine. Each step corresponds to 1.5 dB gain adjustment, with a total available range from 0 dB to -22.5 dB attenuation. The recommended starting point for listening is -12 dB center attenuation and -4.5 dB depth attenuation, a register value of 070Ch. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 POP ST 3D LD 0 0 MIX MS LPBK 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 CR3 CR2 CR1 CR0 0 0 0 0 DP3 DP2 DP1 DP0

5.14 Powerdown Control/Status Register (Index 26h)

EAPD External Amplifier Power Down. The EAPD pin fo llows this bit and is generally used to power down external amplifiers. The EAPD bit is mutually exclusive with the SDSC bit in the Serial Port Control Register (Index 6Ah). The SDSC bit must be ‘clear’ before the EAPD bit may be ‘set’. If the SDSC bit is ‘set’, EAPD is a read-only bit and always returns ‘0’. PR5 Internal Clock Disable. When ‘set’, the internal master clock is disabled (BIT_CLK running). The only way to recover from setting this bit is through a Cold Reset (driving the RESET# sig- nal active). PR4 AC-link Powerdown. When ‘set ’, the AC-link is powered down (BIT_CLK off). The AC-link can be restarted through a Warm Reset using the SYNC signal, or a Cold Reset using the RE- SET# signal (primary audio codec only). PR3 Analog Mixer Powerdown (Vref off). When ‘set’, the analog mixer and voltage reference are powered down. When clearing this bit, the ANL, ADC, and DAC bits should be checked be- fore writing any mixer registers. PR2 Analog Mixer Powerdown (Vref on). When ‘set’, the analog mixer is powered down (the volt- age reference is still active). When clearing this bit, the ANL bit should be checked before writ- ing any mixer registers. PR1 Front DACs Powerdown. When ‘set’, the DACs are powered down. When clearing this bit, the DAC bit should be checked before sending any data to the DACs. PR0 L/R ADCs and Input Mux Powerdown. When ‘s et’, the ADCs and the ADC input muxes are powered down. When clearing this bit, no valid data will be sent down the AC-link until the ADC bit goes high. REF Voltage Reference Ready Status. When ‘set’, th e REF bit indicates the voltage reference is at a nominal level. ANL Analog Ready Status. When ‘set’, the analog out put mixer, input multiplexer, and volume con- trols are ready. When ‘clear’, no volume control registers should be written. DAC Front DAC Ready Status. When ‘set’, the DACs are ready to receive data across the AC-link. When ‘clear’, the DACs will not accept any valid data. ADC L/R ADCs Ready Status. When ‘set’, the ADCs are ready to send data across the AC-link. When ‘clear’, no data will be sent to the controller. Default 0000h. This value indicates all blocks are powe red on. The lower four bits will change as the CS4205 finishes an initialization and calibration sequence. The PR[5:0] and the EAPD bits are powerdown control for different sections of the CS4205 as well as external am- plifiers. The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular sec- tion of the CS4205 is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must be checked before writing to any mixer registers. See Section 10, Power Management, for more information on the powerdown functions. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EAPD 0 PR5 PR4 PR3 PR2 PR1 PR0 0 0 0 0 REF ANL DAC ADC

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5.15 Extended Audio ID Register (Index 28h)

ID[1:0] Codec ID. These bits indicate the curr ent codec configuration. When ID[1:0] = 00, the CS4205 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4205 is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins and the current clocking scheme, see Table 27 on page 63. AMAP Audio Slot Mapping. The AMAP bit indicates whether the optional AC ’97 2.1 compliant AC-link slot to audio DAC mapping is supported. This bit is a shadow of the AMAP bit in the AC Mode Control Register (Index 5Eh). The PCM playback and capture slots are mapped ac- cording to Table 14 on page 43. VRM Variable Rate Mic Audio. The VRM bit indicates whether variable rate Mic audio is supported. This bit always returns ‘1’, indicating that variable rate mic audio is available. VRA Variable Rate PCM Audio. The VRA bit indicate s whether variable rate PCM audio is support- ed. This bit always returns ‘1’, indicating that variable rate PCM audio is available. Default x209h. The Extended Audio ID Register (Index 28h) is a read-only register. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ID1 ID0 0 0 0 0 AMAP 0 0 0 0 0 VRM 0 0 VRA

5.16 Extended Audio Status/Control Register (Index 2Ah)

PRL Mic ADC Powerdown. When ‘set’, the PRL bit powers down the dedicated Mic ADC and cor- responding input gain stage. To use the dedicated Mic ADC, clear the PRL bit first. MADC Mic ADC Ready Status. When ‘set’, the MADC bit indicates the dedicated Mic ADC is ready to transmit data. VRM Enable Variable Rate Mic Audio. When ‘set’, the VRM bit allows access to the Mic ADC Rate Register (Index 34h). This bit must be ‘set’ in order to use variable mic capture rates. The VRM bit also serves as a powerdown for the Mic ADC SRC block. Clearing VRM will reset the Mic ADC Rate Register (Index 34h) to its default value and the SRC data path is flushed. VRA Enable Variable Rate Audio. When ‘s et’, the VRA bit allows access to the PCM Front DAC Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h). This bit must be ‘set’ in order to use variable PCM playback or capture rates. The VRA bit also serves as a powerdown for the DAC and ADC SRC blocks. Clearing VRA will reset the PCM Front DAC Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default values. The SRC data path is flushed and the Slot Request bits for the currently active DAC slots will be fixed at ‘0’. Default 4000h D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 PRL 0 0 0 0 MADC 0 0 0 0 0 VRM 0 0 VRA

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5.17 Audio Sample Rate Control Registers (Index 2Ch - 34h)

(column 2 in Table 12) and not the one attempted to be written. Default BB80h. This value corres ponds to 48 kHz sample rate. register will always read BB80h. Table 11 lists the SRC registers and their corresponding SRC enable bit. Table 11. Audio Sample Rate Control Register Index Table 12. Directly Supported SRC Sample Rates for the CS4205

5.18 Extended Modem ID Register (Index 3Ch)

ID[1:0] Codec ID. These bits indicate the curr ent codec configuration. When ID[1:0] = 00, the CS4205 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4205 is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins and the current clocking scheme, see Table 27 on page 63. Default x000h. This value indicates no supported modem functions. The Extended Modem ID Register (Index 3Ch) is a read/write register that identifies the CS4205 modem capabilities. Writing any value to this location issues a reset to modem registers (Index 3Ch-54h), including GPIO registers (Index 4Ch - 54h). Audio registers are not reset by a write to this location.

5.19 Extended Modem Status/Cont rol Register (Index 3Eh)

PRA GPIO Powerdown. When ‘set’, the PRA bit powers down the GPIO subsystem. When the GPIO section is powered down, all outputs must be tri-stated and input Slot 12 should be marked invalid when the AC-link is active. To use any GPIO functionality, including Internal Error Signaling, PRA must be cleared first. GPIO GPIO. When ‘set’, the GPIO bit indicates t he GPIO subsystem is ready for use. When ‘set’, input Slot 12 will also be marked valid. Default 0100h

5.20 GPIO Pin Configuration Register (Index 4Ch)

GC[4:0] GPIO Pin Configuration. When ‘set’, the GC [4:0] bits define the corresponding GPIO pin as an input. When ‘clear’, the corresponding GPIO pin is defined as an output. When the SDEN bit in the Serial Port Control Register (Index 6Ah) is ‘set’, the GC[1:0] bits are read-only bits and always return ‘0’. When SDEN is ‘clear’, the GC[1:0] bits function normally. Likewise, GC2 depends on SDI1, GC3 depends on SDI2, and GC4 depends on SDI3. The SDI[1:3] bits are located in the Serial Port Control Register (Index 6Ah). Default 001Fh. This value corresponds to all GPIO pins configured as inputs. After a Cold Reset or a modem Register Reset (see Extended Modem ID Register (Index 3Ch)), all GPIO pins are configured as inputs. The upper 11 bits of this register always return ‘0’. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I D 1 I D 0 00000000000000 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0000000 P R A 0000000 G P I O

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 GC4 GC3 GC2 GC1 GC0

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5.21 GPIO Pin Polarity/Type Config uration Register (Index 4Eh)

puts or outputs. See Table 13 for the various GPIO configurations.

5.22 GPIO Pin Sticky Register (Index 50h)

fined as edge sensitive, “non-sticky” as level sensitive. The upper 11 bits of this register always return ‘0’. Table 13. GPIO Input/Output Configurations

5.23 GPIO Pin Wakeup Mask Register (Index 52h)

GW[4:0] GPIO Pin Wakeup. This regi ster provides a mask for determining if an input GPIO change will generate a wakeup event (0 = no, 1 = yes). When the AC-link is powered up, a wakeup event will be communicated through the assertion of GPIO_INT = 1 in input Slot 12. When the AC-link is powered down (Powerdown Control/Status Register (Index 26h) bit PR4 = 1 for pri- mary codecs), a wakeup event will be communicated through a ‘0’ to ‘1’ transition on SDATA_IN. Default 0000h GPIO bits which have been programmed as inputs, “sticky”, and “wakeup”, upon transition either (high-to-low) or (low-to-high) depending on pin polarity, will cause an AC-link wakeup if and only if the AC-link was powered down. Once the controller has re-established communication with the CS4205 following a Warm Reset, it will continue to signal the wakeup event through the GPIO_INT bit of input Slot 12 until the AC ’97 controller clears the inter- rupt-causing bit in the GPIO Pin Status Register (Index 54h); or the “wakeup”, config, or “sticky” status of that GPIO pin changes. After a Cold Reset or a modem Register Reset (see Extended Modem ID Register (Index 3Ch)) this register defaults to all 0’s, specifying no wakeup event. The upper 11 bits of this register always return ‘0’.

5.24 GPIO Pin Status Register (Index 54h)

GI[4:0] GPIO Pin Status. This register reflects th e state of all GPIO pin inputs and outputs. These values are also reflected in Slot 12 of every SDATA_IN frame. GPIO inputs configured as “sticky” are ‘cleared’ by writing a ‘0’ to the corresponding bit of this register. The GPIO_INT bit in input Slot 12 is ‘cleared’ by clearing all interrupt-causing bits in this register. Default 0000h GPIO pins which have been programmed as inputs and “sticky”, upon transition either (high-to-low) or (low-to-high) depending on pin polarity, will cause the individual GI bit to be ‘set’, and remain ‘set’ until ‘cleared’. GPIO pins which have been programmed as outputs are controlled either through output Slot 12 or through this register, depending on the state of the GPOC bit in the Misc. Crystal Control Register (Index 60h). If the GPOC bit is ‘cleared’, the GI bits in this register are read-only and reflect the status of the corresponding GPIO output pin ‘set’ through output slot 12. If the GPOC bit is ‘set’, the GI bits in this register are read/write bits and control the corresponding GPIO output pins. The default value is always the state of the GPIO pin. The upper 11 bits of this register should be forced to zero in this register and input Slot 12.

5.25 AC Mode Control Register (Index 5Eh)

DACS DAC Source Select. The DACS bit controls the so urce of data routed to the DACs. If this bit is ‘clear’, the DACs will receive data from the DAC slots, see Table 14 for actual slots used. If this bit is ‘set’, the DACs will receive data from the CS4205 digital effects engine. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 GW4 GW3 GW2 GW1 GW0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 GI4 GI3 GI2 GI1 GI0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DACS CAPS1 CAPS0 MICS 0 0 TMM DDM AMAP 0 SM1 SM0 SDOS1 SDOS0 SPDS1 SPDS0

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CAPS[1:0] L/R Capture Source Select. The CAPS[1:0] bits control the source of data routed to the L/R ADC slots, see Table 14 for actual slots used. Table 15 lists the available capture options. If a reserved source is selected, the capture slot data will be fixed to ‘0’. MICS Microphone Capture Source Select. The MICS bit selects the source of data routed to the Mic ADC slot. If this bit is ‘clear’, the Mic capture slot will receive data from the Mic ADC. If this bit is ‘set’, the Mic capture slot will receive the left channel data from the first serial data input port. TMM True Mono Mode. The TMM bit controls the source of the stereo-to-mono mixer that feeds into the mono out select mux. If this bit is ‘clear’, the output of the stereo input mixer is sent to the stereo-to-mono mixer. If this bit is ‘set’, the output of the DAC direct mode mux is sent to the stereo-to-mono mixer. This allows a true mono mix that includes the PC Beep and Phone inputs and also works during DAC direct mode. DDM DAC Direct Mode. The DDM bit cont rols the source of the line output drivers. When this bit is ‘clear’, the CS4205 stereo output mixer drives the line output. When this bit is ‘set’, the CS4205 audio DACs (DAC1 and DAC2) directly drive the line output. AMAP Audio Slot Mapping. The AMAP bit controls whether the CS4205 responds to the Codec ID based slot mapping as outlined in the AC ’97 2.1 Specification. This bit is shadowed in the Extended Audio ID Register (Index 28h). Refer to Table 14 for the slot mapping configura- tions. SM[1:0] Slot Map. The SM[1 :0] bits define the Slot Mapping for the CS4205 when the AMAP bit is ‘cleared’. Refer to Table 14 for the slot mapping configurations. SDOS[1:0] Serial Data Output Source Select. The SDOS[1:0] bits control the source of data routed to the CS4205 first serial data output port. Table 15 on page 43 lists the available source options. If a reserved source is selected, the serial output data will be fixed to ‘0’. SPDS[1:0] S/PDIF Transmitter Source Se lect. The SPDS[1:0] bits control the source of data routed to the S/PDIF transmitter. Table 15 on page 43 lists the available source options. Default 0080h See Section 3, Digital Signal Paths, for more information on using the bits in this register to create various digital signal path options.

Table 14. Slot Mapping for the CS4205

00 L/R ADCs SDOUT slots DAC slots

10 Digital Mixer Digital Mixer Digital Mixer

11 Digital Effects Digital Effects Digital Effects

Table 15. Digital Signal Source Selects

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5.26 Misc. Crystal Contro l Register (Index 60h) DPC DAC Phase Control. This bit controls the phase of the PCM stream sent to the DACs (after SRC). When ‘cleared’ the phase of the signal will remain unchanged. When this bit is ‘set’, each PCM sample will be inverted before being sent to the DACs. 10dB Microphone 10 dB Boost. When ‘set’, the 10dB bit enables an additional boost of 10 dB on the selected microphone input. In combination with the 20dB boost bit in the Microphone Vol- ume Register (Index 0Eh) this bit allows for variable boost from 0 dB to +30 dB in steps of 10 dB. CRST Force Cold Reset. The CRST bit is used as an override to the New Warm Reset behavior defined during PR4 powerdown. If this bit is ‘set’, an active RESET# signal will force a Cold Reset to the CS4205 during a PR4 powerdown. GPOC General Purpose Output Contro l. The GPOC bit specifies the mechanism by which the status of a General Purpose Output pin can be controlled. If this bit is ‘cleared’, the GPO status is controlled through the standard AC ’97 method of setting the appropriate bits in output Slot 12. If this bit is ‘set’, the GPO status is controlled through the GPIO Pin Status Register (Index 54h). LOSM Loss of SYNC Mute Enable. The LOSM bit contro ls the loss of SYNC mute function. If this bit is ‘set’, the CS4205 will mute all analog outputs for the duration of loss of SYNC. If this bit is ‘cleared’, the mixer will continue to function normally during loss of SYNC. The CS4205 ex- pects to sample SYNC ‘high’ for 16 consecutive BIT_CLK periods and then ‘low’ for 240 con- secutive BIT_CLK periods, otherwise loss of SYNC becomes true. Default 0003h D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 Res DPC 0 0 Reserved 10dB CRST Reserved GPOC Reserved LOSM

5.27 S/PDIF Control Register (Index 68h)

SPEN S/PDIF Enable. The SPEN bit enables S/PDIF data transmission on the SPDO/SDO2 pin. The SPEN bit routes the left and right channel data from the AC ’97 controller, the digital mix- er, or the digital effects engine to the S/PDIF transmitter block. The actual data routed to the S/PDIF block are controlled through the SPDS[1:0]/AMAP/SM[1:0] configuration in the AC Mode Control Register (Index 5Eh). This bit can only be ‘set’ if the SDO2 bit in the Serial Port Control Register (Index 6Ah) is ‘0’. If the SDO2 bit is ‘set’, SPEN is a read-only bit and always returns ‘0’. Val Validity. The Val bit is mapped to the V bit (bit 28) of every sub-frame. If this bit is ‘clear’, the signal is suitable for conversion or processing. Fs Sample Rate. The Fs bit indicates the sampling rate for the S/PDIF data. The inverse of this bit is mapped to bit 25 of the channel status block. When the Fs bit is ‘clear’, the sampling frequency is 48 kHz. When ‘set’, the sampling frequency is 44.1 kHz. The actual rate at which S/PDIF data are being transmitted solely depends on the master clock frequency of the CS4205. The Fs bit is merely an indicator to the S/PDIF receiver. L Generation Status. The L bit is mapped to bit 15 of the channel status block. For category codes 001xxxx, 0111xxx and 100xxxx, a value of ‘0’ indicates original material and a value of ‘1’ indicates a copy of original material. For all other category codes the definition of the L bit is reversed. CC[6:0] Category Code. The CC[6:0] bits are mapped to bits 8-14 of the channel status block. Emph Data Emphasis. The Emph bit is mapped to bi t 3 of the channel status block. When ‘set’, 50/15 µs filter pre-emphasis is indicated. When is ‘clear’, no pre-emphasis is indicated. Copy Copyright. The Copy bit is mapped to bit 2 of the channel status block. If the Copy bit is ‘set’ copyright is not asserted and copying is permitted. /Audio Audio / Non-Audio. The /Audio bit is mapped to bit 1 of the channel status block. If the /Audio bit is ‘clear’, the data transmitted over S/PDIF is assumed to be digital audio. If the /Audio bit is ‘set’, non-audio data is assumed. Pro Professional/Consumer. The Pro bit is mapped to bit 0 of the channel status block. If the Pro bit is ‘clear’, consumer use of the audio control block is indicated. If the bit is ‘set’, professional use is indicated. Default 0000h For a further discussion of the proper use of the channel status bits see application note AN22: Overview of Digital Audio Interface Data Structures [3]. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SPEN Val 0 Fs L CC6 CC5 CC4 CC3 CC2 CC1 CC0 Emph Copy /Audio Pro

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5.28 Serial Port Control Register (Index 6Ah)

4Ch). Clearing this bit re-enables the GPIO[1:0] pins and sets the GC[1:0] bits. ing GPIO pin and sets the associated GC bit. trolled through the AMAP/SM[1:0] configuration in the AC Mode Control Register (Index 5Eh). is ‘0’ or the EAPD bit is ‘1’, SDSC is a read-only bit and always returns ‘0’.

00 I 2S

Table 16. Serial Data Format Selection

5.29 Special Feature Address Register (Index 6Ch)

registers, the correct index value must be written to bits A[3:0].

5.30 Special Feature Data Register (Index 6Eh)

mixer settings, effects engine parameters, ZV Port control, and internal error condition signaling. ture Address Register (Index 6Ch).

5.31 Digital Mixer Input Volume Registers (Index 6Eh, Address 00h - 05h)

Mute Digital Mixer Mute. Setting this bit mutes the re spective input signal, both left and right inputs. ume. Each step corresponds to 1 dB gain adjustment. The total range is 0 dB to -63 dB gain. volume. Each step corresponds to 1 dB gain adjustment. The total range is 0 dB to -63 dB gain. Default 8000h. This value corresponds to 0 dB gain and Mute ‘set’. Digital Mixer Input Volume Registers are listed in Table 17.

000000000000 A 3 A 2 A 1 A 0

Table 17. Digital Mixer Input Volume Register Index

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5.32 Serial Data Port Volume Contro l Registers (Index 6Eh, Address 06h - 07h)

Mute Serial Data Port Mute. Setting this bit mutes the respective input signal, both left and right inputs. volume. Each step corresponds to 1 dB gain adjustment. The total range is 0 dB to -63 dB gain. Default 8000h. This value corresponds to 0 dB gain and Mute ‘set’. The Serial Data Port Volume Control Registers are listed in Table 18. Table 18. Serial Port Volume Control Register Index

5.33 Signal Processing Engine Contro l Register (Index 6Eh, Address 08h)

port is routed to both, the left and right channels of the SDI1 volume control. ital volume controls. Table 19 lists the available settings. the EQ algorithm. Table 19 lists the available settings. the EQ algorithm. Table 19 lists the available settings. uation. The total range is 0 dB to -15 dB attenuation. uation. The total range is 0 dB to -15 dB attenuation. Table 19. Volume Change Modes and EQ Filter Selects

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5.34 Internal Error Condition Control/Status Registers (Index 6Eh, Address 09h - 0Bh)

longer present. This behavior is equivalent to “sticky” (edge sensitive) GPIO input pins. Wakeup Mask Register (Index 52h). nal error sources and corrective measures for each source. Table 20. Internal Error Sources and Correction Methods

5.35 BIOS-Driver Interface Control Regi sters (Index 6Eh, Address 0Ch - 0Dh)

E[15:0] Event Configuration. The E[15:0] bits control the BIOS-Driver Interface mechanism. Register (Index 7Ah). This bit remains ‘set’ until it is cleared by the driver, acknowledging the event has been handled. This behavior is equivalent to “non-sticky” (level sensitive) GPIO input pins.

5.36 ZV Port Control/Status Regist ers (Index 6Eh, Address 0Eh - 0Fh)

down. To use the ZV Port and the ASRC, this bit must be ‘set’. on the ZV Port and the ZV input to the digital mixer will be muted. current sample rate can be determined by Fsin = Fsout*Ph/16,777,216, where Fsout is 48 kHz. For more information on how to use these bits see Section 7, ZV Port.

5.37 BIOS-Driver Interface Status Register (Index 7Ah)

dex 6Eh, Address 0Ch - 0Dh), controls the BIOS-Driver Interface mechanism. Table 21. ZV Port Control/Status Register Index

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The BDI Status Register (Index 7Ah) reflects the state of all possible events. If a bit is ‘0’, the corresponding event has not occurred or has already been handled by the driver. If a bit is ‘1’, the corresponding event has occurred and has not been handled by the driver yet. The BDI bit in input slot 12 is a logic OR of all bits in this register ANDed with their cor- responding bit in the BDI Config Register (Index 6Eh, Address 0Ch). After handling an event, the driver should clear it by writing a ‘0’ to the corresponding bit of this register.

5.38 Vendor ID1 Register (Index 7Ch)

Default 4352h. This register contains read-only data.

5.39 Vendor ID2 Register (Index 7Eh)

DID[2:0] Device ID. With a value of DID[2:0] = 101, these bits specify the audio codec is a CS4205. REV[2:0] Revision. With a value of REV[2:0] = 001, th ese bits specify the audio codec revision is ‘A’. Default 595xh. This register contains read-only data. Vendor ID registers is divided into a Device ID field and a Revision field. Table 22 lists the currently defined Device ID’s.

000 CS4297

001 CS4297A

010 CS4294/CS4298

011 CS4299

100 CS4201

101 CS4205

110 CS4291

111 CS4202

Table 22. Device ID with Corresponding Part Number

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6.1 Overview

eration in the CS4205 is optional. trol Registers (Index 6Eh, Address 06h - 07h) . ware to provide this functionality if desired.

6.2 Multi-Channel Expansion

a six channel application using the CS4205. Figure 15. Serial Data Port: Six Channel Circuit

6.3 Digital Docking

docking applications of the CS4205. and LRCLK should also be considered.

6.4 Serial Data Formats

data justification, alignment, and resolution vary. Figure 16. Digital Docking Connection Diagram

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Table 23. Serial Data Formats and Compatible DACs/ADC’s for the CS4205 Figure 17. Serial Data Format 0 (I2S) Figure 18. Serial Data Format 1 (Left Justified) Figure 19. Serial Data Format 2 (Right Justified, 20-bit data) Figure 20. Serial Data Format 3 (Right Justified, 16-bit data)

signals: MCLK, SCLK, LRCLK, and SDATA. data stream. Figure 21 shows the ZV Port format. Registers (Index 6Eh, Address 0Eh - 0Fh). Figure 21. ZV Port Format (I2S, 16-bit data)

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view of Digital Audio Interface Data Structures [3]. S/PDIF Recommended Transformers [4].

• GPIO and Serial Data Port (GPIO0 pin is shared with LRCLK pin, GPIO1 pin is shared with SDOUT pin, and GPIO[4:2] pins are shared with SDI[3:1] pins)
• EAPD and Serial Data Port Serial Clock (EAPD pin is shared with SCLK pin)
• S/PDIF and Second Serial Data Port (SPDO pin is shared with SDO2 pin) Use of the GPIO0/LRCLK, GPIO1/SDOUT, and GPIO[4:2]/SDI[3:1] pins for serial data port has priority over their GPIO functionality. There is no priority assigned to the other two exclusive func- tions. A function currently in use must be disabled or powered down before the corresponding exclu- sive function can be enabled. The following control bits for these functions will behave differently than normal bits: the EAPD bit in the Powerdown Con- trol/Status Register (Index 26h), the GC[4:0] bits in the GPIO Pin Configuration Register (Index 4Ch), the SPEN bit in the S/PDIF Control Register (Index 68h), and the SDI[3:1], SDO2, and SDSC bits in the Serial Port Control Register (Index 6Ah). These bits can become read-only bits if they control a fea- ture that is currently unavailable because the corre- sponding exclusive feature is already in use, or the corresponding master control for this feature is not set. 0.1 µ FR2 DGNDDVdd SPDO/SDO2 S/PDIF_OUT TOTX-173 SPDO/SDO2+5V_PCI DGND 8.2 kΩ DGND DGND 3.3V 247.5 Ω 107.6 Ω 375 Ω 93.75 Ω

Figure 22. S/PDIF Output

1. POWER MANAGEMENT

10.1 AC ’97 Reset Modes

The CS4205 supports four reset methods, as de- fined in the AC ’97 Specification: Cold Reset , Warm Reset, New Warm Reset, and Register Reset. A Cold Reset results in all AC ’97 logic (registers included) initialized to its default state. A Warm Reset or New Warm Reset leaves the contents of the AC ’97 register set unaltered. A Register Reset initializes only the AC ’97 registers to their default states.

10.1.1 Cold Reset

A Cold Reset is achieved by asserting RESET# for a minimum of 1 µs afte r the power supply rails have stabilized. This is done in accordance with the minimum timing specifications in the AC ’97 Seri- al Port Timing section on page 10. Once de-assert- ed, all of the CS4205 registers will be reset to their default power-on states and the BIT_CLK and SDATA_IN signals will be reactivated.

10.1.2 Warm Reset

A Warm Reset allows the AC-link to be reactivated without losing information in the CS4205 registers. A Warm Reset is required to resume from a D3 hot state where the AC-link ha d been halted yet full power had been mainta ined. A primary codec Warm Reset is initiated when the SYNC signal is driven high for at least 1 µs and then driven low in the absence of the BIT_ CLK clock signal. The BIT_CLK clock will not restart until at least 2 nor- mal BIT_CLK clock periods (162.8 ns) after the SYNC signal is de-asserted. A Warm Reset of the secondary codec is reco gnized when the primary codec on the AC-link resumes BIT_CLK genera- tion. The CS4205 will wait for BIT_CLK to be sta- ble to restore SDATA_IN activity, S/PDIF and/or serial data port transm ission on the following frame.

10.1.3 New Warm Reset

The New Warm Reset also allows the AC-link to be reactivated without losing information in the registers. A New Warm Reset is required to resume from a D3 cold state where AC-link power has been removed. New Warm Rese t is recognized by the low-high transition of RE SET# after the AC-link has been programmed into PR4 powerdown. The New Warm Reset functionality can be disabled by setting the CRST bit in the Misc. Crystal Control Register (Index 60h).

10.1.4 Register Reset

The last reset mode provides a Register Reset to the CS4205. This is available only when the CS4205 AC-link is active and the Codec Ready bit is ‘set’. The audio (including extended audio) control reg- isters (Index 00h - 3Ah) and the vendor specific registers (Index 5A h - 7Ah) are reset to their de- fault states by a write of any value to the Reset Reg- ister (Index 00h). The m odem (including GPIO) registers (Index 3Ch - 56h) are reset to their default states by a write of any value to the Extended Mo- dem ID Register (Index 3Ch).

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10.2 Powerdown Controls

bit will be ‘set’ when the hardware is ready. hot or D3cold state has been entered. Table 24. Powerdown PR Bit Functions

Table 25. Powerdown PR Function Matrix for the CS4205 Table 26. Power Consumption by Powerdown Mode for the CS4205

1 Assuming standard resistive load for transformer coupled coaxial S/PDIF output

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crystal, or the internal Phase Locked Loop (PLL).

11.1 PLL Operation (External Clock)

(Index 3Ch) will always report ‘00’ in PLL mode. the system clock as shown in Figure 24.

11.3 Secondary Codec Operation

Figure 23. PLL External Loop Filter

24.576 MHz

Figure 24. External Crystal Table 27. Clocking Configurations for the CS4205

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1. ANALOG HARDWARE

The analog input section c onsists of four stereo line-level inputs (LINE_L/R, CD_L/GND/R, VIDEO_L/R, and AUX_ L/R), two selectable mono microphone inputs (M IC1 and MIC2), and two mono inputs (PC_BEEP and PHONE). The an- alog output section cons ists of a mono output (MONO_OUT) and a ster eo line-level output (LINE_OUT_L/R). This section describes the ana- log hardware needed to in terface with these pins. The designs presented in this section are compliant with Chapter 17 of Microsoft’s ® PC 99 System De- sign Guide [7] (referred to as PC 99) and Chapter 11 of Microsoft’s® PC 2001 System Design Guide [8] (referred to as PC 2001). For information on EMI reduction techniques refer to the application note AN165: CS4297A/CS4299 EMI Reduction Techniques [5].

12.1 Analog Inputs

All analog inputs to the CS4205, including CD_GND, should be capaci tively coupled to the input pins. Unused analog inputs should be tied to- gether and connected through a capacitor to analog ground or tied to the Vrefout pin directly. The max- imum allowed voltage for analog inputs, except the microphone input, is 1 V RMS. The maximum al- lowed voltage for the microphone input depends on the selected boost setting.

12.1.1 Line Inputs

Figure 25 shows circuitry for a line-level stereo in- put. Replicate this circuit for the Video and Aux in- puts. This design atte nuates the input by 6 dB, bringing the signal from the PC 99 specified RMS, to the CS4205 maximum allowed 1 VRMS.

12.1.2 CD Input

The CD line-level input has an extra pin, CD_GND, providing a pse udo-differential input for both CD_L and CD_R . This pin takes the common-mode noise out of the CD inputs when connected to the CD analog source ground. Follow- ing the reference desi gns in Figure 26 and Figure 27 provides extra attenuation of common mode noise coming from the CD-ROM drive, thereby producing a higher quality signal. One per- cent resistors are reco mmended since closely matched resistor values provide better com- mon-mode attenuation of unwanted signals. The circuit shown in Figure 26 can be used to attenuate a 2 V RMS CD input signal by 6 dB. The circuit shown in Figure 27 can be used for a 1 V RMS CD input signal. LINE_IN_R LINE_IN_L 6.8 kΩ 1.0 µ F 1.0 µ F AGND AGND 6.8 kΩ 6.8 kΩ6.8 kΩ Figure 25. Line Input (Replicate for Video and AUX) Figure 26. Differential 2 VRMS CD Input Figure 27. Differential 1 VRMS CD Input

12.1.3 Microphone Inputs

gain can be set to 0 dB, 10 dB, 20 dB, or 30 dB.

12.1.4 PC Beep Input

should be tied to analog ground instead of +5VA. analog inputs and may be used for other purposes.

12.1.5 Phone Input

a line-level source of 2 VRMS.

12.2 Analog Outputs

Figure 28. Microphone Input Figure 29. PC_BEEP Input Figure 30. Modem Connection

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be greater than 10 kΩ for the line output).

12.2.1 Stereo Output

12.2.2 Mono Output

12.3 Miscellaneous Analog Signals

at each analog input pin unnecessary. away from REFFLT for similar reasons.

12.4 Power Supplies

digital supply as the controller’s AC-link interface. Figure 31. Stereo Output Figure 32. +5V Analog Voltage Regulator

12.5 Reference Design

See Section 16 for a CS4205 reference design.

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1. GROUNDING AND LAYOUT Figure 33 on page 69 shows the conceptual layout for the CS4205 in XTAL or OSC clocking modes. The decoupling capacitors should be located phys- ically as close to the pins as possible. Also, note the connection of the REFF LT decoupling capacitors to the ground return trace connected directly to the ground return pin, AVss1. It is strongly recommende d that separate analog and digital ground planes be used. Separate ground planes keep digital noise and return currents from modulating the CS4205 gr ound potential and de- grading performance. The digital ground pins should be connected to the digital ground plane and kept separate from th e analog ground connections of the CS4205 and any othe r external analog cir- cuitry. All analog components and traces should be located over the analog ground plane and all digital components and traces shou ld be located over the digital ground plane. The common connection point between the two ground planes (required to maintain a common ground voltage potential) should be located under the CS4205. The AC-link digital interface connec- tion traces should be routed such that the digital ground plane lies underneath these signals (on the internal ground layer). This applies along the entire length of these traces from the AC ’97 controller to the CS4205. Refer to the Application Note AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices [2] for more information on layout and design rules.

Figure 33. Conceptual Layout for the CS4205 when in XTAL or OSC Clocking Modes

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Figure 34. Pin Locations for the CS4205

PC_BEEP - Analog Mono Source, Input, Pin 12 The PC_BEEP input is intended to allow the PC system POST (Power On Self-Test) tones to pass through to the audio subsystem. The PC_BEEP input has two connections : the first connect ion is to the analog output mixer, the second co nnection is directly to the LINE_OUT stereo outputs. While the RESET# pin is actively being asserted to the CS4205, the PC_BEEP bypass path to the LINE_OUT outputs is enabled. While the CS4205 is in normal operation mode with RESET# de-asserted, PC_BEEP is a monophonic source to the analog output mi xer. The maximum allo wable input is 1 V RMS (sinusoidal). This input is interna lly biased at the Vrefout voltage reference and requires AC-coupling to external circuitry. If this input is not used, it s hould be connected to the Vr efout pin or AC-coupled to analog ground. PHONE - Analog Mono Source, Input, Pin 13 This analog input is a monophonic source to the out put mixer. It is intended to be used as a modem subsystem input to the audio subsystem. The maximum allowable input is 1 V RMS (sinusoidal). This input is internally biased at the Vrefout voltage re ference and requires AC-coupling to external circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to analog ground. MIC1 - Analog Mono Source, Input, Pin 21 This analog input is a monophonic source to the anal og output mixer. It is intended to be used as a desktop microphone connection to the audio subsystem. The CS4205 internal mixer's microphone input is MUX selectable with either MIC1 or MIC2 as the input. The maximum allowable input is 1 V RMS (sinusoidal). This input is interna lly biased at the Vrefout voltage reference and requires AC-coupling to external circuitry. If this input is not used, it s hould be connected to the Vr efout pin or AC-coupled to analog ground. MIC2 - Analog Mono Source, Input, Pin 22 This analog input is a monophonic source to the analog output mixer. It is intended to be used as an alternate microphone connection to the audio subsystem. The CS4205 internal mixer's microphone input is MUX selectable with either MIC1 or MIC2 as the input. The maximum allowable input is 1 V RMS (sinusoidal). This input is interna lly biased at the Vrefout voltage reference and requires AC-coupling to external circuitry. If this input is not used, it s hould be connected to the Vr efout pin or AC-coupled to analog ground. LINE_IN_L, LINE_IN_R - Analog Line Source, Inputs, Pins 23 and 24 These inputs form a stereo input pair to the CS4205. The maximum allowable input is 1 V RMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or AC-coupled to analog ground. CD_L, CD_R - Analog CD Source, Inputs, Pins 18 and 20 These inputs form a stereo input pair to the CS4205. It is intended to be used for the Red Book CD audio connection to the audio subsystem. The maximum allowable input is 1 V RMS (sinusoidal). These inputs are internally biased at the Vrefout voltage re ference and require AC-coupling to external circuitry. If these inputs are not used, they should both be conn ected to the Vrefout pin or AC-coupled to analog ground. CD_GND - Analog CD Common Source, Input, Pin 19 This analog input is used to remove common mode noise from Red Book CD audio signals. The impedance on the input signal path should be on e half the impedance on the CD_L and CD_R input paths. This pin requires AC-coupling to external circuitr y. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to analog ground.

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VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17 These inputs form a stereo input pair to the CS4 205. It is intended to be used for the audio signal output of a video device. The ma ximum allowable input is 1 V RMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference an d require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or AC-coupled to analog ground. AUX_L, AUX_R - Analog Auxiliary Source, Inputs, Pins 14 and 15 These inputs form a stereo input pair to the CS4205. The maximum allowable input is 1 V RMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or AC-coupled to analog ground. LINE_OUT_L, LINE_OUT_R - Analog Line-Level, Outputs, Pins 35 and 36 These signals are analog outputs from the stereo ou tput mixer. The full-scale output voltage for each output is nominally 1 V RMS (sinusoidal). These outputs are inte rnally biased at the Vrefout voltage reference and require either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biased at the Vrefout voltage. These pins need a 680-1000 pF NPO capacitor attached to analog ground. MONO_OUT - Analog Mono Line-Level, Output, Pin 37 This signal is an analog output from the stereo-to-mono mixer. The full-scale output voltage for this output is nominally 1 V RMS (sinusoidal). This output is internally biased at the Vrefout voltage reference and requires either AC-coupling to external circui try or DC-coupling to a buffer op-amp biased at the Vrefout voltage. This pin needs a 680-1000 pF NPO capacitor attached to analog ground. Analog Reference, Filter, and Configuration Pins REFFLT - Internal Reference Voltage, Input, Pin 27 This signal is the voltage reference used internal to the CS4205. A 0.1 µF and a 2.2 µF ceramic capacitor with short, wide traces must be connected to this pin. No other c onnections should be made to this pin. Do not use an electrolytic 2.2 µF capacitor, use a type Z5U or Y5V ceramic capacitor. Vrefout - Voltage Reference, Output, Pin 28 All analog inputs and outputs are centered around Vref out, nominally 2.4 Volts. This pin may be used to bias external amplifiers. It can also drive up to 5 mA of DC which can be used for microphone bias.

AFLT1 - Left ADC Channel Antialiasing Filter, Input, Pin 29 This pin needs a 1000 pF NPO capa citor connected to analog ground. AFLT2 - Right ADC Channel Antialiasing Filter, Input, Pin 30 This pin needs a 1000 pF NPO capa citor connected to analog ground. AFLT3 - Mic ADC Channel Antialiasing Filter, Input, Pin 31 This pin needs a 1000 pF NPO capa citor connected to analog ground. AC-Link Pins RESET# - AC ’97 Chip Reset, Input, Pin 11 This active low signal is the asynchronous Cold Re set input to the CS4205. The CS4205 must be reset before it can enter normal operating mode. SYNC - AC-Link Serial Port Sync Pulse, Input, Pin 10 SYNC is the serial port timing signal for the AC-link. Its period is the reciproc al of the maximum sample rate, 48 kHz. The signal is generated by the cont roller and is synchronous to BIT_CLK. SYNC is an asynchronous input when the CS4205 is configured as a primary codec and is in a PR4 powerdown state. A series terminating resistor of 47 Ω should be connected on this signal close to the controller. BIT_CLK - AC-Link Serial Port Master Clock, Input/Output, Pin 6 This input/output signal controls the master clock timi ng for the AC-link. In primary mode, this signal is a 12.288 MHz output clock derived from either a 24.576 MHz crystal or from the internal PLL based on the XTL_IN input clock. When the CS4205 is in se condary mode, this signal is an input which controls the AC-link serial interface and generates all inter nal clocking including the AC-link serial interface timing and the analog sampling clocks. A series terminating resistor of 47 Ω should be connected on this signal close to the CS4205 in primary mode or close to the BIT_CLK source in secondary mode. SDATA_OUT - AC-Link Serial Data Input Stream to AC ’97, Input, Pin 5 This input signal receives the cont rol information and digital audio ou tput streams. The data is clocked into the CS4205 on the falling edge of BIT_CL K. A series terminating resistor of 47 Ω should be connected on this signal close to the controller. SDATA_IN - AC-Link Serial Data Output Stream from AC ’97, Output, Pin 8 This output signal transmits the st atus information and digital audio input streams from the ADCs. The data is clocked out of the CS4205 on the rising edge of BIT_CLK. A series terminating resistor of 47 Ω should be connected on this signal close to the CS4205.

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Clock and Configuration Pins XTL_IN - Crystal Input / Clock Input, Pin 2 This pin requires either a 24.576 MHz crystal, with th e other pin attached to XTL_OUT, or an external CMOS clock. XTL_IN must have a crystal or cloc k source attached for proper operation except when operating in secondary codec mode. The crystal frequency must be 24.576 MHz and designed for fundamental mode, parallel resonance operation. If an ex ternal CMOS clock is used to drive this pin, it must run at one of these acceptable frequencies: 14 .31818, 24.576, 27, or 48 MHz. When configured as a secondary codec, all timing is derived from th e BIT_CLK input signal and this pin should be left floating. See Section 11, Clocking, for additional details. XTL_OUT - Crystal Output / PLL Loop Filter, Pin 3 This pin is used for a crystal placed between this pin and XLT_IN. If an external 24.576 MHz clock is used on XTL_IN, this pin must be left floating with no traces or components connected to it. If one of the other acceptable clocks is used on XTL_IN, this pin must be connected to a loop filter circuit. See Section 11, Clocking, for additional details. ID1#, ID0# - Codec ID, Inputs, Pins 45 and 46 These pins select the Codec ID for the CS4205, as well as determine the rate of the incoming clock in PLL mode. They are only sa mpled after the rising edge of RESET#. These pins are in ternally pulled up to the digital supply voltage and should be left floating for logic ‘0’ or tied to digital ground for logic ‘1’. Misc. Digital Interface Pins SPDO/SDO2 - Sony/Philips Digital Interface / Serial Data Output 2, Output, Pin 48 This pin generates the S/PDIF digital output from the CS 4205 when the SPEN bit in the S/PDIF Control Register (Index 68h) is ‘set’. This output may be used to di rectly drive a resistive divider and coupling transformer to an RCA-type connec tor for use with consumer audio equ ipment. This pin also provides the serial data for the second serial data port when the SDO2 bit in the Serial Port Control Register (Index 6Ah) is ‘set’. These two functions are mutually exclusive. When neither function is being used this output is driven to a logic ‘0’. EAPD/SCLK - External Amplifier Powerdown / Serial Clock, Output, Pin 47 This pin is used to control the powerdown state of an audio amplifier external to the CS4205. The output is controlled by the EAPD bi t in the Powerdow n Ctrl/Stat Register (Index 26h). It is driven as a normal CMOS output and defaults low (‘0’) upon power-up. This pin also provides the serial clock for all serial data ports when the SDSC bit in the Serial Port Control Register (Index 6Ah) is ‘set’. GPIO0/LRCLK - General Purpose I/O / Left-Right Clock, Input/Output, Pin 43 This pin is a general purpose I/O pin that can be us ed to interface with various external circuitry. When configured as an input, it functions as a Schmi tt triggered input with 350 mV hysteresis at 5 V and 220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output (4 mA drive) or as an open drain output. This pin also provides the L/R clock for all serial data ports when the SDEN bit in the Serial Port Control Register (Index 6Ah) is ‘set’. This pin powers up in the high impedance state for backward compatibility. GPIO1/SDOUT - General Purpose I/O / Serial Data Output, Input/Output, Pin 44

This pin is a general purpose I/O pin that can be us ed to interface with various external circuitry. When configured as an input, it functions as a Schmi tt triggered input with 350 mV hysteresis at 5 V and 220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output (4 mA drive) or as an open drain output. This pin also provides the serial data for the first serial data port when the SDEN bit in the Serial Port Control Register (Index 6Ah) is ‘set’. This pin powers up in the high impedance state for backward compatibility. GPIO2/SDI1 - General Purpose I/O / Serial Data Input 1, Input/Output, Pin 39 This pin is a general purpose I/O pin that can be us ed to interface with various external circuitry. When configured as an input, it functions as a Schmi tt triggered input with 350 mV hysteresis at 5 V and 220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output (4 mA drive) or as an open drain output. This pin also receives the serial data for the first serial input port when the SDI1 bit in the Serial Port Control Register (Index 6Ah) is ‘set’. This pin powers up in the high impedance state for backward compatibility. GPIO3/SDI2 - General Purpose I/O / Serial Data Input 2, Input/Output, Pin 40 This pin is a general purpose I/O pin that can be us ed to interface with various external circuitry. When configured as an input, it functions as a Schmi tt triggered input with 350 mV hysteresis at 5 V and 220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output (4 mA drive) or as an open drain output. This pin also receives the serial data for the second serial input port when the SDI2 bit in the Serial Port Control Register (Index 6Ah) is ‘set’. This pin powers up in the high impedance state for backward compatibility. GPIO4/SDI3 - General Purpose I/O / Serial Data Input 3, Input/Output, Pin 41 This pin is a general purpose I/O pin that can be us ed to interface with various external circuitry. When configured as an input, it functions as a Schmi tt triggered input with 350 mV hysteresis at 5 V and 220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output (4 mA drive) or as an open drain output. This pin also receives the serial data for the third serial input port when the SDI3 bit in the Serial Port Control Register (Index 6Ah) is ‘set’. This pin powers up in the high impedance state for backward compatibility. ZLRCLK - ZV Port Left-Right Clock, Input, Pin 32 This pin receives the Left/Right clock for the Z oomed Video Port. The L/R clock determines which channel is currently being inputt ed on the ZSDATA pin. The sig nal must conform to the ZV Port Specification. ZSDATA - ZV Port Serial Data, Input, Pin 33 This pin receives two’s complement MSB-first serial audio data for the Zoomed Video Port. The data is clocked into the CS4205 by the ZSCLK, and the ch annel is determined by ZLRCLK. The signal must conform to the ZV Port Specification. ZSCLK - ZV Port Serial Clock, Input, Pin 34 This pin receives the serial clock for the Zoomed Vi deo Port. The serial clock is used to clock data on the ZSDATA pin into the CS4205. The signal must conform to the ZV Port Specification. Power Supply Pins DVdd1, DVss1 - Digital Supply Voltage 1 / Digital Ground 1, Pins 1 and 4

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These pins provide the supply voltage and ground fo r the clocking section of the CS4205. In XTAL or OSC clocking modes DVdd1 should be tied to +5 VD or to +3.3 VD, with DVss1 tied to DGND. In PLL clocking mode, DVdd1 must be tied to +5 VA and DVss1 must be tied to AGND. If connecting these pins to +5 VD or to +3.3 VD and DGND, the CS4205 and controller AC-link should share a common digital supply. DVdd2, DVss2 - Digital Supply Voltage 2 / Digital Ground 2, Pins 9 and 7 These pins provide the digital supply voltage and di gital ground for the AC-link section of the CS4205. In all clocking modes DVdd2 should be tied to +5 VD or to +3.3 VD, with DVss2 tied to DGND. The CS4205 and controller AC-link should share a common digital supply. DVss2 should be isolated from analog ground currents. AVdd1, AVss1 - Analog Supply Voltage 1 / Analog Ground 1, Pins 25 and 26 These pins provide the analog supply voltage an d analog ground for the analog and mixed signal sections of the CS4205. AVdd1 mu st be tied to the +5 VA power supply, with AVss1 connected to AGND. It is strongly recommended the +5 VA power supply be generated from a voltage regulator to ensure proper supply currents and noise immunity fr om the rest of the system. AVss2 should be isolated from digital ground currents AVdd2, AVss2 - Analog Supply Voltage 2 / Analog Ground 2, Pins 38 and 42 The AVdd2 and AVss2 pins are not used on the CS4205 and may be left floating or tied to +5 VA and AGND for backwards compatibility

1. PARAMETER AND TERM DEFINITIONS AC ’97 Specification Refers to the Audio Codec ’97 Component Specification Ver 2.1 published by the Intel ® Corporation [6]. AC ’97 Controller or Controller Refers to the control chip which interfaces to the audio codec AC-link. This has been also called DC ’97 for Digital Controller ’97 [6]. AC ’97 Registers or Codec Registers Refers to the 64-field register map defined in the AC ’97 Specification. ADC Refers to a single Analog-to-Digital converter in the CS4205. “ADCs” refers to the stereo pair of Analog-to-Digital converters. The CS4205 ADCs have 18-bit resolution. Codec Refers to the chip containing the ADCs, DACs, and a nalog mixer. In this data sheet, the codec is the CS4205. DAC Refers to a single Digital-to-Analog converter in the CS4205. “DACs” refers to the stereo pair of Digital-to-Analog converters. The CS4205 DACs have 20-bit resolution. dB FS A dB FS is defined as dB relative to full-scale. The “A” indicates an A weighting filter was used. Differential Nonlinearity The worst case deviation from th e ideal code width. Units in LSB. Dynamic Range (DR) DR is the ratio of the RMS full-scale signal level divided by the RMS sum of the noise floor, in the presence of a signal, available at any instan t in time (no change in gain settings between measurements). Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A. FFT Fast Fourier Transform. Frequency Response (FR) FR is the deviation in signal leve l verses frequency. The 0 dB refe rence point is 1 kHz. The amplitude corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The listed minimum and maximum frequencies are guarant eed to be within the Ac from minimum frequency to maximum frequency inclusive. Fs Sampling Frequency. Interchannel Gain Mismatch For the ADCs, the difference in input voltage to get an equal code on both channels. For the DACs, the difference in output voltages for each channel when both channels are fed the same code. Units are in dB.

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The amount of 1 kHz signal presen t on the output of the grounded AC -coupled line input channel with 1 kHz, 0 dB, signal present on the other line input channel. Units are in dB. Line-level Refers to a consumer equipment compatible, voltage driven interface. The term implies a low driver impedance and a minimum 10 k Ω load impedance. PATHS A-D: Analog in, through the ADCs, onto the serial link. D-A: Serial interface inputs through the DACs to the analog output. A-A: Analog in to Analog out (analog mixer). PC 99 Refers to the PC 99 System Design Guide published by the Microsoft ® Corporation [7]. PC 2001 Refers to the PC 2001 System Design Guide published by the Microsoft ® Corporation [8]. PLL Phase Lock Loop. Circuitry for generating a desired clock from an external clock source. Resolution The number of bits in the output words to the DACs, and in the input words to the ADCs. Signal to Noise Ratio (SNR) SNR, similar to DR, is the ratio of an arbitrary sinu soidal input signal to the RMS sum of the noise floor, in the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB. S/PDIF Sony/Phillips Digital Interface. This interface was established as a me ans of digitally interconnecting consumer audio equipment. The documentation fo r S/PDIF has been superseded by the IEC-958 consumer digital interface document. SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The CS4205 operates at a fixed sample frequency of 48 kHz. The internal sample rate converters are used to convert digital audio streams playing back at other frequencies to 48 kHz. Total Harmonic Distortion plus Noise (THD+N) THD+N is the ratio of the RMS sum of all non-fund amental frequency components, divided by the RMS full-scale signal level. It is tested using a -3 dB FS input signal and is measured over a 20 Hz to 20 kHz bandwidth with units in dB FS.

1 XTL_IN

Figure 35. CS4205 Reference Design

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1. REFERENCES 1) Cirrus Logic, Audio Quality Measurement Specification , Version 1.0, 1997 http://www.cirrus.com/products/papers/meas/meas.html 2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998 3) Cirrus Logic, AN22: Overview of Di gital Audio Interface Data Structures, Version 2.0, February 1998 4) Cirrus Logic, AN134: AES and S/PDIF Recommended Transformers, Version 2, April 1999 5) Cirrus Logic, AN165: CS4297A /CS4299 EMI Reduction Techniques, Version 1.0, September 1999 6) Intel ®, Audio Codec ’97 Component Specification, Revision 2.1, May 1998 http://developer.intel.com/ial/scalableplatforms/audio/index.htm 7) Microsoft ®, PC 99 System Design Guide, Version 1.0, July 1999 http://www.microsoft.com/hwdev/desguid/ 8) Microsoft ®, PC 2001 System Design Guide, Version 1.0, November 2000 http://www.pcdesguide.org/pc2001/default.htm 9) Intel ® 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub, June 1999 http://developer.intel.com/design/chipsets/datashts/290655.htm 10) Intel® 82801BA (ICH2) I/O Controller Hub, October 2000 http://developer.intel.com/design/chipsets/datashts/290687.htm 11) Intel® 82801CAM (ICH3-M) I/O Controller Hub, July 2001 http://developer.intel.com/design/chipsets/datashts/290716.htm

1. PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS022 48L LQFP PACKAGE DRAWING E D1D e L B A