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Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved)http://www.cirrus.com Advance Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Gate Drivers Class-H Controller Advanced ΔΣ Modulator Gate Drivers Internal Oscillator Gain Gain Audio In + Audio In - Shutdown Speaker Out + Speaker Out - GND VBATT 2.5V - 5VLDO Filter Short Circuit/Thermal Protection MODE Low Drop -Out Voltage Regulator Gain Select
2.7 W Mono Class-D Audio Amplifier with Low Idle Current
Hybrid Class-D Architecture – <1 mA Quiescent Current – 1 x 2.7 W into 4 (10% THD+N) – 1 x 2.1 W into 4 (1% THD+N) – 1 x 1.6 W into 8 (10% THD+N) – 1 x 1.3 W into 8 (1% THD+N) Advanced Closed-loop Modulation – 98 dB Signal-to-Noise Ratio (A-Weighted) – 0.02% THD+N @ 1 W (SD & HD Mode) Integrated Protection and Automatic Recovery for Output Short-circuit and Thermal Overload Thermally Enhanced 10-pin DFN Package with Pin-selectable Gain of +6 dB or +12 dB Pop and Click Suppression Common Applications Laptops Netbooks Portable Navigation Devices Active Speakers Portable Gaming General Description The CS35L00 is a 2.7 W high efficiency Hybrid Class-D audio amplifier with low idle current consumption and a selectable gain. The CS35L00 features an advanced closed-loop archi- tecture to provide 0.02% THD+N at 1 W and -75 dB PSRR at 217 Hz. A flexible Hybrid Class-D output stage offers four modes of operation: Standard Class-D (SD) mode of- fers full audio bandwidth and high audio performance; Hybrid Class-D (HD) mode o ffers a substantial reduc- tion in idle power consumption with an integrated Class- H controller; Reduced Frequency Class-D (FSD) mode reduces the output switching frequency, producing low- er electromagnetic interference (EMI); and Reduced Frequency Hybrid Class-D (FHD) mode produces both the lower idle power consum ption of HD mode and the reduced EMI benefits of FSD mode. Requiring minimal external components and PCB space, the CS35L00 is available in a 3.0 mm x 3.0 mm, 10-pin DFN package in Co mmercial grade (-10°C to +70°C). Please see “Ordering Information” on page 33 for package options and gain configurations. CS35L00 MAY '10 DS906A2
2 DS906A2
4 DS906A2
- PIN DESCRIPTIONS FOR CS35L00
SD 1 Shutdown (Input) - Pulling this pin low places the CS35L00 in shutdown. necting this net to VBATT places the device into SD mode. IN+ 4 Positive Analog Input (Input) - Differential positive audio signal input. MODE 5 Switching Mode (Input) - Controls the output switching modes of the CS35L00. OUT- 6 Negative PWM Output (Output) - Differential negative PWM output. VBATT 8 Positive Analog Power Supply (Input) - Positive power supply input. GND 9 Ground (Input) - Power supply ground. OUT+ 10 Positive PWM Output (Output) - Differential Positive PWM output. Thermal Pad” on page 31 for more information. Figure 1. Top View of DFN Pin Out
6 DS906A2
- DIGITAL PIN CONFIGURATIONS See (Note 1) and (Note 2) below the table. Note: 1. Refer to specification table “Digital Interface Specifications & Characteristics” on page 14 for details on the digital I/O characteristics. 2. I/O voltage levels must not exceed the voltage listed in table “Absolute Maximum Ratings” on page 8. Power Supply I/O Name Pin # Direction Internal Connections Configuration VBATT SD 1 Input No Internal Pull Up Hysteresis on CMOS Input MODE 5 Input No Internal Pull Up Hysteresis on CMOS Input GAIN_SEL 7 Input No Internal Pull Up Hysteresis on CMOS Input
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- CHARACTERISTICS & SPECIFICATIONS Test Conditions (unless otherwise specified): GND = 0 V; All voltages with respect to ground; Input Signal = 997 Hz Differential Sine; TA = 25°C; VBATT = 5 V; RL =8 ; 10 Hz to 20 kHz Measurement Bandwidth; Measurements tak- en with AES17 measurement filter and Audio Precision AUX-0025 passive filter. RECOMMENDED OPERATING CONDITIONS GND = 0 V; All voltages with respect to ground. Please see (Note 4). ABSOLUTE MAXIMUM RATINGS GND = 0 V; All voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 4. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. 5. No external loads should be connected to the LFIL T+ net. Any connection of a load to this point may result in errant operation or performance degradation in the device. Parameters Symbol Min Typ Max Units DC Power Supply Supply Voltage VBATT 2.5 5.0 5.5 V Temperature Ambient Temperature T A -10 - +70 °C Junction Temperature T J -10 - +150 °C Parameters Symb ol Min Max Units DC Power Supply Supply Voltage VBATT -0.3 6.0 V LFILT+ Current (Note 5) IVDREG 10 A Inputs Input Current I in -± 1 0 m A Temperature Ambient Operating Temperature (power applied) T A -20 +125 °C Storage Temperature T stg -65 +150 °C
ELECTRICAL CHARACTERISTICS - ALL OPERATIONAL MODES Note: 6. No external loads should be connected to the LFIL T+ net. Any connection of a load to this point may result in errant operation or performance degradation in the device. 7. When VBATT is below this threshold (VB LIM), operation is automatically restricted to SD mode. 8. When operating in HD or FHD mode and the differential input voltage remains below the input level threshold (VIN-LDO) for a period of time (tLDO), the PWM outputs will be powered by the internally generated LDO supply (VLDO). 9. When operating in HD or FHD mode and the diff erential input voltage is above this input level threshold (VIN-VBATT), the PWM outputs will powered directly from the VBATT supply. 10. Refer to Section 5.5 for more information on Thermal Error functionality. Parameters Symbol Test Conditions Min Typ Max Units Max. Current from LFILT+ (Note 6) ILFILT+ -1 0 - A LFILT+ Output Impedance Z LFILT+ -0 . 7 - VBATT Limit for HD/FHD Mode (Note 7) VBLIM -3 . 0 - V D C Input Level for Entering LDO Operation in HD/FHD Modes (Note 8) VIN-LDO GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 0.014•VBATT 0.027•VBATT Vrms Vrms Input Level for Entering VBATT Operation in HD/FHD Modes (Note 9) VIN-VBATT GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 0.09 0.18 Vrms Vrms LDO Entry Time Delay tLDO - 800 - ms LDO Level for HD/FHD Modes VLDO - 1.0 - V Output Offset Voltage VOFFSET Inputs AC coupled to GND -+ / - 2 - m V Amplifier Gain AV GAIN_SEL = Low GAIN_SEL = High dB dB Shutdown Supply Current I A(SD) SD = Low -0 . 0 5 - A MOSFET On Resistance R DS(ON) Ibias = 0.5 A - 380 - m Thermal Error Threshold (Note 10) TTE - 150 - C Thermal Error Retry Time (Note 10) RTE - 100 - ms Under Voltage Lockout Threshold UVLO - 1.9 - V Total Group Delay GD - 10 - s Operating Efficiency Output Levels at 10% THD+N 8 + 33H Load VBATT = 5 VDC - 89 - % VBATT = 3.7 VDC - 88 - % 4 + 33H Load VBATT = 5 VDC - 81 - % VBATT = 3.7 VDC - 80 - %
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ELECTRICAL CHARACTERISTICS - SD MODE Parameters Symbol Test Conditions Min Typ Max Units Output Power (Continuous Average) PO THD+N = 1% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) 1.32/0.92/0.70 2.17/1.50/1.14 W W THD+N = 10% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) 1.65/1.15/0.89 2.72/1.89/1.45 W W Total Harmonic Distortion + Noise THD+N PO = 1.0 W -0 . 0 2 - % Power Supply Rejection Ratio PSRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz dB dB Common-Mode Rejection Ratio CMRR Vripple =1V PP, fripple = 217 Hz -5 5 - d B Signal to Noise Ratio A-Weighted SNRA Inputs AC Coupled to Ground, Referenced to 1% THD+N (Note 12) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) dB dB Idle Channel Noise A-Weighted ICNA AIN+ connected to AIN- GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) Vrms Vrms Idle Channel Noise ICN AIN+ connected to AIN- GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 100 100 Vrms Vrms Frequency Response FR 20 Hz to 20 kHz -0.1 0 0.4 dB Output Switching Frequency fsw1 -1 9 2 - k H z Idle Current Draw (Note 11) IIDLE AIN+ connected AIN-, No Output Load VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC 1.06 1.00 0.97 mA mA mA Input Impedance, Single Ended Z IN GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 100 Input Voltage @ 1 % THD+N V ICLIP RL = 8 (VBATT = 5.0/4.2/3.7 VDC) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 0.84/0.70/0.62 1.68/1.40/1.22 Vrms Vrms
ELECTRICAL CHARACTERISTICS - FSD MODE Note: 11. Idle Current Draw (IIDLE) is specified without any output filtering. Refer to Section 5.3 on page 17 for information on output filtering. Parameters Symbol Test Conditions Min Typ Max Units Output Power (Continuous Average) PO THD+N = 1% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) 1.27/0.88/0.68 2.09/1.45/1.10 W W THD+N = 10% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) 1.63/1.14/0.88 2.69/1.87/1.43 W W Total Harmonic Distortion + Noise THD+N PO = 1.0 W - 0.13 - % Power Supply Rejection Ratio PSRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz dB dB Common-Mode Rejection Ratio CMRR Vripple =1V PP, fripple =2 1 7H z -5 5 - d B Signal to Noise Ratio A-Weighted SNRA Inputs AC Coupled to Ground, Referenced to 1% THD+N (Note 12) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) dB dB Idle Channel Noise A-Weighted ICNA AIN+ connected to AIN- GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 300 300 Vrms Vrms Idle Channel Noise ICN AIN+ connected to AIN- GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 660 660 Vrms Vrms Frequency Response FR 20 Hz to 20 kHz -4.0 0 0.5 dB Output Switching Frequency fsw2 - 76 - kHz Idle Current Draw (Note 11) IIDLE AIN+ connected AIN-, No Output Load VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC 0.88 0.86 0.85 mA mA mA Input Impedance, Single Ended Z IN GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 160 240 Input Voltage @ 1 % THD+N V ICLIP RL = 8 (VBATT = 5.0/4.2/3.7 VDC) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 0.82/0.69/0.60 1.64/1.37/1.20 Vrms Vrms
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ELECTRICAL CHARACTERISTICS - HD MODE Parameters Symbol Test Conditions Min Typ Max Units Output Power (Continuous Average) PO THD+N = 1% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) 1.32/0.92/0.70 2.17/1.50/1.15 W W THD+N = 10% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) 1.65/1.15/0.89 2.72/1.89/1.45 W W Total Harmonic Distortion + Noise THD+N PO = 1.0 W - 0.02 - % Power Supply Rejection Ratio PSRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz dB dB Common-Mode Rejection Ratio CMRR Vripple =1V PP, fripple = 217 Hz -5 5- d B Signal to Noise Ratio A-Weighted SNRA Inputs AC Coupled to Ground, Referenced to 1% THD+N (Note 12) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) dB dB Idle Channel Noise A-Weighted ICNA AIN+ connected to AIN- GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) Vrms Vrms Idle Channel Noise ICN AIN+ connected to AIN- GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) Vrms Vrms Frequency Response FR 20 Hz to 20 kHz -0.1 0 0.4 dB Output Switching Frequency fsw1 - 192 - kHz Idle Current Draw (Note 13) IIDLE AIN+ connected AIN-, No Output Load VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC 0.94 0.94 0.94 mA mA mA Input Impedance, Single Ended Z IN GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 100 Input Voltage @ 1 % THD+N V ICLIP RL = 8 (VBATT = 5.0/4.2/3.7 VDC) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 0.84/0.70/0.62 1.68/1.40/1.22 Vrms Vrms
ELECTRICAL CHARACTERISTICS - FHD MODE Note: 12. SNRA dB is referenced to the output signal amplitude resulting in the specified output power at THD+N <1%. See “Parameter Definitions” on page 29 for more information. 13. Idle Current Draw (IIDLE) is specified without any output filtering. Refer to Section 5.3 on page 17 for information on output filtering. At idle, the output devices will switch at the same rate in HD and FHD mode. FHD only changes the output switching frequency when the input levels are above the “Input Level for Entering VBATT Operation in HD/FHD Modes (VIN-VBATT) given in “Electrical Characteristics - All Operational Modes” on page 9. Parameters Symbol Test Conditions Min Typ Max Units Output Power (Continuous Average) PO THD+N = 1% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) 1.27/0.88/0.68 2.09/1.45/1.10 W W THD+N = 10% RL = 8 (VBATT = 5.0/4.2/3.7 VDC) RL = 4 (VBATT = 5.0/4.2/3.7 VDC) 1.63/1.14/0.88 2.69/1.87/1.43 W W Total Harmonic Distortion + Noise THD+N PO = 1.0 W - 0.15 - % Power Supply Rejection Ratio PSRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz dB dB Common-Mode Rejection Ratio CMRR Vripple =1V PP, fripple = 217 Hz -5 5- d B Signal to Noise Ratio A-Weighted SNRA Inputs AC Coupled to Ground, Referenced to 1% THD+N (Note 12) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) dB dB Idle Channel Noise A-Weighted ICNA AIN+ connected to AIN- GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) Vrms Vrms Idle Channel Noise ICN AIN+ connected to AIN- GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 125 125 Vrms Vrms Frequency Response FR 20 Hz to 20 kHz -4.0 0 0.5 dB Output Switching Frequency fsw1 Input level below VIN-LDO -1 9 2- k H z Output Switching Frequency fsw2 Input level above VIN-VBATT - 76 - kHz Idle Current Draw (Note 13) IIDLE AIN+ connected AIN-, No Output Load VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC 0.94 0.94 0.94 mA mA mA Input Impedance, Single Ended Z IN GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 160 240 Input Voltage @ 1 % THD+N V ICLIP RL = 8 (VBATT = 5.0/4.2/3.7 VDC) GAIN_SEL = Low (12 dB) GAIN_SEL = High (6 dB) 0.82/0.69/0.60 1.64/1.37/1.20 Vrms Vrms
14 DS906A2
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS POWER-UP & POWER-DOWN CHARACTERISTICS Note: 14. Start-Up Time (tstart) refers to the internal start-up time from when SD is released to when the device is ready to activate the PWM outputs. The total power-up time from SD release to the PWM outputs becoming active will vary based on the input signal, not exceeding the Start-Up Time + Zero Crossing Power-Up Timeout (tstart +t timeout). For more information refer to Section 5.4. Parameters Symb ol Min Max Units Input Leakage Current I in -± 1 0 A Input Capacitance -1 0 p F SD Pulse Width Requirement 1 - ms Logic I/Os (Applicable to GAIN_SEL, MODE, and SD) High-Level Input Voltage V IH 0.7•VBATT - V Low-Level Input Voltage V IL - 0.3•VBATT V Parameters Symbol Test C onditions Min Typ Max Units Start-Up Time (Note 14) tstart After “Low” to “High” SD Pin transition edge -1 8- m s Zero Crossing Power-Up Timeout ttimeout No audio input applied -2 5- m s Power-Down Time toff After “High” to “Low” SD Pin transition edge -1- m s
5.1 MODE Descriptions
Table 1. LFILT+ and MODE Operation Configurations
5.1.1 Standard Class D Modes of Operation
5.1.1.1 SD Mode
across the entire audio frequency range.
5.1.1.2 FSD Mode
being better EMI performance and power consumption.
5.1.2 Hybrid Class D Modes of Operation
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tioning properly between VBATT and the internal LDO.
5.1.2.1 HD Mode
created at the output of the CS35L00 when operating at low amplitude or idle power.
5.1.2.2 FHD Mode
output stage and its associated components.
5.2 Reducing the Gain with External Series Resistors
signal as is shown in Figure 4 below. Figure 4. Adjusting Gain via External Series Resistance
5.3 Output Filtering with the CS35L00
ing with no external filtering required. device in order to decrease EMI levels.
5.3.1 Reduced Filter Order with the CS35L00
5.3.2 Filter Component Selection
gathered in the EMI testing. present a very high impedance at the frequency corresponding to the tallest peak in the spectral plot. Figure 5. Optional Output Filter Components
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allows the ferrite bead to sufficiently attenuate the problematic high-frequency emissions without compro- mising audio performance.
5.3.3 Output Filter Power Dissipation Considerations
In systems without inductiv e series elements like inductors or ferrite beads, power losses in the output filter are equal to the switching losses that occur in the system due to the cyclical charging and discharging of capacitors connected to the amplifier outputs. In systems that require an inductive series element, con- ducted losses also occur due to the series impedance added to the output path.
5.3.3.1 Conduction Losses for All Modes of Operation
For all modes of operation (SD, FSD, HD, and FH D), conduction losses are governed by the following equation: Where: P = Power dissipated in the series impedance. I = RMS AC output current Z = impedance of the series element at the frequency of the AC current This equation neglects any series impedances presented by the PCB traces or speaker wires in the output path.
5.3.3.2 Switching Loss es in SD/FSD Mode
Switching losses in SD/FSD Mode are governed by the equation Where: P = Power dissipated in the capacitor (neglecting parasites). C = Value of filtering capacitor V = Peak voltage developed across the capacitor f = Switching frequency of the outputs These calculations are straightforward, as the peak voltage is simply the voltage level attached to VBATT, the capacitor is the value of capacitor that has been added for filtering (neglecting parasitic board capac- itances), and the frequency is 192 kHz for SD and 76 kHz for FSD, respectively. 5.3.3.3 Switching Losses in HD/FHD. Many factors affect the switching losses when the device is operated in HD/FHD mode. These factors in- clude the frequency of the content being amplified, the voltage level of VBATT, and the amplitude of the output signal will factor into both the voltage presented across the capacitors and the frequency at which the capacitors are charged or discharged. PI 2Z= P 1 2---CV2f=
Static signals (i.e. sine waves at a fixed amplitude) are easier to consid er than are dynamic signals (i.e. 76 kHz or 192 kHz, and to operate off of the VBATT supply or off of the internally generated LDO.
5.4 Power-Up and Power-Down
ting it into a low power mode.
5.4.1 Recommended Power-Up Sequence
- With the SD pin pulled low, apply power to the CS35L00 and wait for the power supply to be stable.
- Set the SD pin high to begin normal operation.
5.4.1.1 Zero Crossing on Power-Up Functionality
input audio signal during the power-up process. out and the outputs will begin switching immediately. Both tstart and ttimeout are specified in “Power-Up & Power-Down Characteristics” on page 14. Figure 6. Power-Up Timing with Input Figure 7. Power Up Timing without Input
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5.4.2 Recommended Power-Down Sequence
- Mute the audio supplied to the CS35L00. 2. Pull the SD pin low in order to reset the device and put it into the low power mode. 3. The power supply to the CS35L00 can now be removed.
5.5 Over Temperature Protection
The CS35L00 is internally protected against thermal overload. Built in die temperature sensing circuitry monitors the die temperature and will place the device into shut-down if thermal overload occurs. A ther- mal overload is characterized by the die temperature reaching the Thermal Error Threshold (TTE) at which time the outputs will tristate and shut down. If the device has entered into shut-down due to a thermal overload, the die temperature must remain be- low the Thermal Error Threshold (T TE) for the time specified by the Thermal Error Retry Time (R TE) in order for the device to automatically return to normal operation. Both TTE and RTE are specified in “Electrical Characteristics - All Operational Modes” on page 9.
- TYPICAL PERFORMANCE PLOTS
AES17 measurement filter and Audio Precision AUX-0025 passive filter.
6.1 SD Mode Typical Performance Plots
Figure 8. THD+N vs. Output Power - SD Mode Figure 9. THD+N vs. Output Power - SD Mode Figure 11. THD+N vs. Frequency - SD Mode Figure 10. THD+N vs. Frequency - SD Mode Figure 12. THD+N vs. Frequency - SD Mode Figure 13. Frequency Response - SD Mode
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- “Idle Current Draw vs. VBATT - SD Mode” capacitor values refer to CFILT when configured as the
“CS35L00’s Minimized Optional Output Filter”, shown in Figure 5 on page 17. Figure 14. Idle Current Draw vs. VBATT - SD Mode Figure 15. Output Power vs. VBATT - SD Mode Figure 16. Efficiency vs. Output Power - SD Mode Figure 17. Efficiency vs. Output Power - SD Mode Figure 18. Supply Current vs. Output Power - SD Mode Figure 19. Supply Current vs. Output Power - SD Mode
6.2 FSD Mode Typical Performance Plots
Figure 20. THD+N vs. Output Power - FSD Mode Figure 21. THD+N vs. Output Power - FSD Mode Figure 22. THD+N vs. Frequency - FSD Mode Figure 23. THD+N vs. Frequency - FSD Mode Figure 24. THD+N vs. Frequency - FSD Mode Figure 25. Frequency Response - FSD Mode
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- “Idle Current Draw vs. VBATT - FSD Mode” capacitor values refer to CFILT when configured as the
“CS35L00’s Minimized Optional Output Filter”, shown in Figure 5 on page 17. Figure 26. Idle Current Draw vs. VBATT - FSD Mode Figure 27. Output Power vs. VBATT - FSD Mode Figure 28. Efficiency vs. Output Power - FSD Mode Figure 29. Efficiency vs. Output Power - FSD Mode Figure 30. Supply Current vs. Output Power - FSD Mode Figure 31. Supply Current vs. Output Power - FSD Mode
6.3 HD Mode Typical Performance Plots
Figure 32. THD+N vs. Output Power - HD Mode Figure 33. THD+N vs. Output Power - HD Mode Figure 34. THD+N vs. Frequency - HD Mode Figure 35. THD+N vs. Frequency - HD Mode Figure 36. THD+N vs. Frequency - HD Mode Figure 37. Frequency Response- HD Mode
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- “Idle Current Draw vs. VBATT - HD Mode” capacitor values refer to CFILT when configured as the
“VBATT Limit for HD/FHD Mode” (VBLIM), operation is restricted to SD Mode. Figure 38. Idle Current Draw vs. VBATT - HD Mode Figure 39. Output Power vs. VBATT - HD Mode Figure 40. Efficiency vs. Output Power - HD Mode Figure 41. Efficiency vs. Output Power - HD Mode Figure 42. Supply Current vs. Output Power - HD Mode Figure 43. Supply Current vs. Output Power - HD Mode
6.4 FHD Mode Typical Performance Plots
Figure 44. THD+N vs. Output Power - FHD Mode Figure 45. THD+N vs. Output Power - FHD Mode Figure 46. THD+N vs. Frequency - FHD Mode Figure 47. THD+N vs. Frequency - FHD Mode Figure 48. THD+N vs. Frequency - FHD Mode Figure 49. Frequency Response - FHD Mode
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- “Idle Current Draw vs. VBATT - FHD Mode” capacitor values refer to CFILT when configured as the
below “VBATT Limit for HD/FHD Mode” (VBLIM), operation is restricted to SD Mode. Figure 50. Idle Current Draw vs. VBATT - FHD Mode Figure 51. Output Power vs. VBATT - FHD Mode Figure 52. Efficiency vs. Output Power - FHD Mode Figure 53. Efficiency vs. Output Power - FHD Mode Figure 54. Supply Current vs. Output Power - FHD Mode Figure 55. Supply Current vs. Output Power - FHD Mode
- PARAMETER DEFINITIONS Signal to Noise Ratio (SNR) The ratio of the RMS value of the output signal, wher e Pout is equivalent to the specified output power at THD+N<1%, to the RMS value of the noise floor with no input signal applied and measured over the spec- ified bandwidth, typically 20 Hz to 20 kHz. This measurement technique has been accepted by the Electron- ic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise (THD+N) The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified band width (typically 10 Hz to 20 kH z), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Idle Channel Noise (ICN) Measure of the signal present on the outputs of the device when no audio signal is presented to the input pins. For this test, both input pins are shorted together, setting the differential signal to them to zero.
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- PACKAGING AND THERMAL INFORMATION
8.1 Package Drawings and Dimensions (Note 19)
Note: 19. Dimensioning and tolerance per ASME Y 14.5M-1994. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-220 Controlling Dimension is Millimeters.
10 PIN DFN
8.2 Recommend PCB Footprint an d Routing Configuration
the probability of solder bridging and other manufacturing defects.
8.3 Package Thermal Performance
Class D amplifiers, though highly efficient, produce heat through the process of amplifying the audio signal. As is well understood, the amount of heat is very small compared to that of traditional Class AB amplifiers. ature is kept under its Over-Temperature Error Threshold. into the PCB is shown in Table 2. Table 2. JA Specification for Typical PCB Designs
- Test Printed Circuit Board Assembly (PCBA) constructed in accordance with JEDEC standard
JESD51-9. Two-signal, two-plane (2s2p) PCB used.
- Test conducted with still air in accordance with JEDEC standards JESD51, JESD51-2A, and JESD51-
8.4 DFN Thermal Pad
layers; the copper in these ground planes will act as a heat sink for the CS35L00.
32 DS906A2
8.4.1 Determining Maximu m Ambient Temperature
To determine (to a first order approximation) the maximum ambient temperature in which the CS35L00 will operate, the following equations can be used: Where: Tmax = The maximum ambient temperature in which the device can operate. Top = The operating temperature of the device, given a dissipated power “ Pmax” and a known thermal impedance “JA”. TTE = The Over-Temperature Error Threshold, given in the “Characteristics & Specifications” section on page 8. JA = The thermal impedance of the device and PCB. (This value is highly subjective to a number of ap- plication specific scenarios. The numbers given in Table 2 on page 31 can be used for a first order ap- proximation, but proper characterization of the application’s specific PCB and supporting mechanicals is needed to increase the accuracy of the result achieved here.) Pmax = The maximum power at which the amplifier will be operated continuously. (For conservative esti- mates, the 10% THD+N rated power given in “Characteristics & Specifications” section on page 8 can be used. However, this method will predict higher operating temperatures than what may be seen in the ap- plication, since power content of audio signals is much smaller than that of the sine wave used to establish the power specifications.) = The efficiency of the device at the power Pmax. (A safe, conservative assumption is 85%) Tmax TTE Top–=
- ORDERING INFORMATION 10.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order# CS35L00 2.9 W Mono Audio Amplifier with select- able gain 10-DFN Yes Commercial -10° to +70°C Rail CS35L00-CNZ Tape and Reel CS35L00-CNZR Release Changes A1 Initial Release A2 – Updated all output switching frequency references to f sw1 from 200 kHz to 192 kHz. – Updated all output switching frequency references to f sw2 from 80 kHz to 76 kHz. – Updated front page title, feat ures, and common applications. – Updated front page block diagram. – Updated Section 3. Typical Connection Diagrams to show 10 F and 0.1 F power-supply decoupling capacitors. – Reorganized location of individual specifications in electrical characteristics tables based on measured device performance in different operational modes (“Electrical Characteristics - All Operational Modes” on page 9, “Electrical Characteristics - SD Mode” on page 10, “Electrical Characteristics - FSD Mode” on page 11, “Electrical Characteristics - HD Mode” on page 12, and “Electrical Characteristics - FHD Mode” on page 13). – The following specification changes have been made in “Electrical Characteristics - SD Mode” on page 10, “Electrical Characteristics - FSD Mode” on page 11, “Electrical Characteristics - HD Mode” on page 12, and “Electrical Characteristics - FHD Mode” on page 13: – Added “Common-Mode Rejection Ratio” test conditions (V ripple =1V PP and fripple = 217 Hz) – Updated “Signal to Noise Ratio” to be specified as A-Weighted – Updated “Idle Channel Noise” to be sp ecified as both A-Weighted & Unweighted – Updated “Idle Current Draw” to be specified with no load at 3 voltages (5.0 V, 4.2 V, and 3.7 V) – Changed “Max Input Before Clipping specification to “Input Voltage @ 1 % THD+N” – Updated specification typical values for 1% Out put Power, 10% Output Power, THD+N @ 1 W, SNR A-Weighted, Idle Channel Noise A-Weighted, Idle Channel Noise (unweighted), Frequency Response, Output Switching Frequency, Input Impedance, and Input Voltage @ 1% THD+N – Updated “Operating Efficiency” to be specified with 8 + 33 H and 4 + 33 H in “Electrical Characteristics - All Operational Modes” on page 9. – Modified “Power-Up Time” specific ation into “Start-Up Time” and “Zero Crossing Power-Up” and added a cross-reference in “Power-Up & Power-Down Characteristics” on page 14. – Moved power-up and power-down timing specifications from “Electrical Characteristics - All Operational Modes” on page 9 to their own specification table, “Power-Up & Power-Down Characteristics” on page 14. – Renamed “Thermal Error Wait Time (W TE)” to “Thermal Error Retry Time (RTE)” in “Electrical Characteristics - All Operational Modes” on page 9 and in Section 5.5 Over Temperature Protection and added (Note 10) Thermal Error cross reference from spec table to description section. – Updated “Operating Efficiency” specification ( ) in “Electrical Characteristics - All Operational Modes” on page 9. – Updated “MOSFET On Resi stance” specification (RDS(ON)) in “Electrical Characteristics - All Operational Modes” on page 9.
34 DS906A2
A2 – Updated Shutdown Supply Current specification (IA(SD)) in “Electrical Characteristics - All Operational Modes” on page 9. – Added “MOSFET On Resistance” test conditions (I bias =0 . 5A ) i n “Electrical Characteristics - All Operational Modes” on page 9. – Section 5.1.1.1 SD Mode updated to remove references to edge rate control. – Section 5.1.2.1 HD Mode updated to include fsw1 switching frequency and clarify the conditions under which radiated emissions gains occur. – Added Section 6. Typical Performance Plots. – Added Section 5.4 Power-Up and Power-Down. – Modified “Input Level Threshold for HD/FHD Modes” to be split up into “Input Level for Entering LDO Operation in HD/FHD Modes” and “Input Level for Entering VBATT Operation in HD/FHD Modes” in “Electrical Characteristics - All Operational Modes” on page 9. – Added “LDO Entry Time Delay” specification in “Electrical Characteristics - All Operational Modes” on page 9. – Updated (Note 8) and added (Note 9) referring to the “Input Level Thresholds”. – Updated Section 5.5 Over Temperature Protection functional description. – Updated out of date specification names, symbols, and cross-references in multiple locations throughout the document. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) be- lieve that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information t o verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the infor- mation only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.