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Features
Closed-loop Advanced ΔΣ Architecture True Spread Spectrum Modulation Premium Quality Audio Amplification – 99 dB Dynamic Range - System Level – 0.025% THD+N @ 5 W - System Level – -96 dB Channel Separation Four Selectable Amplifier Gain Settings Integrated Protection and Automatic Recovery for Over-current, Under-voltage, and Thermal Overload Single-supply Operation (Typ. = 9-12 V) No Bootstrap Capacitors Required Low-power Standby Mode Supports Differential or Single-ended Inputs Thermally Enhanced 32-pin, 6 x 6 mm QFN Package Requires No External Heat Sink Common Applications Active Speakers Portable Media Player Docking Stations Mini/Micro Shelf Systems Digital Televisions General Description The CS3511 is a high-efficiency class-D PWM amplifier that integrates on-chip over-current, under-voltage, over-temperature protection, and error reporting. An on- board regulator generates a 5 VDC supply used to power the internal low-voltage analog and digital cir- cuitry. The low R DS(ON) outputs can source peak cur- rents up to 2.7 A, deliver high efficiency, allow a small device package, and lower power supply voltage levels. The CS3511 is available in a 32-pin QFN package in Commercial grade (-10°C to +70°C). The CRD3511 customer reference design is also available. Please re- fer to “Ordering Information” on page 24 for complete ordering information. GAIN0 GAIN1 MUTE STATUS Gain Control SLEEP Positive Input Negative Input Positive Input Negative Input Channel 2 Channel 1 PGND Charge Pump 5 V RegulatorDigital PowerAnalog Power Gate Drive Gate Drive Processing and Modulation Channel 2 Positive Output Negative Output Channel 1 Positive Output Negative Output VP 12 V Processing and Modulation CS3511 AUG ‘09 DS845PP2
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- PIN DESCRIPTIONS Pin Name # Pin Description IN1+ IN1- IN2+ IN2- Differential Analog Input (Input) - Differential Audio Signal Inputs for channel 1 and channel 2. V5D 2 Digital Power (Input) - Supply for digital logic. Connect to 5VGEN. GAIN0 GAIN1 22 Gain (Input) - Gain select bits. GAIN0 is the least significant bit. DGND 4 Digital Ground (Input) - Ground reference for the internal logic and digital I/O. REF 5 Reference (Output) - Internal reference voltage. SLEEP 6 Sleep (Input) - When set to logic high, device enters low power mode. If not used, this pin should be grounded. MUTE 7 Mute (Input) - When set to logic high, both amplifiers are muted and in Idle Mode. When low (grounded), both amplifiers are fully operational. If not used, this pin should be grounded. STATUS 8 Status (Output) - A logic high output indicates over-current or under-voltage condition, thermal over- load, that an output is shorted to ground or to another output, that the device is in low power mode (the SLEEP pin is high), or that the device is in reset. A logic low state indicates that the CS3511 is ready to output audio. Thermal Pad 109 11 12 13 14 15 16 2526272829303132 IN1- IN2+ OUT1+ IN1+ Top-Down (Through Package) View 32-Pin QFN Package VP PGND OUT1- OUT2- PGND VP OUT2+ V5D GAIN0 DGND REF SLEEP MUTE STATUS AGND BIASCAP V5A AGND IN2- AGND GAIN1 5VGEN VP DCAP CPUMP PGND
Differential PWM Output (Output) - Differential PWM Outputs for channel 1 and channel 2. VP High Voltage Power (Input) - Supply pins for high current H-bridges. PGND Power Ground (Input) - High current ground for analog outputs. CPUMP 18 Charge Pump Input (Input) - Input pin for charge pump. DCAP 19 Charge Pump Switching Pin (Output) - Free-running 350 kHz square wave between VP and ground. 5VGEN 21 5 Volt Generator (Output) - Regulated 5 VDC source used to supply power to the input section (pins 2 and 28). AGND Analog Ground (Input) - Connect all pins together directly at the thermal pad of the CS3511. IN2+ IN2- 25 Negative Analog Input (Input) - Negative Audio Signal for channel 2 and channel 1, respectively. 31 Pop Minimization Capacitor (Input) - External capacitor used to reduce turn on/off pops. V5A 28 Analog Power (Input) - Supply for analog circuitry. Connect to 5VGEN. BIASCAP 29 Analog Input Bias (Input) - Input stage bias voltage. Thermal Pad - Thermal Pad (Input) - Thermal relief pad for optimized heat dissipation. Connect to PGND. See “QFN Thermal Pad” on page 16 for more information.
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- CHARACTERISTICS AN D SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS AGND = DGND = PGND = 0 V; All voltages with respect to ground. (Note 1) Notes: 1. Device functionality is not guaranteed or implied outs ide of these limits. Operation outside of these limits may adversely affect device reliability. ABSOLUTE MAXIMUM RATINGS AGND = DGND = PGND = 0 V; All voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 2. The outputs will stop switching at the VP Under-Voltage Error Falling Trigger Point. See “DC Electrical Char- acteristics” on page 8. 3. Any pin except supplies. Transient currents of up to ±100 mA on the INxx pins will not cause SCR latch-up. 4. The maximum over/under voltage is limited by the input current. Parameters Symbol Min Typ Max Units DC Power Supply Supply Voltage VP 8.5 12 13.2 V Temperature Ambient Temperature T A -10 - +70 °C Junction Temperature T J -10 - +150 °C Parameters Symb ol Min Max Units DC Power Supply Outputs Switching and Under Load (Note 2) VP - 13.2 V No Output Switching VP -0.3 14.0 Inputs Input Current (Note 3) Iin -± 1 0 m A Digital Input Voltage (Note 4) VIND -0.3 V5D + 0.3 V Temperature Ambient Operating Temperature (power applied) T A -20 +85 °C Storage Temperature T stg -65 +150 °C
AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground; TA = 25°C; VP = 12 V; RL =8 Ω full-bridge; GAIN1 = 0, GAIN0 = 1; 10 Hz to 20 kHz Measurement Bandwidth; Per- formance measurements taken with a differential 997 Hz sine wave and AES17 measurement filter; Stereo Full- Bridge measurements taken through the Full-Bridge Output Filter shown in Figure 4 on page 15. Notes: 5. See Figure 5 on page 17. 6. dBi is referenced to the input signal amplitude resu lting in the specified outp ut power at THD+N<1%. See “Parameter Definitions” on page 21 for more information. 7. See Section 4.2 “Dynamic DC Offset Calibration” on page 12. Parameters Symbol Test Co nditions Min Typ Max Units Output Power (Continuous Average/Channel) (Note 5) PO THD+N = 1% R L = 8 Ω RL = 6 Ω 7.5 9.1 W W THD+N = 7% R L = 8 Ω RL = 6 Ω 8.8 10.8 W W THD+N = 10% R L = 8 Ω RL = 6 Ω 9.4 11.4 W W Total Harmonic Distortion + Noise (Note 5) THD+N PO = 1 W, RL = 8 Ω PO = 5 W, RL = 8 Ω 0.019 0.025 Dynamic Range (Note 6) DYR Vin = -60 dBi A-Weighted Unweighted dB dB Signal to Noise Ratio (Note 6) SNR Inputs AC coupled to AGND A-Weighted Unweighted dB dB Power Supply Rejection Ratio PSRR 200 mv p-p from
20 Hz ≤ f ≤ 1 kHz, inputs AC
-5 5- d B IHF Intermodulation Distortion IHF-IMD 19 kHz, 20 kHz, 1:1 (IHF), Channel Separation CS PO=1 W, f = 1 kHz
20 Hz ≤ f ≤ 20 kHz
Output Offset Voltage (Note 7) VOFFSET MUTE = low -5 0- m V Efficiency η PO = 2 x 9.4 W, RL = 8 Ω -8 5- % PWM Output Over-Current Error Trigger Point I CE -2 . 7-A Junction Thermal Error Rising Trigger Point T TERISE -1 5 5- °C Junction Thermal Error Falling Trigger Point T TEFALL -1 3 5- °C Turn On Time t on SLEEP = VIL -1 5 5- m s Turn Off Time t off SLEEP = VIH -3- m s Amplifier Gain Gain1 = 0, Gain0 = 0 - 13.6 - dB Gain1 = 0, Gain0 = 1 - 19.5 - dB Gain1 = 1, Gain0 = 0 - 23.8 - dB Gain1 = 1, Gain0 = 1 - 27.3 - dB Gain Matching Between output channels - 0.1 - % Input Impedance Gain1 = 0, Gain0 = 0 36.8 46.0 55.2 k Ω Gain1 = 0, Gain0 = 1 18.4 23.0 27.6 k Ω Gain1 = 1, Gain0 = 0 11.0 13.8 16.6 k Ω Gain1 = 1, Gain0 = 1 7.3 9.2 11.1 k Ω
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DC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified): AGND = DGND = PGND = 0 V; All voltages with respect to ground; TA = 25°C; VP = 12 V; RL =8 Ω full-bridge; GAIN1 = 0, GAIN0 = 1; Stereo Full-Bridge measurements taken through the Full-Bridge Output Filter shown in Figure 4 on page 15. DIGITAL INTERFACE SPECIFICATIONS AGND = DGND = PGND = 0 V; All voltages with respect to ground; Unless otherwise specified. Notes: 8. Levels between V IH and VIL are invalid. The transition period between VIH and VIL should not exceed tI. Parameters Symbol Test Conditions Min Typ Max Units Sleep Supply Current ICC(sleep) SLEEP = VIH -5 . 2- m A SLEEP = VIH; no load, filter, or snubber -5 . 2- m A Mute Supply Current ICC(mute) MUTE = VIH -3 8- m A MUTE = VIH; no load, filter, or snubber -3 8- m A Quiescent Current ICC VIN = 0 V; SLEEP = VIL, MUTE = VIL -6 8- m A VIN = 0 V; SLEEP = VIL, MUTE = VIL; no load, filter, or snubber -8 5- m A MOSFET On Resistance (each FET) RDS(ON) Id = 0.5 A, TJ =5 0°C - 325 - m Ω 5VGEN Nominal Voltage - 5.2 - V 5VGEN DC current source - - 70 mA REF Nominal Voltage -1 . 2 -V BIASCAP Nominal Voltage - 2.5 - V VP Under-Voltage Error Falling Trigger Point V UVVPFALL -7 . 5 6- V VP Under-Voltage Error Rising Trigger Point V UVVPRISE -8 . 0 8- V V5A Under-Voltage Error Falling Trigger Point V UV5VFALL -4 . 1-V V5A Under-Voltage Error Rising Trigger Point V UV5VRISE -4 . 3-V Charge Pump Under-Voltage Error Falling Trigger Point VUVCPFALL - 1.55*VP - Charge Pump Under-Voltage Error Rising Trigger Point VUVCPRISE - 1.62*VP - Parameters Symbol Min Max Units High-Level Input Voltage (MUTE, SLEEP) (Note 8) VIH V5D - 2 - V High-Level Input Voltage (GAIN1, GAIN0) V IH V5D - 0.8 - V Low-Level Input Voltage (MUTE, SLEEP, GAIN1, GAIN0) (Note 8) VIL -1 V Transition Time Between VIH and VIL (MUTE, SLEEP) (Note 8) tI - 500 ns High-Level Output Voltage (STATUS) I O =2 5 0μA VOH V5D - 0.5 - V Low-Level Output Voltage (STATUS) I O =2 5 0μA VOL -0 . 5 V Input Leakage Current (MUTE, SLEEP) I in -± 1 0 μA Input Leakage Current (GAIN1, GAIN0) I in -± 3 0 0 μA
The logic level for each input is set by its corresponding power supply and should not exceed the maximum ratings. Table 1. I/O Power Rails
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- TYPICAL CONNEC TION DIAGRAMS
Figure 1. Typical Connection Diagram - Stereo Amplifier with Differential Inputs
1 IN1+
32 IN1-
6 SLEEP
8 STATUS
27 AGND
24 IN2+
25 IN2-
28 V5A
29 BIASCAP
30 AGND
18 CPUMP
19 DCAP
23 AGND
2 V5D
5 REF
4 DGND
- See Section 4.11 for typical full-bridge output filter.
- Incorrectly connecting the external charge pump ci rcuitry can result in permanent damage to the device.
Figure 2. Typical Connection Diagram - Stereo Amplifier with Single-Ended Inputs
- See Section 4.11 for typical full-bridge output filter.
- Incorrectly connecting the external charge pump ci rcuitry can result in permanent damage to the device.
- See Section 4.1 for important information regarding using Single-Ended inputs with the CS3511.
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4.1 CS3511 Input Stage
one another from their source to the analog inputs of the CS3511. to Figure 3. The value of the resistor should match the output impedance of the audio source. Figure 3. CS3511 Input Stage
4.2 Dynamic DC Offset Calibration
abruptly from the steady-state DC offset voltage to 0 V. These abrupt changes are heard as a pop. ically minimized DC offset level before output switching is stopped.
4.3 CS3511 Amplifier Gain
The closed-loop gain of the CS3511 is externally configured via two input pins, GAIN0 and GAIN1. The “AC Electrical Characteristics” on page 7 shows the four different gain values available based on the pin voltag- es at GAIN0 and GAIN1. The GAIN0 and GAIN1 input pins have weak internal pull-down resistors; so they should be driven high when set to a logic high. Inter nally, different input resistor values are used to imple- ment the four gain settings. Thus, the input impedance will change based on the gain setting. The gain track- ing is very tightly matched within each device, but th e absolute input impedance will vary due to process variations. This variation must be considered when choosing the proper value of CI. The low-frequency roll- off characteristic is dedicated by the choice of CI and RI. The -3 dB frequency is: On the CRD3511, a value of 1.0 µF is used for CI; this value provides a nearly flat response down to 20 Hz, even for the highest gain setting. In many cases, a lower value of CI can be used due to a lower gain setting or because the speakers used do not have the ability to reproduce low-frequency signals.
4.4 MUTE Pin
The MUTE pin must be driven to a logic low or logic high state for proper operation. To enable the amplifier, connect the MUTE pin to a logic low. To enable the mute function, connect the MUTE pin to a logic high signal. When in mute, the internal processor bias voltages re main active in the CS3511 . This state maintains the bias on the input coupling capacitor to prevent audible transients which would be caused by the charging and discharging of this capacitor. It is recommended that the MUTE pin be held high during power-up or power-down to eliminate audible transients. If power-up and/or power-down pops are present with a CS3511 amplifier, the cause may be other circuitry external to the CS3511, such as an audio processor or preamp. If the CS3511 is in the active state (MUTE pin is low), these audible pops will be amplified and output to the speakers. To eliminate this problem, acti- vate the MUTE pin before the power supply collapses during a power-down sequence.
4.5 SLEEP Pin
When pulled high, the SLEEP pin puts the device into a low quiescent current mode. To disable sleep mode, the SLEEP pin should be grounded. While the device is in low power mode the STATUS pin will be in a logic high state to indicate that the device is not ready to produce audio.
4.6 Power Up and Power Down Sequence
To minimize power-on and power-off transients, the device should be held in the MUTE state while powering up or powering down the CS3511. The SLEEP pin can be held in either the logic high state or logic low state during power-up or power-down.
4.6.1 Recommended Power-Up Sequence
- Apply power to the system. 2. Hold the MUTE pin in the logic high state until the po wer supply is stable. In this state, all associated outputs are held in a high-impedance state. 3. Set the MUTE pin to a logic low state to begin no rmal operation. If the SLEEP pin is held high during power-on (optional), it should be set low before the MUTE pin is set low. fc - 3 dB = 1 2 π CI RI
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4.6.2 Recommended Power-Down Sequence
- Set the MUTE pin to the logic hi gh state. This will mute the amplifier outputs and hold them in a high- impedance state. 2. Optionally, the SLEEP pin can now be set to a logic high state to place the device into low power mode. 3. The power supplies can now be removed.
4.7 Protection Circuits
The CS3511 is protected against under-voltage, over -current, and over-temperature conditions. If one of these fault conditions are present the amplifier will be muted, the outputs will be tri-stated, and the STATUS pin will remain in a logic high state until the condition clears. The amplif ier will automatically attempt to re- cover from a detected fault condition.
4.7.1 Under-Voltage Protection
An under-voltage fault occurs if the voltage sensed on the VP terminals, the charge pump, or on V5A drops below the corresponding falling trigger point seen in the DC Electrical Characteristics table. The under-voltage fault will auto matically clear once the voltage exceed s the associated ri sing trigger point. V5GEN, V5A, and V5D must be connected together in order to properly monitor V5D and V5GEN. (See Figure 1 and Figure 2).
4.7.2 Over-Temperature Protection
An over-temperature fault occurs if the junction temperature of the device exceeds the rising junction ther- mal error trigger point seen in the AC Electrical Characteristics table. The thermal hysteresis of the device will cause the fault to automatically clear when the junction temperature drops below the falling junction thermal error trigger point.
4.7.3 Over-Current Protection
An over-current fault occurs if more current than the over-current error trigger point flows from any of the amplifier output pins, see AC Electrical Characteristics. Over current can occur if the speaker wires are shorted together, if one side of the speaker is shorted to ground, or if the speaker impedance is too low. WARNING: The outputs of the CS3511 should never be shorted to VP. Doing so can result in permanent damage to the device.
4.8 Integrated 5 V Regulator
The CS3511 includes an internal 5 V regulator in order to provide a supply to the internal digital and analog circuitry. The output of the regulator is present on the 5VGEN pin. The regulator output pin should have a bypass capacitor connected to AGND and be connected to the digita l and analog supply pins as shown in the Typical Connection Diagrams in Section 3. The regulator output can be used to set the SLEEP, MUTE, GAIN0, and GAIN1 pins to a logic high state. The re gulator is able to source the maximum current shown in the DC Electrical Characteristics table.
4.9 Power Dissipation De-Rating
As a result of high-efficiency and good package thermal characteristics, the CS3511 can operate at elevated ambient temperatures without having to de-rate the output power, assuming 8Ω output loads or higher. The exposed pad must be soldered to the PC Board to increase the maximum power dissipation capability of the CS3511 package. Soldering will minimize the likelihood of an over-temperature fault occurring during
formation on the thermal pad and Section 9.1 for more information on thermal dissipation for the CS3511.
4.10 Performance Measurements of the CS3511
the audio input signal, but it does introduce some inaudible components outside of the audio band. introduced by the CS3511 amplifier’s switching pattern will degrade the measurement result. bandwidth setting in the measurement instrument.
4.11 Full-Bridge Output Filter
speaker (load) impedance for a corner frequency (-3 dB point) of approximately 35 kHz. Table 2. Low-Pass Filter Components Figure 4. Output Filter
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- POWER SUPPLY, GROUNDING, AND PCB LAYOUT
5.1 Power Supply and Grounding
The CS3511 requires careful attention to power supply and grounding arrangements if its potential perfor- mance is to be realized. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. It is necessary to de-cou ple the power supply by placing capacitors directly between the power and ground of the CS3511. Decoupling capacitors should be as close to the pins of the CS3511 as possible. The lowest value ceramic capacitor should be closest to the pin and should be mount- ed on the same side of the board as the CS3511 to minimize inductance effects. The CRD3511 reference design demonstrates the optimum layout and power supply arrangements.
5.1.1 Maximum Supply Voltage
The absolute maximum allowable voltage on the VP supply pins (pins 10, 15 and 20) is shown in the Ab- solute Maximum Ratings table. Device damage can occur above this voltage. Please note that the abso- lute maximum voltage does not represent a valid operating condition. The maximum voltage on the VP pins during operation is shown in the Recommended Operating Conditions table. During normal operation, the output pins (pins 9, 12, 13, and 16) may experience overshoot voltages due to inductive kickback. Care should be taken to properly de-couple the VP pins because overshoot on the output pins can travel through the CS3511 output devices and appear on the VP pins. Without proper power supply decoupling, this can cause ripple voltages on the VP pins that might exceed their absolute maximum voltage shown in the Absolute Maximum Ratings table. However, this will only happen in ex- treme cases and can be prevented by placing the hi gh-frequency decoupling capacitors close to the VP pins.
5.2 QFN Thermal Pad
The CS3511 is available in a compact QFN package. The underside of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and mu st be electrically connected to PGND. A series of thermal vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers; the copper in these ground planes will act as a heat sink for the CS3511. The CRD3511 reference design demonstrates the optimum thermal pad and via configuration.
5.3 Layout Considerations
The CS3511 is a power (high current) amplifier that oper ates at relatively high switching frequencies. The outputs of the amplifier switch between the supply vo ltage and ground, at high speeds, while driving high currents. This high-frequency digital signal is passed through an LC low-pass filter to recover the amplified audio signal. Since the amplifier must drive the inducti ve LC output filter and speaker loads, the amplifier outputs can be pulled above the supply voltage and be low ground by the energy in the output inductance. Additionally, the CS3511’s junction temperature rises when supplying power to loads and relies on the PCB for heat sinking. To avoid subjecting the CS3511 to potentially damaging voltage stress and output-power-limiting elevated junction temperatures, it is critic al to have a good printed circuit board layout. It is strongly recommended that the Cirrus CRD3511 layout be used for all applications and only be deviated from after careful analysis of the effects of any changes. Please refer to Cirru s Logic application note AN315 for further information regarding the layout of the CS3511.
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Figure 11. Supply Current vs. POUT (RL= 8 Ω) Figure 12. Supply Current vs. POUT (RL= 6 Ω) Figure 13. THD+N vs. Frequency (RL= 8 Ω) Figure 14. THD+N vs. Frequency (RL= 6 Ω) Figure 15. Frequency Response (POUT = 1 W, RL= 8 Ω) Figure 16. Frequency Response (POUT = 1 W, RL= 6 Ω) and is optimized for an 8 Ω load.
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Figure 23. Efficiency (RL= 8 Ω) Figure 24. Efficiency (RL= 6 Ω)
- PARAMETER DEFINITIONS Signal to Noise Ratio (SNR) The ratio of the RMS value of the output signal, wher e Pout is equivalent to the specified output power at THD+N<1%, to the RMS value of the noise floor with no input signal applied and measured over the spec- ified bandwidth, typically 20 Hz to 20 kHz. Expressed in decibels. Dynamic Range (DYR) The ratio of the RMS value of the output signal produ ced when Pout is equivalen t to the specified output power at THD+N<1% to the RMS sum of all other spectral components over the specified bandwidth, typi- cally 20 Hz to 20 kHz. Dynamic Range is a signal-to -noise ratio measurement made with a -60 dBi input signal where dBi is referenced to the input signal amplitude resulting in the specified output power at THD+N<1%. This technique ensures that the distorti on components are below the noise level and do not effect the measurement. Expressed in decibels. Total Harmonic Distortion + Noise (THD+N) The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
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- PACKAGE DIMENSIONS 1. Dimensioning and tolerance per ASME Y 14.5M-1994. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A3 - 0.008 REF - - 0.203 REF - D - 0.2362 BSC - - 6.00 BSC - 1 E 0.2362 BSC 6.00 BSC 1 e 0.026 BSC 0.65 BSC 1 JEDEC #: MO-220 Controlling Dimension is Millimeters. Side View Bottom ViewTop View A Pin #1 Corner D E D2L b e Pin #1 Corner 32L QFN (6 X 6 mm BODY) PACKAGE DRAWING
- THERMAL CHARACTERISTICS
9.1 Thermal Flag
This device is designed to have the metal flag on the bottom of the device soldered directly to a metal plane on the PCB. To enhance the thermal dissipation capabilities of the system, this metal plane should be cou- pled with vias to a large metal plane on the backside (and inner ground layer, if applicable) of the PCB. In either case, it is beneficial to use copper fill in any unused regions inside the PCB layout, especially those immediately surrounding the CS3511. In addition to impr oving in electrical performance, this practice also aids in heat dissipation. The heat dissipation capabilit y required of the metal plane for a gi ven output power can be calculated as follows: θCA = [(TJ(MAX) - TA) / PD] - θJC where, θCA = Thermal resistance of the metal plane in °C/Watt TJ(MAX) = Maximum rated operating junction temperature in °C, equal to 150 °C TA = Ambient temperature in °C PD = RMS power dissipation of the device, equal to 0.176*PRMS-OUT (assuming 85% efficiency) θJC = Junction-to-case thermal resistance of the device in °C/Watt, equal to 1 °C/Watt Parameter Symbol Min Typ Max Units Junction to Case Thermal Impedance θJC -1 - ° C / W a t t
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10.ORDERING INFORMATION Product Description Package Pb-Free Grade Temp Range Container Order# CS3511 Stereo, 10W High-Efficiency Class-D Audio Amplifier 32-QFN Yes Commercial -10° to +70°C Rail CS3511-CNZ Tape and Reel CS3511-CNZR CRD3511-Q1 2x1 0W , 4L a y e r / 1o z . Copper Reference Design - - - - - CRD3511-Q1
11.REVISION HISTORY Release Changes A1 Initial Release A2 – Updated cover diagram. – Removed Dynamic Output Offs et Voltage specification. – Updated Section 4.2 on page 12. A3 – Updated PWM Output Over-Current specification in “AC Electrical Characteristics” table on page 7 and in the General Description on the front page. – FAULT pin (8) name updated to STATUS. – Updated Section 4.7 on page 14. – Updated “Under-Voltage Protection” table on page 14 and “DC Electrical Characteristics” table on page 8 from V5GEN to V5A for 5 V voltage sensing. – Updated Input Impedance specification in “AC Electrical Characteristics” table on page 7. PP1 – Updated front page Features and Common Applications. – Updated DC Power Supply specification in “Absolute Maximum Ratings” table on page 6. – Updated THD+N, Dynamic Range, SNR, PSRR, Channel Separation, Amplifier Gain, Gain Matching, and Efficiency specifications in “AC Electrical Characteristics” table on page 7. – Updated Sleep Supply Current, Mute Supply Curren t, Quiescent Current, 5VGEN Nominal Voltage, REF Nominal Voltage, and BIASCAP Nominal Voltage in “DC Electrical Characteristics” table on page 8. – Updated Leakage Current specification in “Digital Interface Specifications” table on page 8. – Updated the typical audio performance plots in Section 6. PP2 – Added SLEEP and MUTE pin transition ti me specification and information to the “DC Electrical Characteristics” table on page 8. – Updated the typical audio performance plots in Section 6. – Updated Input Impedance specifications in “AC Electrical Characteristics” table on page 7. – Updated front page Features, “AC Electrical Characteristics” table on page 7, and Section 4.3 to reference four GAIN settings.
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Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its sub- sidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of re levant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this informa- tion, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.