CS3310

CS3310 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

lComplete Digital Volume Control — 2 Independent Channels — Serial Control — 0.5 dB Step Size lWide Adjustable Range — -95.5 dB Attenuation — +31.5 dB Gain lLow Distortion & Noise — 0.001% THD+N — 116 dB Dynamic Range lNoise Free Level Transitions lChannel-to-Channel Crosstalk Better Than 110 dB

Description

The CS3310 is a complete stereo digital volume control designed specifically for audio systems. It features a 16- bit serial interface that controls two independent, low dis- tortion audio channels. The CS3310 includes an array of well-matched resistors and a low noise active output stage that is capable of driving a 600 W load. A total adjustable range of 127 dB, in 0.5 dB steps, is achieved through 95.5 dB of attenua- tion and 31.5 dB of gain. The simple 3-wire interface provides daisy-chaining of multiple CS3310's for multi-channel audio systems. The device operates from ±5 V supplies and has an in- put/output voltage range of ±3.75 V.

ORDERING INFORMATION

CS3310-KP 0° to 70° C 16-pin Plastic DIP CS3310-KS 0° to 70° C 16-pin Plastic SOIC I AINL AGNDL MUX AINR AGNDR MUX Control Register Serial to Parallel Register AOUTL14 MUTE8 ZCEN CS

3 SDATAI

7 SDATAO

6 SCLK

FEB ‘99 DS82PP3

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ANALOG CHARACTERISTICS (TA = 25 °C, VA+, VD+ = 5 V ± 5%; VA- = -5V ± 5%; Rs = 0; RL = 2k W ; CL = 20 pF; 10 Hz to 20 kHz Measurement Bandwidth; unless otherwise specified) Notes: 1. Measured with input grounded and Gain = 1. Will increase as a function of Gain settings >1. 2. This parameter is guaranteed by design and/or characterization. Parameter Symbol Min Typ Max Unit DC Characteristics Step Size - 0.5 - dB Gain Error (31.5 dB Gain) - –0.05 -d B Gain Matching Between Channels - –0.05 -d B Input Resistance R IN 81 0- k W Input Capacitance C IN -1 0- p F AC Characteristics Total Harmonic Distortion plus Noise (V in = 2V rms, 1 kHz) THD+N - 0.001 .0025 % Dynamic Range 110 116 - dB Input/Output Voltage Range (VA-)+1.25 - (VA+)-1.25 V Output Noise (Note 1) - 4.2 8.4 mVrms Digital Feedthrough (Peak Component) (Note 2) -80 - - dB Interchannel Isolation (1 kHz) (Note 2) -100 -110 - dB Output Buffer Offset Voltage (Note 1) V OS - 0.25 0.75 mV Load Capacitance - - 100 pF Short Circuit Current - 20 - mA Unity Gain Bandwidth, Small Signal (Note 2) 2 - - MHz Power Supplies Supply Current (No Load, AIN = 0 V) IA+ IA- ID+ 5.0 5.0 350 8.0 8.0 800 mA mA mA Power Consumption P D - 52.0 84.0 mW Power Supply Rejection Ratio (250 Hz) PSRR - 80 - dB

Figure 1. Serial Port Timing Diagram

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RECOMMENDED OPERATING CONDITIONS (DGND = 0V; all voltages with respect to ground) Notes: 3. Applying power to VD+ prior to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the recommended power connections. ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to ground.) Parameter Symbol Min Typ Max Unit DC Power Supplies: Positive Digital Positive Analog Negative Analog (VD+) - (VA+) (Note 3) VD+ VA+ VA 4.75 4.75 -4.75 -0.3 5.0 5.0 -5.0 VA+ 5.25 -5.25 0.0 V V V V Ambient Operating Temperature T A 02 5 7 0 °C Parameter Symbol Min Max Unit DC Power Supplies: Positive Digital Positive Analog Negative Analog VD+ VA+ VA- -0.3 -0.3 0.3 (VA+)+ 0.3 6.0 -6.0 V V V Input Current, Any Pin Except Supply I in - –10 mA Digital Input Voltage V IND -0.3 (VA+) + 0.3 V Ambient Operating Temperature (power applied) T A -55 +125 °C Storage Temperature T STG -65 +150 °C

Figure 2. Recommended Connection Diagram state of SDATAO when CS is high.

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bit adjustable range of 127 dB. daisy-chaining of multiple CS3310’s. put levels of both left and right channels are set. with the daisy-chaining capability of the CS3310. Figure 3. Serial Port Timing

register and out SDATAO during the process. function as well as the 18 ms time-out circuit. volts of the analog supply rails. short circuit protected to 20 mA. Figure 4. Daisy Chaining Diagram Table 1. Input Code Definition

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to prevent “clicks and pops” which occur with gain changes if an appreciable offset is present. Source Impedance Requirements The CS3310 requires a low source impedance to achieve maximum performance. The ESD protec- tion diodes on the analog input pins are reversed bi- ased during normal operation. A characteristic of a reversed biased diode is a non-linear voltage de- pendent capacitance which can be a source of dis- tortion if the source impedance becomes appreciable relative to the reversed biased diode capacitance. Source impedances equal to or less than 600 ohms will avoid this distortion mecha- nism for the CS3310. Mute Muting can be achieved by either hardware or soft- ware control. Hardware muting is accomplished via the MUTE input and software muting by load- ing all zeroes into the volume control register. MUTE disconnects the internal buffer amplifiers from the output pins and terminates AOUTL and AOUTR with 10 kW resistors to ground. The mute is activated with a zero crossing detection (inde- pendent of the zero cross enable status) or an 18 ms timeout to eliminate any audible “clicks” or “pops”. MUTE also initiates an internal offset cal- ibration. A software mute is implemented by loading all ze- roes into the volume control register. The internal amplifier is set to unity gain with the amplifier in- put connected to the maximum attenuation point of the resistive divider, AGND. A “soft mute” can be accomplished by sequentially ramping down from the current volume control set- ting to the maximum attenuation code of all zeroes. Power-Up Considerations Upon initial application of power, the MUTE pin of the CS3310 should be set low to initiate a power-up sequence. This sequence sets the serial shift regis- ter and the volume control register to zero and per- forms an offset calibration. The device should remain muted until the supply voltages have settled to ensure an accurate calibration. The device also includes an internal power-on reset circuit that re- quires approximately 100 µs to settle and will ig- nore any attempts to address the internal registers during this period. The offset calibration minimizes internally gener- ated offsets and ignores offsets applied to the AIN pins. External clocks are not required for calibra- tion. Although the device is tolerant to power supply variation, the device will enter a hardware mute state if the power supply voltage drops below ap- proximately –3.5 volts. A power-up sequence will be initiated if the power supply voltage returns to greater than –3.5 volts. Applying power to VD+ prior to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the recommended power connections. PCB Layout, Grounding and Power Supply Decoupling As with any high performance device which con- tains both analog and digital circuitry, careful at- tention to power supply and grounding arrangements must be observed to optimize perfor- mance. Figure 2 shows the recommended power arrangements with VA+ connected to a clean +5 volt supply and VA- connected to a clean -5 volt supply. VD+ powers the digital interface circuitry and should be powered from VA+, as shown in Fig- ure 2, to avoid potentially destructive SCR latch- up. Decoupling capacitors should be located as near to the CS3310 as possible, see Figure 5. The printed circuit board layout should have sepa- rate analog and digital regions with individual ground planes. The CS3310 should reside in the an- alog region as shown in Figure 5. Care should be taken to ensure that there is minimal resistance in

large reductions in radiated noise effects. CS3310 below 2.7 Vrms signal levels. crosstalk performance of the CS3310 at 20 kHz. nel to channel crosstalk of -130 dB at 20 kHz.

10 W 10 m F

Figure 5. Recommended 2-Layer PCB Layout

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Figure 6. THD+N vs. AMP Figure 7. 20 kHz Crosstalk Figure 8. Frequency Response Full Scale Input Figure 9. Frequency Response -20 dB Input

2.8 VRMS

1 VRMS

2 VRMS

Figure 10. THD+N vs. Frequency LOAD = 600 W , 2 kW , Figure 11. THD+N vs. Frequency Output levels of 1, 2,

V A+ - Positive Analog Power, Pin 12. Positive analog supply. Nominally +5 volts. V A- - Negative Analog Power, Pin 13. Negative analog supply. Nominally -5 volts. AGNDL - Left Channel Analog Ground, Pin 15. Analog ground reference for the left channel. AGNDR - Right Channel Analog Ground, Pin 10. Analog ground reference for the right channel. VD+ - Positive Digital Power, Pin 4. Positive supply for the digital section. Nominally +5 volts. Applying power to VD+ prior to V A+ creates a SCR latch-up condition. Refer to Figure 2 for the recommended power connections. DGND - Digital Ground, Pin 5. Digital ground for the digital section. Zero Crossing Enable ZCEN AINL Left Channel Input Chip Select CS AGNDL Left Analog Ground Serial Data InputSDATAI AOUTL Left Channel Output Positive Digital Power VD+ VA - Negative Analog Power Digital Ground DGND VA + Positive Analog Power Serial Clock Input SCLK AOUTR Right Channel Output Serial Data OutputSDATAO AGNDR Right Analog Ground Mute MUTE AINR Right Channel Input

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AINL, AINR - Left and Right Channel Analog Inputs, Pins 16, 9. Analog input connections for the left and right channels. Nominally ±3.75 volts for a full scale input. AOUTL, AOUTR - Left and Right Channel Analog Outputs, Pins 14, 11. Analog outputs for the left and right channels. Nominally ±3.75 volts for a full scale output. Digital Pins SDATAI - Serial Data Input, Pin 3. Serial input data that sets the analog output level of the left and right channels. The data is formatted in a 16-bit word. The first eight bits clocked into this pin control the analog output level for the right channel, and the second eight bits clocked into the device control the analog output level for the left channel. The data is clocked into the CS3310 by the rising edge of SCLK. SDATAO - Serial Data Output, Pin 7. Serial output data that provides daisy-chaining of multiple CS3310’s. This serial output will output the previous sixteen bits of volume control data that were clocked into the SDATAI pin. SDATAO will enter a High Impedance State when CS is High. SCLK - Serial Input Clock, Pin 6. Serial clock that clocks in the individual bits of serial data from the SDATAI pin. This clock is also used to clock out the individual bits from the SDATAO pin. The SDATAI data is latched on the rising edge, and SDATAO data is clocked out on the falling edge. CS - Chip Select, Pin 2. When high, the SDATAO output is held in a high impedance state. A falling transition defines the start of the 16-bit volume control word into the device. The 16-bit input data is latched into the control register on the rising edge of CS MUTE - Mute, Pin 8. Forces both the left and right analog output channels to ground. An offset calibration is initiated following the low transition of MUTE. Calibration requires a minimum mute period of 2m s . ZCEN - Zero Crossing Enable, Pin 1. This pin enables or disables the zero crossing detection and time-out function used during analog output level transitions. A high level on this pin enables the zero crossing detection function. A low level on this pin disables the zero crossing detection.

Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured over the specified bandwidth with the input grounded. Units in decibels. Total Harmonic Distortion plus Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with the input under test grounded and a full-scale signal applied to the other channel. Units in decibels.

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A 0.000 0.210 0.00 5.33 A1 0.015 0.025 0.38 0.64 A2 0.115 0.195 2.92 4.95 b 0.014 0.022 0.36 0.56 b1 0.045 0.070 1.14 1.78 c 0.008 0.014 0.20 0.36 D 0.780 0.800 19.81 20.32 E 0.300 0.325 7.62 8.26 E1 0.240 0.280 6.10 7.11 e 0.090 0.110 2.29 2.79 eA 0.280 0.320 7.11 8.13 eB 0.300 0.430 7.62 10.92 eC 0.000 0.060 0.00 1.52 L 0.115 0.150 2.92 3.81 µ 0° 15° 0° 15°

16 PIN PLASTIC (PDIP) PACKAGE DRAWING

D SEATING PLANE e b A LA1 µ TOP VIEW BOTTOM VIEW SIDE VIEW eA c E eC eB

A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.398 0.413 10.10 10.50 E 0.291 0.299 7.40 7.60 e 0.040 0.060 1.02 1.52 H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 µ 0° 8° 0° 8° JEDEC #: MS-013 e 16L SOIC (300 MIL BODY) PACKAGE DRAWING D HE b A c L µSEATING PLANE

• •Demonstrates recommended layout and grounding arrangements
• •On-board or externally supplied system control
• •Buffered PC Control Interface
• •Digital and Analog Patch Areas General Description The CDB3310 evaluation board allows fast evaluation of the CS3310 stereo digital volume control. The board generates all control signals. Evaluation requires a low- distortion signal source and a power supply. The evaluation board may be configured to accept ex- ternal timing signals for operation in a user application during system development. The CDB3310 also pro- vides a PC compatible control port for user software development. Analog inputs and outputs are standard RCA phono plugs. ORDERING INFORMATION: CDB3310 SEPT ’93 DS82DB1 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445 7222 Fax: (512) 445 7581 Evaluation Board for CS3310 Semiconductor Corporation CDB3310 +5V GND -5V AINR AINL Microcontroller PC Control Port Power Supply Conditioning Analog Patch Area Digital Patch Area CS3310 AOUTR AOUTL CS SDATAI SCLK SDATAO Copyright  Crystal Semiconductor Corporation 1993 (All Rights Reserved)

• Notes •

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Fur- thermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.